src/mem/cache/write_queue.cc

   1 /*
   2  * Copyright (c) 2012-2013, 2015-2016 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  *          Andreas Sandberg
  42  *          Andreas Hansson
  43  */
  44
  45 /** @file
  46  * Definition of WriteQueue class functions.
  47  */
  48
  49 #include "mem/cache/write_queue.hh"
  50
  51 using namespace std;
  52
  53 WriteQueue::WriteQueue(const std::string &_label,
  54                        int num_entries, int reserve)
  55     : Queue<WriteQueueEntry>(_label, num_entries, reserve)
  56 {}
  57
  58 WriteQueueEntry *
  59 WriteQueue::allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
  60                     Tick when_ready, Counter order)
  61 {
  62     assert(!freeList.empty());
  63     WriteQueueEntry *entry = freeList.front();
  64     assert(entry->getNumTargets() == 0);
  65     freeList.pop_front();
  66
  67     entry->allocate(blk_addr, blk_size, pkt, when_ready, order);
  68     entry->allocIter = allocatedList.insert(allocatedList.end(), entry);
  69     entry->readyIter = addToReadyList(entry);
  70
  71     allocated += 1;
  72     return entry;
  73 }
  74
  75 void
  76 WriteQueue::markInService(WriteQueueEntry *entry)
  77 {
  78     // for a normal eviction, such as a writeback or a clean evict,
  79     // there is no more to do as we are done from the perspective of
  80     // this cache, and for uncacheable write we do not need the entry
  81     // as part of the response handling
  82     entry->popTarget();
  83     deallocate(entry);
  84 }