src/mem/cache/write_queue_entry.cc

   1 /*
   2  * Copyright (c) 2012-2013, 2015-2017 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2010 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Erik Hallnor
  42  *          Dave Greene
  43  *          Andreas Hansson
  44  */
  45
  46 /**
  47  * @file
  48  * Miss Status and Handling Register (WriteQueueEntry) definitions.
  49  */
  50
  51 #include "mem/cache/write_queue_entry.hh"
  52
  53 #include <cassert>
  54 #include <string>
  55
  56 #include "base/logging.hh"
  57 #include "base/types.hh"
  58 #include "mem/cache/base.hh"
  59 #include "mem/request.hh"
  60
  61 inline void
  62 WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
  63                                  Counter order)
  64 {
  65     emplace_back(pkt, readyTime, order);
  66 }
  67
  68 bool
  69 WriteQueueEntry::TargetList::trySatisfyFunctional(PacketPtr pkt)
  70 {
  71     for (auto& t : *this) {
  72         if (pkt->trySatisfyFunctional(t.pkt)) {
  73             return true;
  74         }
  75     }
  76
  77     return false;
  78 }
  79
  80 void
  81 WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
  82                                    const std::string &prefix) const
  83 {
  84     for (auto& t : *this) {
  85         ccprintf(os, "%sFromCPU: ", prefix);
  86         t.pkt->print(os, verbosity, "");
  87     }
  88 }
  89
  90 void
  91 WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
  92                           Tick when_ready, Counter _order)
  93 {
  94     blkAddr = blk_addr;
  95     blkSize = blk_size;
  96     isSecure = target->isSecure();
  97     readyTime = when_ready;
  98     order = _order;
  99     assert(target);
 100     _isUncacheable = target->req->isUncacheable();
 101     inService = false;
 102
 103     // we should never have more than a single target for cacheable
 104     // writes (writebacks and clean evictions)
 105     panic_if(!_isUncacheable && !targets.empty(),
 106              "Write queue entry %#llx should never have more than one "
 107              "cacheable target", blkAddr);
 108     panic_if(!((target->isWrite() && _isUncacheable) ||
 109                (target->isEviction() && !_isUncacheable) ||
 110                target->cmd == MemCmd::WriteClean),
 111              "Write queue entry %#llx should be an uncacheable write or "
 112              "a cacheable eviction or a writeclean");
 113
 114     targets.add(target, when_ready, _order);
 115
 116     // All targets must refer to the same block
 117     assert(target->matchBlockAddr(targets.front().pkt, blkSize));
 118 }
 119
 120 void
 121 WriteQueueEntry::deallocate()
 122 {
 123     assert(targets.empty());
 124     inService = false;
 125 }
 126
 127 bool
 128 WriteQueueEntry::trySatisfyFunctional(PacketPtr pkt)
 129 {
 130     // For printing, we treat the WriteQueueEntry as a whole as single
 131     // entity. For other requests, we iterate over the individual
 132     // targets since that's where the actual data lies.
 133     if (pkt->isPrint()) {
 134         pkt->trySatisfyFunctional(this, blkAddr, isSecure, blkSize, nullptr);
 135         return false;
 136     } else {
 137         return targets.trySatisfyFunctional(pkt);
 138     }
 139 }
 140
 141 bool
 142 WriteQueueEntry::sendPacket(BaseCache &cache)
 143 {
 144     return cache.sendWriteQueuePacket(this);
 145 }
 146
 147 bool
 148 WriteQueueEntry::matchBlockAddr(const Addr addr, const bool is_secure) const
 149 {
 150     assert(hasTargets());
 151     return (blkAddr == addr) && (isSecure == is_secure);
 152 }
 153
 154 bool
 155 WriteQueueEntry::matchBlockAddr(const PacketPtr pkt) const
 156 {
 157     assert(hasTargets());
 158     return pkt->matchBlockAddr(blkAddr, isSecure, blkSize);
 159 }
 160
 161 bool
 162 WriteQueueEntry::conflictAddr(const QueueEntry* entry) const
 163 {
 164     assert(hasTargets());
 165     return entry->matchBlockAddr(blkAddr, isSecure);
 166 }
 167
 168 void
 169 WriteQueueEntry::print(std::ostream &os, int verbosity,
 170                        const std::string &prefix) const
 171 {
 172     ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
 173              prefix, blkAddr, blkAddr + blkSize - 1,
 174              isSecure ? "s" : "ns",
 175              _isUncacheable ? "Unc" : "",
 176              inService ? "InSvc" : "");
 177
 178     ccprintf(os, "%s  Targets:\n", prefix);
 179     targets.print(os, verbosity, prefix + "    ");
 180 }
 181
 182 std::string
 183 WriteQueueEntry::print() const
 184 {
 185     std::ostringstream str;
 186     print(str);
 187     return str.str();
 188 }