src/mem/cache/write_queue_entry.cc

   1 /*
   2  * Copyright (c) 2012-2013, 2015-2016 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2010 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Erik Hallnor
  42  *          Dave Greene
  43  *          Andreas Hansson
  44  */
  45
  46 /**
  47  * @file
  48  * Miss Status and Handling Register (WriteQueueEntry) definitions.
  49  */
  50
  51 #include "mem/cache/write_queue_entry.hh"
  52
  53 #include <algorithm>
  54 #include <cassert>
  55 #include <string>
  56 #include <vector>
  57
  58 #include "base/misc.hh"
  59 #include "base/types.hh"
  60 #include "debug/Cache.hh"
  61 #include "mem/cache/cache.hh"
  62 #include "sim/core.hh"
  63
  64 using namespace std;
  65
  66 inline void
  67 WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
  68                                  Counter order)
  69 {
  70     emplace_back(pkt, readyTime, order);
  71 }
  72
  73 bool
  74 WriteQueueEntry::TargetList::checkFunctional(PacketPtr pkt)
  75 {
  76     for (auto& t : *this) {
  77         if (pkt->checkFunctional(t.pkt)) {
  78             return true;
  79         }
  80     }
  81
  82     return false;
  83 }
  84
  85 void
  86 WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
  87                                    const std::string &prefix) const
  88 {
  89     for (auto& t : *this) {
  90         ccprintf(os, "%sFromCPU: ", prefix);
  91         t.pkt->print(os, verbosity, "");
  92     }
  93 }
  94
  95 void
  96 WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
  97                           Tick when_ready, Counter _order)
  98 {
  99     blkAddr = blk_addr;
 100     blkSize = blk_size;
 101     isSecure = target->isSecure();
 102     readyTime = when_ready;
 103     order = _order;
 104     assert(target);
 105     _isUncacheable = target->req->isUncacheable();
 106     inService = false;
 107
 108     // we should never have more than a single target for cacheable
 109     // writes (writebacks and clean evictions)
 110     panic_if(!_isUncacheable && !targets.empty(),
 111              "Write queue entry %#llx should never have more than one "
 112              "cacheable target", blkAddr);
 113     panic_if(!((target->isWrite() && _isUncacheable) ||
 114                (target->isEviction() && !_isUncacheable)),
 115              "Write queue entry %#llx should either be uncacheable write or "
 116              "a cacheable eviction");
 117
 118     targets.add(target, when_ready, _order);
 119 }
 120
 121 bool
 122 WriteQueueEntry::markInService()
 123 {
 124     assert(!inService);
 125     if (!isUncacheable()) {
 126         // we just forwarded the request packet & don't expect a
 127         // response, so get rid of it
 128         assert(getNumTargets() == 1);
 129         popTarget();
 130         return true;
 131     }
 132
 133     inService = true;
 134
 135     return false;
 136 }
 137
 138 void
 139 WriteQueueEntry::deallocate()
 140 {
 141     assert(targets.empty());
 142     inService = false;
 143 }
 144
 145 bool
 146 WriteQueueEntry::checkFunctional(PacketPtr pkt)
 147 {
 148     // For printing, we treat the WriteQueueEntry as a whole as single
 149     // entity. For other requests, we iterate over the individual
 150     // targets since that's where the actual data lies.
 151     if (pkt->isPrint()) {
 152         pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL);
 153         return false;
 154     } else {
 155         return targets.checkFunctional(pkt);
 156     }
 157 }
 158
 159 bool
 160 WriteQueueEntry::sendPacket(Cache &cache)
 161 {
 162     return cache.sendWriteQueuePacket(this);
 163 }
 164
 165 void
 166 WriteQueueEntry::print(std::ostream &os, int verbosity,
 167                        const std::string &prefix) const
 168 {
 169     ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
 170              prefix, blkAddr, blkAddr + blkSize - 1,
 171              isSecure ? "s" : "ns",
 172              _isUncacheable ? "Unc" : "",
 173              inService ? "InSvc" : "");
 174
 175     ccprintf(os, "%s  Targets:\n", prefix);
 176     targets.print(os, verbosity, prefix + "    ");
 177 }
 178
 179 std::string
 180 WriteQueueEntry::print() const
 181 {
 182     ostringstream str;
 183     print(str);
 184     return str.str();
 185 }