src/mem/coherent_bus.hh

   1 /*
   2  * Copyright (c) 2011-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  *          William Wang
  44  */
  45
  46 /**
  47  * @file
  48  * Declaration of a coherent bus.
  49  */
  50
  51 #ifndef __MEM_COHERENT_BUS_HH__
  52 #define __MEM_COHERENT_BUS_HH__
  53
  54 #include "mem/bus.hh"
  55 #include "params/CoherentBus.hh"
  56
  57 /**
  58  * A coherent bus connects a number of (potentially) snooping masters
  59  * and slaves, and routes the request and response packets based on
  60  * the address, and also forwards all requests to the snoopers and
  61  * deals with the snoop responses.
  62  *
  63  * The coherent bus can be used as a template for modelling QPI,
  64 * HyperTransport, ACE and coherent OCP buses, and is typically used
  65  * for the L1-to-L2 buses and as the main system interconnect.
  66  * @sa  \ref gem5MemorySystem "gem5 Memory System"
  67  */
  68 class CoherentBus : public BaseBus
  69 {
  70
  71   protected:
  72
  73     /**
  74      * Declare the three layers of this bus, one for requests, one
  75      * for responses, and one for snoop responses
  76      */
  77     Layer<SlavePort> reqLayer;
  78     Layer<MasterPort> respLayer;
  79     Layer<SlavePort> snoopRespLayer;
  80
  81     /**
  82      * Declaration of the coherent bus slave port type, one will be
  83      * instantiated for each of the master ports connecting to the
  84      * bus.
  85      */
  86     class CoherentBusSlavePort : public SlavePort
  87     {
  88
  89       private:
  90
  91         /** A reference to the bus to which this port belongs. */
  92         CoherentBus &bus;
  93
  94       public:
  95
  96         CoherentBusSlavePort(const std::string &_name,
  97                              CoherentBus &_bus, PortID _id)
  98             : SlavePort(_name, &_bus, _id), bus(_bus)
  99         { }
 100
 101       protected:
 102
 103         /**
 104          * When receiving a timing request, pass it to the bus.
 105          */
 106         virtual bool recvTimingReq(PacketPtr pkt)
 107         { return bus.recvTimingReq(pkt, id); }
 108
 109         /**
 110          * When receiving a timing snoop response, pass it to the bus.
 111          */
 112         virtual bool recvTimingSnoopResp(PacketPtr pkt)
 113         { return bus.recvTimingSnoopResp(pkt, id); }
 114
 115         /**
 116          * When receiving an atomic request, pass it to the bus.
 117          */
 118         virtual Tick recvAtomic(PacketPtr pkt)
 119         { return bus.recvAtomic(pkt, id); }
 120
 121         /**
 122          * When receiving a functional request, pass it to the bus.
 123          */
 124         virtual void recvFunctional(PacketPtr pkt)
 125         { bus.recvFunctional(pkt, id); }
 126
 127         /**
 128          * When receiving a retry, pass it to the bus.
 129          */
 130         virtual void recvRetry()
 131         { panic("Bus slave ports always succeed and should never retry.\n"); }
 132
 133         /**
 134          * Return the union of all adress ranges seen by this bus.
 135          */
 136         virtual AddrRangeList getAddrRanges() const
 137         { return bus.getAddrRanges(); }
 138
 139         /**
 140          * Get the maximum block size as seen by the bus.
 141          */
 142         virtual unsigned deviceBlockSize() const
 143         { return bus.deviceBlockSize(); }
 144
 145     };
 146
 147     /**
 148      * Declaration of the coherent bus master port type, one will be
 149      * instantiated for each of the slave interfaces connecting to the
 150      * bus.
 151      */
 152     class CoherentBusMasterPort : public MasterPort
 153     {
 154       private:
 155         /** A reference to the bus to which this port belongs. */
 156         CoherentBus &bus;
 157
 158       public:
 159
 160         CoherentBusMasterPort(const std::string &_name,
 161                               CoherentBus &_bus, PortID _id)
 162             : MasterPort(_name, &_bus, _id), bus(_bus)
 163         { }
 164
 165       protected:
 166
 167         /**
 168          * Determine if this port should be considered a snooper. For
 169          * a coherent bus master port this is always true.
 170          *
 171          * @return a boolean that is true if this port is snooping
 172          */
 173         virtual bool isSnooping() const
 174         { return true; }
 175
 176         /**
 177          * When receiving a timing response, pass it to the bus.
 178          */
 179         virtual bool recvTimingResp(PacketPtr pkt)
 180         { return bus.recvTimingResp(pkt, id); }
 181
 182         /**
 183          * When receiving a timing snoop request, pass it to the bus.
 184          */
 185         virtual void recvTimingSnoopReq(PacketPtr pkt)
 186         { return bus.recvTimingSnoopReq(pkt, id); }
 187
 188         /**
 189          * When receiving an atomic snoop request, pass it to the bus.
 190          */
 191         virtual Tick recvAtomicSnoop(PacketPtr pkt)
 192         { return bus.recvAtomicSnoop(pkt, id); }
 193
 194         /**
 195          * When receiving a functional snoop request, pass it to the bus.
 196          */
 197         virtual void recvFunctionalSnoop(PacketPtr pkt)
 198         { bus.recvFunctionalSnoop(pkt, id); }
 199
 200         /** When reciving a range change from the peer port (at id),
 201             pass it to the bus. */
 202         virtual void recvRangeChange()
 203         { bus.recvRangeChange(id); }
 204
 205         /** When reciving a retry from the peer port (at id),
 206             pass it to the bus. */
 207         virtual void recvRetry()
 208         { bus.recvRetry(id); }
 209
 210         // Ask the bus to ask everyone on the bus what their block size is and
 211         // take the max of it. This might need to be changed a bit if we ever
 212         // support multiple block sizes.
 213         virtual unsigned deviceBlockSize() const
 214         { return bus.deviceBlockSize(); }
 215
 216     };
 217
 218     std::vector<SlavePort*> snoopPorts;
 219
 220     /**
 221      * Store the outstanding requests so we can determine which ones
 222      * we generated and which ones were merely forwarded. This is used
 223      * in the coherent bus when coherency responses come back.
 224      */
 225     std::set<RequestPtr> outstandingReq;
 226
 227     /**
 228      * Keep a pointer to the system to be allow to querying memory system
 229      * properties.
 230      */
 231     System *system;
 232
 233     /** Function called by the port when the bus is recieving a Timing
 234       request packet.*/
 235     virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
 236
 237     /** Function called by the port when the bus is recieving a Timing
 238       response packet.*/
 239     virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
 240
 241     /** Function called by the port when the bus is recieving a timing
 242         snoop request.*/
 243     virtual void recvTimingSnoopReq(PacketPtr pkt, PortID master_port_id);
 244
 245     /** Function called by the port when the bus is recieving a timing
 246         snoop response.*/
 247     virtual bool recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id);
 248
 249     /** Timing function called by port when it is once again able to process
 250      * requests. */
 251     void recvRetry(PortID master_port_id);
 252
 253     /**
 254      * Forward a timing packet to our snoopers, potentially excluding
 255      * one of the connected coherent masters to avoid sending a packet
 256      * back to where it came from.
 257      *
 258      * @param pkt Packet to forward
 259      * @param exclude_slave_port_id Id of slave port to exclude
 260      */
 261     void forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id);
 262
 263     /** Function called by the port when the bus is recieving a Atomic
 264       transaction.*/
 265     Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
 266
 267     /** Function called by the port when the bus is recieving an
 268         atomic snoop transaction.*/
 269     Tick recvAtomicSnoop(PacketPtr pkt, PortID master_port_id);
 270
 271     /**
 272      * Forward an atomic packet to our snoopers, potentially excluding
 273      * one of the connected coherent masters to avoid sending a packet
 274      * back to where it came from.
 275      *
 276      * @param pkt Packet to forward
 277      * @param exclude_slave_port_id Id of slave port to exclude
 278      *
 279      * @return a pair containing the snoop response and snoop latency
 280      */
 281     std::pair<MemCmd, Tick> forwardAtomic(PacketPtr pkt,
 282                                           PortID exclude_slave_port_id);
 283
 284     /** Function called by the port when the bus is recieving a Functional
 285         transaction.*/
 286     void recvFunctional(PacketPtr pkt, PortID slave_port_id);
 287
 288     /** Function called by the port when the bus is recieving a functional
 289         snoop transaction.*/
 290     void recvFunctionalSnoop(PacketPtr pkt, PortID master_port_id);
 291
 292     /**
 293      * Forward a functional packet to our snoopers, potentially
 294      * excluding one of the connected coherent masters to avoid
 295      * sending a packet back to where it came from.
 296      *
 297      * @param pkt Packet to forward
 298      * @param exclude_slave_port_id Id of slave port to exclude
 299      */
 300     void forwardFunctional(PacketPtr pkt, PortID exclude_slave_port_id);
 301
 302   public:
 303
 304     virtual void init();
 305
 306     CoherentBus(const CoherentBusParams *p);
 307
 308     unsigned int drain(DrainManager *dm);
 309 };
 310
 311 #endif //__MEM_COHERENT_BUS_HH__