src/mem/coherent_bus.hh

   1 /*
   2  * Copyright (c) 2011-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  *          William Wang
  44  */
  45
  46 /**
  47  * @file
  48  * Declaration of a coherent bus.
  49  */
  50
  51 #ifndef __MEM_COHERENT_BUS_HH__
  52 #define __MEM_COHERENT_BUS_HH__
  53
  54 #include "mem/bus.hh"
  55 #include "params/CoherentBus.hh"
  56
  57 /**
  58  * A coherent bus connects a number of (potentially) snooping masters
  59  * and slaves, and routes the request and response packets based on
  60  * the address, and also forwards all requests to the snoopers and
  61  * deals with the snoop responses.
  62  *
  63  * The coherent bus can be used as a template for modelling QPI,
  64 * HyperTransport, ACE and coherent OCP buses, and is typically used
  65  * for the L1-to-L2 buses and as the main system interconnect.
  66  */
  67 class CoherentBus : public BaseBus
  68 {
  69
  70   protected:
  71
  72     /**
  73      * Declare the three layers of this bus, one for requests, one
  74      * for responses, and one for snoop responses
  75      */
  76     Layer<SlavePort> reqLayer;
  77     Layer<MasterPort> respLayer;
  78     Layer<SlavePort> snoopRespLayer;
  79
  80     /**
  81      * Declaration of the coherent bus slave port type, one will be
  82      * instantiated for each of the master ports connecting to the
  83      * bus.
  84      */
  85     class CoherentBusSlavePort : public SlavePort
  86     {
  87
  88       private:
  89
  90         /** A reference to the bus to which this port belongs. */
  91         CoherentBus &bus;
  92
  93       public:
  94
  95         CoherentBusSlavePort(const std::string &_name,
  96                              CoherentBus &_bus, PortID _id)
  97             : SlavePort(_name, &_bus, _id), bus(_bus)
  98         { }
  99
 100       protected:
 101
 102         /**
 103          * When receiving a timing request, pass it to the bus.
 104          */
 105         virtual bool recvTimingReq(PacketPtr pkt)
 106         { return bus.recvTimingReq(pkt, id); }
 107
 108         /**
 109          * When receiving a timing snoop response, pass it to the bus.
 110          */
 111         virtual bool recvTimingSnoopResp(PacketPtr pkt)
 112         { return bus.recvTimingSnoopResp(pkt, id); }
 113
 114         /**
 115          * When receiving an atomic request, pass it to the bus.
 116          */
 117         virtual Tick recvAtomic(PacketPtr pkt)
 118         { return bus.recvAtomic(pkt, id); }
 119
 120         /**
 121          * When receiving a functional request, pass it to the bus.
 122          */
 123         virtual void recvFunctional(PacketPtr pkt)
 124         { bus.recvFunctional(pkt, id); }
 125
 126         /**
 127          * When receiving a retry, pass it to the bus.
 128          */
 129         virtual void recvRetry()
 130         { panic("Bus slave ports always succeed and should never retry.\n"); }
 131
 132         /**
 133          * Return the union of all adress ranges seen by this bus.
 134          */
 135         virtual AddrRangeList getAddrRanges() const
 136         { return bus.getAddrRanges(); }
 137
 138         /**
 139          * Get the maximum block size as seen by the bus.
 140          */
 141         virtual unsigned deviceBlockSize() const
 142         { return bus.findBlockSize(); }
 143
 144     };
 145
 146     /**
 147      * Declaration of the coherent bus master port type, one will be
 148      * instantiated for each of the slave interfaces connecting to the
 149      * bus.
 150      */
 151     class CoherentBusMasterPort : public MasterPort
 152     {
 153       private:
 154         /** A reference to the bus to which this port belongs. */
 155         CoherentBus &bus;
 156
 157       public:
 158
 159         CoherentBusMasterPort(const std::string &_name,
 160                               CoherentBus &_bus, PortID _id)
 161             : MasterPort(_name, &_bus, _id), bus(_bus)
 162         { }
 163
 164       protected:
 165
 166         /**
 167          * Determine if this port should be considered a snooper. For
 168          * a coherent bus master port this is always true.
 169          *
 170          * @return a boolean that is true if this port is snooping
 171          */
 172         virtual bool isSnooping() const
 173         { return true; }
 174
 175         /**
 176          * When receiving a timing response, pass it to the bus.
 177          */
 178         virtual bool recvTimingResp(PacketPtr pkt)
 179         { return bus.recvTimingResp(pkt, id); }
 180
 181         /**
 182          * When receiving a timing snoop request, pass it to the bus.
 183          */
 184         virtual void recvTimingSnoopReq(PacketPtr pkt)
 185         { return bus.recvTimingSnoopReq(pkt, id); }
 186
 187         /**
 188          * When receiving an atomic snoop request, pass it to the bus.
 189          */
 190         virtual Tick recvAtomicSnoop(PacketPtr pkt)
 191         { return bus.recvAtomicSnoop(pkt, id); }
 192
 193         /**
 194          * When receiving a functional snoop request, pass it to the bus.
 195          */
 196         virtual void recvFunctionalSnoop(PacketPtr pkt)
 197         { bus.recvFunctionalSnoop(pkt, id); }
 198
 199         /** When reciving a range change from the peer port (at id),
 200             pass it to the bus. */
 201         virtual void recvRangeChange()
 202         { bus.recvRangeChange(id); }
 203
 204         /** When reciving a retry from the peer port (at id),
 205             pass it to the bus. */
 206         virtual void recvRetry()
 207         { bus.recvRetry(); }
 208
 209         // Ask the bus to ask everyone on the bus what their block size is and
 210         // take the max of it. This might need to be changed a bit if we ever
 211         // support multiple block sizes.
 212         virtual unsigned deviceBlockSize() const
 213         { return bus.findBlockSize(); }
 214
 215     };
 216
 217     std::vector<SlavePort*> snoopPorts;
 218
 219     /**
 220      * Store the outstanding requests so we can determine which ones
 221      * we generated and which ones were merely forwarded. This is used
 222      * in the coherent bus when coherency responses come back.
 223      */
 224     std::set<RequestPtr> outstandingReq;
 225
 226     /** Function called by the port when the bus is recieving a Timing
 227       request packet.*/
 228     virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
 229
 230     /** Function called by the port when the bus is recieving a Timing
 231       response packet.*/
 232     virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
 233
 234     /** Function called by the port when the bus is recieving a timing
 235         snoop request.*/
 236     virtual void recvTimingSnoopReq(PacketPtr pkt, PortID master_port_id);
 237
 238     /** Function called by the port when the bus is recieving a timing
 239         snoop response.*/
 240     virtual bool recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id);
 241
 242     /** Timing function called by port when it is once again able to process
 243      * requests. */
 244     void recvRetry();
 245
 246     /**
 247      * Forward a timing packet to our snoopers, potentially excluding
 248      * one of the connected coherent masters to avoid sending a packet
 249      * back to where it came from.
 250      *
 251      * @param pkt Packet to forward
 252      * @param exclude_slave_port_id Id of slave port to exclude
 253      */
 254     void forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id);
 255
 256     /** Function called by the port when the bus is recieving a Atomic
 257       transaction.*/
 258     Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
 259
 260     /** Function called by the port when the bus is recieving an
 261         atomic snoop transaction.*/
 262     Tick recvAtomicSnoop(PacketPtr pkt, PortID master_port_id);
 263
 264     /**
 265      * Forward an atomic packet to our snoopers, potentially excluding
 266      * one of the connected coherent masters to avoid sending a packet
 267      * back to where it came from.
 268      *
 269      * @param pkt Packet to forward
 270      * @param exclude_slave_port_id Id of slave port to exclude
 271      *
 272      * @return a pair containing the snoop response and snoop latency
 273      */
 274     std::pair<MemCmd, Tick> forwardAtomic(PacketPtr pkt,
 275                                           PortID exclude_slave_port_id);
 276
 277     /** Function called by the port when the bus is recieving a Functional
 278         transaction.*/
 279     void recvFunctional(PacketPtr pkt, PortID slave_port_id);
 280
 281     /** Function called by the port when the bus is recieving a functional
 282         snoop transaction.*/
 283     void recvFunctionalSnoop(PacketPtr pkt, PortID master_port_id);
 284
 285     /**
 286      * Forward a functional packet to our snoopers, potentially
 287      * excluding one of the connected coherent masters to avoid
 288      * sending a packet back to where it came from.
 289      *
 290      * @param pkt Packet to forward
 291      * @param exclude_slave_port_id Id of slave port to exclude
 292      */
 293     void forwardFunctional(PacketPtr pkt, PortID exclude_slave_port_id);
 294
 295   public:
 296
 297     virtual void init();
 298
 299     CoherentBus(const CoherentBusParams *p);
 300
 301     unsigned int drain(Event *de);
 302 };
 303
 304 #endif //__MEM_COHERENT_BUS_HH__