src/mem/coherent_bus.hh

   1 /*
   2  * Copyright (c) 2011-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  *          William Wang
  44  */
  45
  46 /**
  47  * @file
  48  * Declaration of a coherent bus.
  49  */
  50
  51 #ifndef __MEM_COHERENT_BUS_HH__
  52 #define __MEM_COHERENT_BUS_HH__
  53
  54 #include "mem/bus.hh"
  55 #include "params/CoherentBus.hh"
  56
  57 /**
  58  * A coherent bus connects a number of (potentially) snooping masters
  59  * and slaves, and routes the request and response packets based on
  60  * the address, and also forwards all requests to the snoopers and
  61  * deals with the snoop responses.
  62  *
  63  * The coherent bus can be used as a template for modelling QPI,
  64 * HyperTransport, ACE and coherent OCP buses, and is typically used
  65  * for the L1-to-L2 buses and as the main system interconnect.
  66  */
  67 class CoherentBus : public BaseBus
  68 {
  69
  70   protected:
  71
  72     /**
  73      * Declaration of the coherent bus slave port type, one will be
  74      * instantiated for each of the master ports connecting to the
  75      * bus.
  76      */
  77     class CoherentBusSlavePort : public SlavePort
  78     {
  79
  80       private:
  81
  82         /** A reference to the bus to which this port belongs. */
  83         CoherentBus &bus;
  84
  85       public:
  86
  87         CoherentBusSlavePort(const std::string &_name,
  88                              CoherentBus &_bus, PortID _id)
  89             : SlavePort(_name, &_bus, _id), bus(_bus)
  90         { }
  91
  92       protected:
  93
  94         /**
  95          * When receiving a timing request, pass it to the bus.
  96          */
  97         virtual bool recvTimingReq(PacketPtr pkt)
  98         { return bus.recvTimingReq(pkt, id); }
  99
 100         /**
 101          * When receiving a timing snoop response, pass it to the bus.
 102          */
 103         virtual bool recvTimingSnoopResp(PacketPtr pkt)
 104         { return bus.recvTimingSnoopResp(pkt, id); }
 105
 106         /**
 107          * When receiving an atomic request, pass it to the bus.
 108          */
 109         virtual Tick recvAtomic(PacketPtr pkt)
 110         { return bus.recvAtomic(pkt, id); }
 111
 112         /**
 113          * When receiving a functional request, pass it to the bus.
 114          */
 115         virtual void recvFunctional(PacketPtr pkt)
 116         { bus.recvFunctional(pkt, id); }
 117
 118         /**
 119          * When receiving a retry, pass it to the bus.
 120          */
 121         virtual void recvRetry()
 122         { panic("Bus slave ports always succeed and should never retry.\n"); }
 123
 124         /**
 125          * Return the union of all adress ranges seen by this bus.
 126          */
 127         virtual AddrRangeList getAddrRanges() const
 128         { return bus.getAddrRanges(); }
 129
 130         /**
 131          * Get the maximum block size as seen by the bus.
 132          */
 133         virtual unsigned deviceBlockSize() const
 134         { return bus.findBlockSize(); }
 135
 136     };
 137
 138     /**
 139      * Declaration of the coherent bus master port type, one will be
 140      * instantiated for each of the slave interfaces connecting to the
 141      * bus.
 142      */
 143     class CoherentBusMasterPort : public MasterPort
 144     {
 145       private:
 146         /** A reference to the bus to which this port belongs. */
 147         CoherentBus &bus;
 148
 149       public:
 150
 151         CoherentBusMasterPort(const std::string &_name,
 152                               CoherentBus &_bus, PortID _id)
 153             : MasterPort(_name, &_bus, _id), bus(_bus)
 154         { }
 155
 156       protected:
 157
 158         /**
 159          * Determine if this port should be considered a snooper. For
 160          * a coherent bus master port this is always true.
 161          *
 162          * @return a boolean that is true if this port is snooping
 163          */
 164         virtual bool isSnooping() const
 165         { return true; }
 166
 167         /**
 168          * When receiving a timing response, pass it to the bus.
 169          */
 170         virtual bool recvTimingResp(PacketPtr pkt)
 171         { return bus.recvTimingResp(pkt, id); }
 172
 173         /**
 174          * When receiving a timing snoop request, pass it to the bus.
 175          */
 176         virtual void recvTimingSnoopReq(PacketPtr pkt)
 177         { return bus.recvTimingSnoopReq(pkt, id); }
 178
 179         /**
 180          * When receiving an atomic snoop request, pass it to the bus.
 181          */
 182         virtual Tick recvAtomicSnoop(PacketPtr pkt)
 183         { return bus.recvAtomicSnoop(pkt, id); }
 184
 185         /**
 186          * When receiving a functional snoop request, pass it to the bus.
 187          */
 188         virtual void recvFunctionalSnoop(PacketPtr pkt)
 189         { bus.recvFunctionalSnoop(pkt, id); }
 190
 191         /** When reciving a range change from the peer port (at id),
 192             pass it to the bus. */
 193         virtual void recvRangeChange()
 194         { bus.recvRangeChange(id); }
 195
 196         /** When reciving a retry from the peer port (at id),
 197             pass it to the bus. */
 198         virtual void recvRetry()
 199         { bus.recvRetry(); }
 200
 201         // Ask the bus to ask everyone on the bus what their block size is and
 202         // take the max of it. This might need to be changed a bit if we ever
 203         // support multiple block sizes.
 204         virtual unsigned deviceBlockSize() const
 205         { return bus.findBlockSize(); }
 206
 207     };
 208
 209     std::vector<SlavePort*> snoopPorts;
 210
 211     /**
 212      * Store the outstanding requests so we can determine which ones
 213      * we generated and which ones were merely forwarded. This is used
 214      * in the coherent bus when coherency responses come back.
 215      */
 216     std::set<RequestPtr> outstandingReq;
 217
 218     /** Function called by the port when the bus is recieving a Timing
 219       request packet.*/
 220     virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
 221
 222     /** Function called by the port when the bus is recieving a Timing
 223       response packet.*/
 224     virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
 225
 226     /** Function called by the port when the bus is recieving a timing
 227         snoop request.*/
 228     virtual void recvTimingSnoopReq(PacketPtr pkt, PortID master_port_id);
 229
 230     /** Function called by the port when the bus is recieving a timing
 231         snoop response.*/
 232     virtual bool recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id);
 233
 234     /**
 235      * Forward a timing packet to our snoopers, potentially excluding
 236      * one of the connected coherent masters to avoid sending a packet
 237      * back to where it came from.
 238      *
 239      * @param pkt Packet to forward
 240      * @param exclude_slave_port_id Id of slave port to exclude
 241      */
 242     void forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id);
 243
 244     /** Function called by the port when the bus is recieving a Atomic
 245       transaction.*/
 246     Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
 247
 248     /** Function called by the port when the bus is recieving an
 249         atomic snoop transaction.*/
 250     Tick recvAtomicSnoop(PacketPtr pkt, PortID master_port_id);
 251
 252     /**
 253      * Forward an atomic packet to our snoopers, potentially excluding
 254      * one of the connected coherent masters to avoid sending a packet
 255      * back to where it came from.
 256      *
 257      * @param pkt Packet to forward
 258      * @param exclude_slave_port_id Id of slave port to exclude
 259      *
 260      * @return a pair containing the snoop response and snoop latency
 261      */
 262     std::pair<MemCmd, Tick> forwardAtomic(PacketPtr pkt,
 263                                           PortID exclude_slave_port_id);
 264
 265     /** Function called by the port when the bus is recieving a Functional
 266         transaction.*/
 267     void recvFunctional(PacketPtr pkt, PortID slave_port_id);
 268
 269     /** Function called by the port when the bus is recieving a functional
 270         snoop transaction.*/
 271     void recvFunctionalSnoop(PacketPtr pkt, PortID master_port_id);
 272
 273     /**
 274      * Forward a functional packet to our snoopers, potentially
 275      * excluding one of the connected coherent masters to avoid
 276      * sending a packet back to where it came from.
 277      *
 278      * @param pkt Packet to forward
 279      * @param exclude_slave_port_id Id of slave port to exclude
 280      */
 281     void forwardFunctional(PacketPtr pkt, PortID exclude_slave_port_id);
 282
 283   public:
 284
 285     virtual void init();
 286
 287     CoherentBus(const CoherentBusParams *p);
 288 };
 289
 290 #endif //__MEM_COHERENT_BUS_HH__