src/mem/coherent_bus.hh

   1 /*
   2  * Copyright (c) 2011-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  *          William Wang
  44  */
  45
  46 /**
  47  * @file
  48  * Declaration of a coherent bus.
  49  */
  50
  51 #ifndef __MEM_COHERENT_BUS_HH__
  52 #define __MEM_COHERENT_BUS_HH__
  53
  54 #include "mem/bus.hh"
  55 #include "params/CoherentBus.hh"
  56
  57 /**
  58  * A coherent bus connects a number of (potentially) snooping masters
  59  * and slaves, and routes the request and response packets based on
  60  * the address, and also forwards all requests to the snoopers and
  61  * deals with the snoop responses.
  62  *
  63  * The coherent bus can be used as a template for modelling QPI,
  64 * HyperTransport, ACE and coherent OCP buses, and is typically used
  65  * for the L1-to-L2 buses and as the main system interconnect.
  66  */
  67 class CoherentBus : public BaseBus
  68 {
  69
  70   protected:
  71
  72     /**
  73      * Declare the single layer of this bus.
  74      */
  75     Layer layer;
  76
  77     /**
  78      * Declaration of the coherent bus slave port type, one will be
  79      * instantiated for each of the master ports connecting to the
  80      * bus.
  81      */
  82     class CoherentBusSlavePort : public SlavePort
  83     {
  84
  85       private:
  86
  87         /** A reference to the bus to which this port belongs. */
  88         CoherentBus &bus;
  89
  90       public:
  91
  92         CoherentBusSlavePort(const std::string &_name,
  93                              CoherentBus &_bus, PortID _id)
  94             : SlavePort(_name, &_bus, _id), bus(_bus)
  95         { }
  96
  97       protected:
  98
  99         /**
 100          * When receiving a timing request, pass it to the bus.
 101          */
 102         virtual bool recvTimingReq(PacketPtr pkt)
 103         { return bus.recvTimingReq(pkt, id); }
 104
 105         /**
 106          * When receiving a timing snoop response, pass it to the bus.
 107          */
 108         virtual bool recvTimingSnoopResp(PacketPtr pkt)
 109         { return bus.recvTimingSnoopResp(pkt, id); }
 110
 111         /**
 112          * When receiving an atomic request, pass it to the bus.
 113          */
 114         virtual Tick recvAtomic(PacketPtr pkt)
 115         { return bus.recvAtomic(pkt, id); }
 116
 117         /**
 118          * When receiving a functional request, pass it to the bus.
 119          */
 120         virtual void recvFunctional(PacketPtr pkt)
 121         { bus.recvFunctional(pkt, id); }
 122
 123         /**
 124          * When receiving a retry, pass it to the bus.
 125          */
 126         virtual void recvRetry()
 127         { panic("Bus slave ports always succeed and should never retry.\n"); }
 128
 129         /**
 130          * Return the union of all adress ranges seen by this bus.
 131          */
 132         virtual AddrRangeList getAddrRanges() const
 133         { return bus.getAddrRanges(); }
 134
 135         /**
 136          * Get the maximum block size as seen by the bus.
 137          */
 138         virtual unsigned deviceBlockSize() const
 139         { return bus.findBlockSize(); }
 140
 141     };
 142
 143     /**
 144      * Declaration of the coherent bus master port type, one will be
 145      * instantiated for each of the slave interfaces connecting to the
 146      * bus.
 147      */
 148     class CoherentBusMasterPort : public MasterPort
 149     {
 150       private:
 151         /** A reference to the bus to which this port belongs. */
 152         CoherentBus &bus;
 153
 154       public:
 155
 156         CoherentBusMasterPort(const std::string &_name,
 157                               CoherentBus &_bus, PortID _id)
 158             : MasterPort(_name, &_bus, _id), bus(_bus)
 159         { }
 160
 161       protected:
 162
 163         /**
 164          * Determine if this port should be considered a snooper. For
 165          * a coherent bus master port this is always true.
 166          *
 167          * @return a boolean that is true if this port is snooping
 168          */
 169         virtual bool isSnooping() const
 170         { return true; }
 171
 172         /**
 173          * When receiving a timing response, pass it to the bus.
 174          */
 175         virtual bool recvTimingResp(PacketPtr pkt)
 176         { return bus.recvTimingResp(pkt, id); }
 177
 178         /**
 179          * When receiving a timing snoop request, pass it to the bus.
 180          */
 181         virtual void recvTimingSnoopReq(PacketPtr pkt)
 182         { return bus.recvTimingSnoopReq(pkt, id); }
 183
 184         /**
 185          * When receiving an atomic snoop request, pass it to the bus.
 186          */
 187         virtual Tick recvAtomicSnoop(PacketPtr pkt)
 188         { return bus.recvAtomicSnoop(pkt, id); }
 189
 190         /**
 191          * When receiving a functional snoop request, pass it to the bus.
 192          */
 193         virtual void recvFunctionalSnoop(PacketPtr pkt)
 194         { bus.recvFunctionalSnoop(pkt, id); }
 195
 196         /** When reciving a range change from the peer port (at id),
 197             pass it to the bus. */
 198         virtual void recvRangeChange()
 199         { bus.recvRangeChange(id); }
 200
 201         /** When reciving a retry from the peer port (at id),
 202             pass it to the bus. */
 203         virtual void recvRetry()
 204         { bus.recvRetry(); }
 205
 206         // Ask the bus to ask everyone on the bus what their block size is and
 207         // take the max of it. This might need to be changed a bit if we ever
 208         // support multiple block sizes.
 209         virtual unsigned deviceBlockSize() const
 210         { return bus.findBlockSize(); }
 211
 212     };
 213
 214     std::vector<SlavePort*> snoopPorts;
 215
 216     /**
 217      * Store the outstanding requests so we can determine which ones
 218      * we generated and which ones were merely forwarded. This is used
 219      * in the coherent bus when coherency responses come back.
 220      */
 221     std::set<RequestPtr> outstandingReq;
 222
 223     /** Function called by the port when the bus is recieving a Timing
 224       request packet.*/
 225     virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
 226
 227     /** Function called by the port when the bus is recieving a Timing
 228       response packet.*/
 229     virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
 230
 231     /** Function called by the port when the bus is recieving a timing
 232         snoop request.*/
 233     virtual void recvTimingSnoopReq(PacketPtr pkt, PortID master_port_id);
 234
 235     /** Function called by the port when the bus is recieving a timing
 236         snoop response.*/
 237     virtual bool recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id);
 238
 239     /** Timing function called by port when it is once again able to process
 240      * requests. */
 241     void recvRetry();
 242
 243     /**
 244      * Forward a timing packet to our snoopers, potentially excluding
 245      * one of the connected coherent masters to avoid sending a packet
 246      * back to where it came from.
 247      *
 248      * @param pkt Packet to forward
 249      * @param exclude_slave_port_id Id of slave port to exclude
 250      */
 251     void forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id);
 252
 253     /** Function called by the port when the bus is recieving a Atomic
 254       transaction.*/
 255     Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
 256
 257     /** Function called by the port when the bus is recieving an
 258         atomic snoop transaction.*/
 259     Tick recvAtomicSnoop(PacketPtr pkt, PortID master_port_id);
 260
 261     /**
 262      * Forward an atomic packet to our snoopers, potentially excluding
 263      * one of the connected coherent masters to avoid sending a packet
 264      * back to where it came from.
 265      *
 266      * @param pkt Packet to forward
 267      * @param exclude_slave_port_id Id of slave port to exclude
 268      *
 269      * @return a pair containing the snoop response and snoop latency
 270      */
 271     std::pair<MemCmd, Tick> forwardAtomic(PacketPtr pkt,
 272                                           PortID exclude_slave_port_id);
 273
 274     /** Function called by the port when the bus is recieving a Functional
 275         transaction.*/
 276     void recvFunctional(PacketPtr pkt, PortID slave_port_id);
 277
 278     /** Function called by the port when the bus is recieving a functional
 279         snoop transaction.*/
 280     void recvFunctionalSnoop(PacketPtr pkt, PortID master_port_id);
 281
 282     /**
 283      * Forward a functional packet to our snoopers, potentially
 284      * excluding one of the connected coherent masters to avoid
 285      * sending a packet back to where it came from.
 286      *
 287      * @param pkt Packet to forward
 288      * @param exclude_slave_port_id Id of slave port to exclude
 289      */
 290     void forwardFunctional(PacketPtr pkt, PortID exclude_slave_port_id);
 291
 292   public:
 293
 294     virtual void init();
 295
 296     CoherentBus(const CoherentBusParams *p);
 297
 298     unsigned int drain(Event *de);
 299 };
 300
 301 #endif //__MEM_COHERENT_BUS_HH__