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28 * Authors: Ron Dreslinski
34 * Derrive a class from PhysicalMemory that support DRAM like timing access.
36 #ifndef __MEM_DRAM_HH__
37 #define __MEM_DRAM_HH__
39 #include "base/statistics.hh"
40 #include "mem/physical.hh"
41 #include "params/DRAMMemory.hh"
43 class DRAMMemory : public PhysicalMemory
46 /* added for dram support */
47 const int cpu_ratio; // ratio between CPU speed and memory bus speed
48 const int bus_width; // memory access bus width (in bytes)
49 /* memory access latency (<first_chunk> <inter_chunk>) */
50 const std::string mem_type;
51 const std::string mem_actpolicy;
52 const std::string memctrladdr_type;
72 /* memory access statistics */
73 int same_row_read_access;
76 int same_row_write_access;
80 int same_bank_read_access;
83 int same_bank_write_access;
87 int other_bank_read_access_hit;
88 int obr_after_read_hit;
89 int obr_after_write_hit;
90 int other_bank_write_access_hit;
91 int obw_after_read_hit;
92 int obw_after_write_hit;
94 // int other_bank_read_access_miss;
95 int obr_after_read_miss;
96 int obr_after_write_miss;
98 // int other_bank_write_access_miss;
99 int obw_after_read_miss;
100 int obw_after_write_miss;
107 int command_overlapping;
111 int full_overlapping;
112 int partial_overlapping;
114 int mem_access_details;
115 int memctrlpipe_enable;
117 Tick time_last_access;
120 Stats::Vector<> accesses;
121 Stats::Vector<> bytesRequested;
122 Stats::Vector<> bytesSent;
123 Stats::Vector<> compressedAccesses;
125 Stats::Vector<> cycles_nCKE;
126 Stats::Vector<> cycles_all_precharge_CKE;
127 Stats::Vector<> cycles_all_precharge_nCKE;
128 Stats::Vector<> cycles_bank_active_nCKE;
129 Stats::Vector<> cycles_avg_ACT;
130 Stats::Vector<> cycles_read_out;
131 Stats::Vector<> cycles_write_in;
132 Stats::Vector<> cycles_between_misses;
133 Stats::Vector<> other_bank_read_access_miss;
134 Stats::Vector<> other_bank_write_access_miss;
135 Stats::Scalar<> total_latency;
136 Stats::Scalar<> total_icache_req;
137 Stats::Scalar<> total_arb_latency;
138 Stats::Formula avg_latency;
139 Stats::Formula avg_arb_latency;
140 Stats::Vector2d<> bank_access_profile;
144 Tick calculateLatency(PacketPtr pkt);
145 int prechargeBanksAround(int bank);
148 typedef DRAMMemoryParams Params;
149 DRAMMemory(const Params *p);
154 return dynamic_cast<const Params *>(_params);
157 virtual void regStats();
160 #endif// __MEM_DRAM_HH__