src/mem/dram.hh

   1 /*
   2  * Copyright (c) 2003-2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ron Dreslinski
  29  *          Ali Saidi
  30  */
  31
  32 /**
  33  * @file
  34  * Derrive a class from PhysicalMemory that support DRAM like timing access.
  35  */
  36 #ifndef __MEM_DRAM_HH__
  37 #define __MEM_DRAM_HH__
  38
  39 #include "base/statistics.hh"
  40 #include "mem/physical.hh"
  41 #include "params/DRAMMemory.hh"
  42
  43 class DRAMMemory : public PhysicalMemory
  44 {
  45   protected:
  46     /* added for dram support */
  47     const int cpu_ratio; // ratio between CPU speed and memory bus speed
  48     const int bus_width;  // memory access bus width (in bytes)
  49     /* memory access latency (<first_chunk> <inter_chunk>) */
  50     const std::string mem_type;
  51     const std::string mem_actpolicy;
  52     const std::string memctrladdr_type;
  53     const int act_lat;
  54     const int cas_lat;
  55     const int war_lat;
  56     const int pre_lat;
  57     const int dpl_lat;
  58     const int trc_lat;
  59     const int num_banks;
  60     const int num_cpus;
  61
  62     int bank_size;
  63     int num_rows;
  64     int *active_row;
  65     int last_bank;
  66     int last_row;
  67     Tick *busy_until;
  68     int last_dev;
  69     bool lastCmdIsRead;
  70     int precharge;
  71
  72     /* memory access statistics */
  73     int same_row_read_access;
  74     int srr_after_read;
  75     int srr_after_write;
  76     int same_row_write_access;
  77     int srw_after_read;
  78     int srw_after_write;
  79
  80     int same_bank_read_access;
  81     int sbr_after_read;
  82     int sbr_after_write;
  83     int same_bank_write_access;
  84     int sbw_after_read;
  85     int sbw_after_write;
  86
  87     int other_bank_read_access_hit;
  88     int obr_after_read_hit;
  89     int obr_after_write_hit;
  90     int other_bank_write_access_hit;
  91     int obw_after_read_hit;
  92     int obw_after_write_hit;
  93     // DR
  94     // int other_bank_read_access_miss;
  95     int obr_after_read_miss;
  96     int obr_after_write_miss;
  97     // DR
  98     // int other_bank_write_access_miss;
  99     int obw_after_read_miss;
 100     int obw_after_write_miss;
 101
 102     int total_access;
 103
 104     int adjacent_access;
 105     int adjacent_read;
 106     int adjacent_write;
 107     int command_overlapping;
 108     int best_case;
 109     int in_between_case;
 110     int worst_case;
 111     int full_overlapping;
 112     int partial_overlapping;
 113
 114     int mem_access_details;
 115     int memctrlpipe_enable;
 116
 117     Tick time_last_access;
 118
 119
 120     Stats::Vector<> accesses;
 121     Stats::Vector<> bytesRequested;
 122     Stats::Vector<> bytesSent;
 123     Stats::Vector<> compressedAccesses;
 124
 125     Stats::Vector<> cycles_nCKE;
 126     Stats::Vector<> cycles_all_precharge_CKE;
 127     Stats::Vector<> cycles_all_precharge_nCKE;
 128     Stats::Vector<> cycles_bank_active_nCKE;
 129     Stats::Vector<> cycles_avg_ACT;
 130     Stats::Vector<> cycles_read_out;
 131     Stats::Vector<> cycles_write_in;
 132     Stats::Vector<> cycles_between_misses;
 133     Stats::Vector<> other_bank_read_access_miss;
 134     Stats::Vector<> other_bank_write_access_miss;
 135     Stats::Scalar<> total_latency;
 136     Stats::Scalar<> total_icache_req;
 137     Stats::Scalar<> total_arb_latency;
 138     Stats::Formula avg_latency;
 139     Stats::Formula avg_arb_latency;
 140     Stats::Vector2d<> bank_access_profile;
 141
 142
 143   protected:
 144     Tick calculateLatency(PacketPtr pkt);
 145     int prechargeBanksAround(int bank);
 146
 147   public:
 148     typedef DRAMMemoryParams Params;
 149     DRAMMemory(const Params *p);
 150
 151     const Params *
 152     params() const
 153     {
 154         return dynamic_cast<const Params *>(_params);
 155     }
 156
 157     virtual void regStats();
 158 };
 159
 160 #endif// __MEM_DRAM_HH__
 161