src/mem/dram.hh

   1 /*
   2  * Copyright (c) 2003-2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ron Dreslinski
  29  *          Ali Saidi
  30  */
  31
  32 /**
  33  * @file
  34  * Derrive a class from PhysicalMemory that support DRAM like timing access.
  35  */
  36 #ifndef __MEM_DRAM_HH__
  37 #define __MEM_DRAM_HH__
  38
  39 #include "base/statistics.hh"
  40 #include "mem/physical.hh"
  41
  42 class DRAMMemory : public PhysicalMemory
  43 {
  44   protected:
  45     /* added for dram support */
  46     const int cpu_ratio; // ratio between CPU speed and memory bus speed
  47     const int bus_width;  // memory access bus width (in bytes)
  48     /* memory access latency (<first_chunk> <inter_chunk>) */
  49     const std::string mem_type;
  50     const std::string mem_actpolicy;
  51     const std::string memctrladdr_type;
  52     const int act_lat;
  53     const int cas_lat;
  54     const int war_lat;
  55     const int pre_lat;
  56     const int dpl_lat;
  57     const int trc_lat;
  58     const int num_banks;
  59     const int num_cpus;
  60
  61     int bank_size;
  62     int num_rows;
  63     int *active_row;
  64     int last_bank;
  65     int last_row;
  66     Tick *busy_until;
  67     int last_dev;
  68     bool lastCmdIsRead;
  69     int precharge;
  70
  71     /* memory access statistics */
  72     int same_row_read_access;
  73     int srr_after_read;
  74     int srr_after_write;
  75     int same_row_write_access;
  76     int srw_after_read;
  77     int srw_after_write;
  78
  79     int same_bank_read_access;
  80     int sbr_after_read;
  81     int sbr_after_write;
  82     int same_bank_write_access;
  83     int sbw_after_read;
  84     int sbw_after_write;
  85
  86     int other_bank_read_access_hit;
  87     int obr_after_read_hit;
  88     int obr_after_write_hit;
  89     int other_bank_write_access_hit;
  90     int obw_after_read_hit;
  91     int obw_after_write_hit;
  92     // DR
  93     // int other_bank_read_access_miss;
  94     int obr_after_read_miss;
  95     int obr_after_write_miss;
  96     // DR
  97     // int other_bank_write_access_miss;
  98     int obw_after_read_miss;
  99     int obw_after_write_miss;
 100
 101     int total_access;
 102
 103     int adjacent_access;
 104     int adjacent_read;
 105     int adjacent_write;
 106     int command_overlapping;
 107     int best_case;
 108     int in_between_case;
 109     int worst_case;
 110     int full_overlapping;
 111     int partial_overlapping;
 112
 113     int mem_access_details;
 114     int memctrlpipe_enable;
 115
 116     Tick time_last_access;
 117
 118
 119     Stats::Vector<> accesses;
 120     Stats::Vector<> bytesRequested;
 121     Stats::Vector<> bytesSent;
 122     Stats::Vector<> compressedAccesses;
 123
 124     Stats::Vector<> cycles_nCKE;
 125     Stats::Vector<> cycles_all_precharge_CKE;
 126     Stats::Vector<> cycles_all_precharge_nCKE;
 127     Stats::Vector<> cycles_bank_active_nCKE;
 128     Stats::Vector<> cycles_avg_ACT;
 129     Stats::Vector<> cycles_read_out;
 130     Stats::Vector<> cycles_write_in;
 131     Stats::Vector<> cycles_between_misses;
 132     Stats::Vector<> other_bank_read_access_miss;
 133     Stats::Vector<> other_bank_write_access_miss;
 134     Stats::Scalar<> total_latency;
 135     Stats::Scalar<> total_icache_req;
 136     Stats::Scalar<> total_arb_latency;
 137     Stats::Formula avg_latency;
 138     Stats::Formula avg_arb_latency;
 139     Stats::Vector2d<> bank_access_profile;
 140
 141
 142   protected:
 143     Tick calculateLatency(PacketPtr pkt);
 144     int prechargeBanksAround(int bank);
 145
 146   public:
 147     struct Params : public PhysicalMemory::Params
 148     {
 149         /* additional params for dram protocol*/
 150         int cpu_ratio;
 151         int bus_width;
 152
 153         std::string mem_type; /* DRDRAM, SDRAM */
 154         std::string mem_actpolicy; /* closed, open */
 155         std::string memctrladdr_type; /* interleaved, anythingelse */
 156
 157         int act_lat;
 158         int cas_lat;
 159         int war_lat;
 160         int pre_lat;
 161         int dpl_lat;
 162         int trc_lat;
 163         int num_banks;
 164         int num_cpus;
 165
 166     };
 167     virtual void regStats();
 168     DRAMMemory(Params *p);
 169 };
 170
 171 #endif// __MEM_DRAM_HH__
 172