2 * Copyright (c) 2010-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
48 #include "mem/dram_ctrl.hh"
50 #include "base/bitfield.hh"
51 #include "base/trace.hh"
52 #include "debug/DRAM.hh"
53 #include "debug/DRAMPower.hh"
54 #include "debug/DRAMState.hh"
55 #include "debug/Drain.hh"
56 #include "sim/system.hh"
61 DRAMCtrl::DRAMCtrl(const DRAMCtrlParams
* p
) :
63 port(name() + ".port", *this), isTimingMode(false),
64 retryRdReq(false), retryWrReq(false),
67 nextReqEvent([this]{ processNextReqEvent(); }, name()),
68 respondEvent([this]{ processRespondEvent(); }, name()),
69 deviceSize(p
->device_size
),
70 deviceBusWidth(p
->device_bus_width
), burstLength(p
->burst_length
),
71 deviceRowBufferSize(p
->device_rowbuffer_size
),
72 devicesPerRank(p
->devices_per_rank
),
73 burstSize((devicesPerRank
* burstLength
* deviceBusWidth
) / 8),
74 rowBufferSize(devicesPerRank
* deviceRowBufferSize
),
75 columnsPerRowBuffer(rowBufferSize
/ burstSize
),
76 columnsPerStripe(range
.interleaved() ? range
.granularity() / burstSize
: 1),
77 ranksPerChannel(p
->ranks_per_channel
),
78 bankGroupsPerRank(p
->bank_groups_per_rank
),
79 bankGroupArch(p
->bank_groups_per_rank
> 0),
80 banksPerRank(p
->banks_per_rank
), channels(p
->channels
), rowsPerBank(0),
81 readBufferSize(p
->read_buffer_size
),
82 writeBufferSize(p
->write_buffer_size
),
83 writeHighThreshold(writeBufferSize
* p
->write_high_thresh_perc
/ 100.0),
84 writeLowThreshold(writeBufferSize
* p
->write_low_thresh_perc
/ 100.0),
85 minWritesPerSwitch(p
->min_writes_per_switch
),
86 writesThisTime(0), readsThisTime(0),
87 tCK(p
->tCK
), tRTW(p
->tRTW
), tCS(p
->tCS
), tBURST(p
->tBURST
),
88 tCCD_L_WR(p
->tCCD_L_WR
),
89 tCCD_L(p
->tCCD_L
), tRCD(p
->tRCD
), tCL(p
->tCL
), tRP(p
->tRP
), tRAS(p
->tRAS
),
90 tWR(p
->tWR
), tRTP(p
->tRTP
), tRFC(p
->tRFC
), tREFI(p
->tREFI
), tRRD(p
->tRRD
),
91 tRRD_L(p
->tRRD_L
), tXAW(p
->tXAW
), tXP(p
->tXP
), tXS(p
->tXS
),
92 activationLimit(p
->activation_limit
), rankToRankDly(tCS
+ tBURST
),
93 wrToRdDly(tCL
+ tBURST
+ p
->tWTR
), rdToWrDly(tRTW
+ tBURST
),
94 memSchedPolicy(p
->mem_sched_policy
), addrMapping(p
->addr_mapping
),
95 pageMgmt(p
->page_policy
),
96 maxAccessesPerRow(p
->max_accesses_per_row
),
97 frontendLatency(p
->static_frontend_latency
),
98 backendLatency(p
->static_backend_latency
),
99 nextBurstAt(0), prevArrival(0),
100 nextReqTime(0), activeRank(0), timeStampOffset(0),
101 lastStatsResetTick(0)
103 // sanity check the ranks since we rely on bit slicing for the
105 fatal_if(!isPowerOf2(ranksPerChannel
), "DRAM rank count of %d is not "
106 "allowed, must be a power of two\n", ranksPerChannel
);
108 fatal_if(!isPowerOf2(burstSize
), "DRAM burst size %d is not allowed, "
109 "must be a power of two\n", burstSize
);
111 for (int i
= 0; i
< ranksPerChannel
; i
++) {
112 Rank
* rank
= new Rank(*this, p
, i
);
113 ranks
.push_back(rank
);
116 // perform a basic check of the write thresholds
117 if (p
->write_low_thresh_perc
>= p
->write_high_thresh_perc
)
118 fatal("Write buffer low threshold %d must be smaller than the "
119 "high threshold %d\n", p
->write_low_thresh_perc
,
120 p
->write_high_thresh_perc
);
122 // determine the rows per bank by looking at the total capacity
123 uint64_t capacity
= ULL(1) << ceilLog2(AbstractMemory::size());
125 // determine the dram actual capacity from the DRAM config in Mbytes
126 uint64_t deviceCapacity
= deviceSize
/ (1024 * 1024) * devicesPerRank
*
129 // if actual DRAM size does not match memory capacity in system warn!
130 if (deviceCapacity
!= capacity
/ (1024 * 1024))
131 warn("DRAM device capacity (%d Mbytes) does not match the "
132 "address range assigned (%d Mbytes)\n", deviceCapacity
,
133 capacity
/ (1024 * 1024));
135 DPRINTF(DRAM
, "Memory capacity %lld (%lld) bytes\n", capacity
,
136 AbstractMemory::size());
138 DPRINTF(DRAM
, "Row buffer size %d bytes with %d columns per row buffer\n",
139 rowBufferSize
, columnsPerRowBuffer
);
141 rowsPerBank
= capacity
/ (rowBufferSize
* banksPerRank
* ranksPerChannel
);
143 // some basic sanity checks
144 if (tREFI
<= tRP
|| tREFI
<= tRFC
) {
145 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
149 // basic bank group architecture checks ->
151 // must have at least one bank per bank group
152 if (bankGroupsPerRank
> banksPerRank
) {
153 fatal("banks per rank (%d) must be equal to or larger than "
154 "banks groups per rank (%d)\n",
155 banksPerRank
, bankGroupsPerRank
);
157 // must have same number of banks in each bank group
158 if ((banksPerRank
% bankGroupsPerRank
) != 0) {
159 fatal("Banks per rank (%d) must be evenly divisible by bank groups "
160 "per rank (%d) for equal banks per bank group\n",
161 banksPerRank
, bankGroupsPerRank
);
163 // tCCD_L should be greater than minimal, back-to-back burst delay
164 if (tCCD_L
<= tBURST
) {
165 fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
166 "bank groups per rank (%d) is greater than 1\n",
167 tCCD_L
, tBURST
, bankGroupsPerRank
);
169 // tCCD_L_WR should be greater than minimal, back-to-back burst delay
170 if (tCCD_L_WR
<= tBURST
) {
171 fatal("tCCD_L_WR (%d) should be larger than tBURST (%d) when "
172 "bank groups per rank (%d) is greater than 1\n",
173 tCCD_L_WR
, tBURST
, bankGroupsPerRank
);
175 // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
176 // some datasheets might specify it equal to tRRD
178 fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
179 "bank groups per rank (%d) is greater than 1\n",
180 tRRD_L
, tRRD
, bankGroupsPerRank
);
189 AbstractMemory::init();
191 if (!port
.isConnected()) {
192 fatal("DRAMCtrl %s is unconnected!\n", name());
194 port
.sendRangeChange();
197 // a bit of sanity checks on the interleaving, save it for here to
198 // ensure that the system pointer is initialised
199 if (range
.interleaved()) {
200 if (channels
!= range
.stripes())
201 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
202 name(), range
.stripes(), channels
);
204 if (addrMapping
== Enums::RoRaBaChCo
) {
205 if (rowBufferSize
!= range
.granularity()) {
206 fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
207 "address map\n", name());
209 } else if (addrMapping
== Enums::RoRaBaCoCh
||
210 addrMapping
== Enums::RoCoRaBaCh
) {
211 // for the interleavings with channel bits in the bottom,
212 // if the system uses a channel striping granularity that
213 // is larger than the DRAM burst size, then map the
214 // sequential accesses within a stripe to a number of
215 // columns in the DRAM, effectively placing some of the
216 // lower-order column bits as the least-significant bits
217 // of the address (above the ones denoting the burst size)
218 assert(columnsPerStripe
>= 1);
220 // channel striping has to be done at a granularity that
221 // is equal or larger to a cache line
222 if (system()->cacheLineSize() > range
.granularity()) {
223 fatal("Channel interleaving of %s must be at least as large "
224 "as the cache line size\n", name());
227 // ...and equal or smaller than the row-buffer size
228 if (rowBufferSize
< range
.granularity()) {
229 fatal("Channel interleaving of %s must be at most as large "
230 "as the row-buffer size\n", name());
232 // this is essentially the check above, so just to be sure
233 assert(columnsPerStripe
<= columnsPerRowBuffer
);
241 // remember the memory system mode of operation
242 isTimingMode
= system()->isTimingMode();
245 // timestamp offset should be in clock cycles for DRAMPower
246 timeStampOffset
= divCeil(curTick(), tCK
);
248 // update the start tick for the precharge accounting to the
250 for (auto r
: ranks
) {
251 r
->startup(curTick() + tREFI
- tRP
);
254 // shift the bus busy time sufficiently far ahead that we never
255 // have to worry about negative values when computing the time for
256 // the next request, this will add an insignificant bubble at the
257 // start of simulation
258 nextBurstAt
= curTick() + tRP
+ tRCD
;
263 DRAMCtrl::recvAtomic(PacketPtr pkt
)
265 DPRINTF(DRAM
, "recvAtomic: %s 0x%x\n", pkt
->cmdString(), pkt
->getAddr());
267 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
270 // do the actual memory access and turn the packet into a response
274 if (pkt
->hasData()) {
275 // this value is not supposed to be accurate, just enough to
276 // keep things going, mimic a closed page
277 latency
= tRP
+ tRCD
+ tCL
;
283 DRAMCtrl::readQueueFull(unsigned int neededEntries
) const
285 DPRINTF(DRAM
, "Read queue limit %d, current size %d, entries needed %d\n",
286 readBufferSize
, readQueue
.size() + respQueue
.size(),
290 (readQueue
.size() + respQueue
.size() + neededEntries
) > readBufferSize
;
294 DRAMCtrl::writeQueueFull(unsigned int neededEntries
) const
296 DPRINTF(DRAM
, "Write queue limit %d, current size %d, entries needed %d\n",
297 writeBufferSize
, writeQueue
.size(), neededEntries
);
298 return (writeQueue
.size() + neededEntries
) > writeBufferSize
;
301 DRAMCtrl::DRAMPacket
*
302 DRAMCtrl::decodeAddr(PacketPtr pkt
, Addr dramPktAddr
, unsigned size
,
305 // decode the address based on the address mapping scheme, with
306 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
307 // channel, respectively
310 // use a 64-bit unsigned during the computations as the row is
311 // always the top bits, and check before creating the DRAMPacket
314 // truncate the address to a DRAM burst, which makes it unique to
315 // a specific column, row, bank, rank and channel
316 Addr addr
= dramPktAddr
/ burstSize
;
318 // we have removed the lowest order address bits that denote the
319 // position within the column
320 if (addrMapping
== Enums::RoRaBaChCo
) {
321 // the lowest order bits denote the column to ensure that
322 // sequential cache lines occupy the same row
323 addr
= addr
/ columnsPerRowBuffer
;
325 // take out the channel part of the address
326 addr
= addr
/ channels
;
328 // after the channel bits, get the bank bits to interleave
330 bank
= addr
% banksPerRank
;
331 addr
= addr
/ banksPerRank
;
333 // after the bank, we get the rank bits which thus interleaves
335 rank
= addr
% ranksPerChannel
;
336 addr
= addr
/ ranksPerChannel
;
338 // lastly, get the row bits, no need to remove them from addr
339 row
= addr
% rowsPerBank
;
340 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
341 // take out the lower-order column bits
342 addr
= addr
/ columnsPerStripe
;
344 // take out the channel part of the address
345 addr
= addr
/ channels
;
347 // next, the higher-order column bites
348 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
350 // after the column bits, we get the bank bits to interleave
352 bank
= addr
% banksPerRank
;
353 addr
= addr
/ banksPerRank
;
355 // after the bank, we get the rank bits which thus interleaves
357 rank
= addr
% ranksPerChannel
;
358 addr
= addr
/ ranksPerChannel
;
360 // lastly, get the row bits, no need to remove them from addr
361 row
= addr
% rowsPerBank
;
362 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
363 // optimise for closed page mode and utilise maximum
364 // parallelism of the DRAM (at the cost of power)
366 // take out the lower-order column bits
367 addr
= addr
/ columnsPerStripe
;
369 // take out the channel part of the address, not that this has
370 // to match with how accesses are interleaved between the
371 // controllers in the address mapping
372 addr
= addr
/ channels
;
374 // start with the bank bits, as this provides the maximum
375 // opportunity for parallelism between requests
376 bank
= addr
% banksPerRank
;
377 addr
= addr
/ banksPerRank
;
379 // next get the rank bits
380 rank
= addr
% ranksPerChannel
;
381 addr
= addr
/ ranksPerChannel
;
383 // next, the higher-order column bites
384 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
386 // lastly, get the row bits, no need to remove them from addr
387 row
= addr
% rowsPerBank
;
389 panic("Unknown address mapping policy chosen!");
391 assert(rank
< ranksPerChannel
);
392 assert(bank
< banksPerRank
);
393 assert(row
< rowsPerBank
);
394 assert(row
< Bank::NO_ROW
);
396 DPRINTF(DRAM
, "Address: %lld Rank %d Bank %d Row %d\n",
397 dramPktAddr
, rank
, bank
, row
);
399 // create the corresponding DRAM packet with the entry time and
400 // ready time set to the current tick, the latter will be updated
402 uint16_t bank_id
= banksPerRank
* rank
+ bank
;
403 return new DRAMPacket(pkt
, isRead
, rank
, bank
, row
, bank_id
, dramPktAddr
,
404 size
, ranks
[rank
]->banks
[bank
], *ranks
[rank
]);
408 DRAMCtrl::addToReadQueue(PacketPtr pkt
, unsigned int pktCount
)
410 // only add to the read queue here. whenever the request is
411 // eventually done, set the readyTime, and call schedule()
412 assert(!pkt
->isWrite());
414 assert(pktCount
!= 0);
416 // if the request size is larger than burst size, the pkt is split into
417 // multiple DRAM packets
418 // Note if the pkt starting address is not aligened to burst size, the
419 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
420 // are aligned to burst size boundaries. This is to ensure we accurately
421 // check read packets against packets in write queue.
422 Addr addr
= pkt
->getAddr();
423 unsigned pktsServicedByWrQ
= 0;
424 BurstHelper
* burst_helper
= NULL
;
425 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
426 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
427 pkt
->getAddr() + pkt
->getSize()) - addr
;
428 readPktSize
[ceilLog2(size
)]++;
431 // First check write buffer to see if the data is already at
433 bool foundInWrQ
= false;
434 Addr burst_addr
= burstAlign(addr
);
435 // if the burst address is not present then there is no need
436 // looking any further
437 if (isInWriteQueue
.find(burst_addr
) != isInWriteQueue
.end()) {
438 for (const auto& p
: writeQueue
) {
439 // check if the read is subsumed in the write queue
440 // packet we are looking at
441 if (p
->addr
<= addr
&& (addr
+ size
) <= (p
->addr
+ p
->size
)) {
445 DPRINTF(DRAM
, "Read to addr %lld with size %d serviced by "
446 "write queue\n", addr
, size
);
447 bytesReadWrQ
+= burstSize
;
453 // If not found in the write q, make a DRAM packet and
454 // push it onto the read queue
457 // Make the burst helper for split packets
458 if (pktCount
> 1 && burst_helper
== NULL
) {
459 DPRINTF(DRAM
, "Read to addr %lld translates to %d "
460 "dram requests\n", pkt
->getAddr(), pktCount
);
461 burst_helper
= new BurstHelper(pktCount
);
464 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, true);
465 dram_pkt
->burstHelper
= burst_helper
;
467 assert(!readQueueFull(1));
468 rdQLenPdf
[readQueue
.size() + respQueue
.size()]++;
470 DPRINTF(DRAM
, "Adding to read queue\n");
472 readQueue
.push_back(dram_pkt
);
474 // increment read entries of the rank
475 ++dram_pkt
->rankRef
.readEntries
;
478 avgRdQLen
= readQueue
.size() + respQueue
.size();
481 // Starting address of next dram pkt (aligend to burstSize boundary)
482 addr
= (addr
| (burstSize
- 1)) + 1;
485 // If all packets are serviced by write queue, we send the repsonse back
486 if (pktsServicedByWrQ
== pktCount
) {
487 accessAndRespond(pkt
, frontendLatency
);
491 // Update how many split packets are serviced by write queue
492 if (burst_helper
!= NULL
)
493 burst_helper
->burstsServiced
= pktsServicedByWrQ
;
495 // If we are not already scheduled to get a request out of the
497 if (!nextReqEvent
.scheduled()) {
498 DPRINTF(DRAM
, "Request scheduled immediately\n");
499 schedule(nextReqEvent
, curTick());
504 DRAMCtrl::addToWriteQueue(PacketPtr pkt
, unsigned int pktCount
)
506 // only add to the write queue here. whenever the request is
507 // eventually done, set the readyTime, and call schedule()
508 assert(pkt
->isWrite());
510 // if the request size is larger than burst size, the pkt is split into
511 // multiple DRAM packets
512 Addr addr
= pkt
->getAddr();
513 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
514 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
515 pkt
->getAddr() + pkt
->getSize()) - addr
;
516 writePktSize
[ceilLog2(size
)]++;
519 // see if we can merge with an existing item in the write
520 // queue and keep track of whether we have merged or not
521 bool merged
= isInWriteQueue
.find(burstAlign(addr
)) !=
522 isInWriteQueue
.end();
524 // if the item was not merged we need to create a new write
527 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, false);
529 assert(writeQueue
.size() < writeBufferSize
);
530 wrQLenPdf
[writeQueue
.size()]++;
532 DPRINTF(DRAM
, "Adding to write queue\n");
534 writeQueue
.push_back(dram_pkt
);
535 isInWriteQueue
.insert(burstAlign(addr
));
536 assert(writeQueue
.size() == isInWriteQueue
.size());
539 avgWrQLen
= writeQueue
.size();
541 // increment write entries of the rank
542 ++dram_pkt
->rankRef
.writeEntries
;
544 DPRINTF(DRAM
, "Merging write burst with existing queue entry\n");
546 // keep track of the fact that this burst effectively
547 // disappeared as it was merged with an existing one
551 // Starting address of next dram pkt (aligend to burstSize boundary)
552 addr
= (addr
| (burstSize
- 1)) + 1;
555 // we do not wait for the writes to be send to the actual memory,
556 // but instead take responsibility for the consistency here and
557 // snoop the write queue for any upcoming reads
558 // @todo, if a pkt size is larger than burst size, we might need a
559 // different front end latency
560 accessAndRespond(pkt
, frontendLatency
);
562 // If we are not already scheduled to get a request out of the
564 if (!nextReqEvent
.scheduled()) {
565 DPRINTF(DRAM
, "Request scheduled immediately\n");
566 schedule(nextReqEvent
, curTick());
571 DRAMCtrl::printQs() const {
572 DPRINTF(DRAM
, "===READ QUEUE===\n\n");
573 for (auto i
= readQueue
.begin() ; i
!= readQueue
.end() ; ++i
) {
574 DPRINTF(DRAM
, "Read %lu\n", (*i
)->addr
);
576 DPRINTF(DRAM
, "\n===RESP QUEUE===\n\n");
577 for (auto i
= respQueue
.begin() ; i
!= respQueue
.end() ; ++i
) {
578 DPRINTF(DRAM
, "Response %lu\n", (*i
)->addr
);
580 DPRINTF(DRAM
, "\n===WRITE QUEUE===\n\n");
581 for (auto i
= writeQueue
.begin() ; i
!= writeQueue
.end() ; ++i
) {
582 DPRINTF(DRAM
, "Write %lu\n", (*i
)->addr
);
587 DRAMCtrl::recvTimingReq(PacketPtr pkt
)
589 // This is where we enter from the outside world
590 DPRINTF(DRAM
, "recvTimingReq: request %s addr %lld size %d\n",
591 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
593 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
596 panic_if(!(pkt
->isRead() || pkt
->isWrite()),
597 "Should only see read and writes at memory controller\n");
599 // Calc avg gap between requests
600 if (prevArrival
!= 0) {
601 totGap
+= curTick() - prevArrival
;
603 prevArrival
= curTick();
606 // Find out how many dram packets a pkt translates to
607 // If the burst size is equal or larger than the pkt size, then a pkt
608 // translates to only one dram packet. Otherwise, a pkt translates to
609 // multiple dram packets
610 unsigned size
= pkt
->getSize();
611 unsigned offset
= pkt
->getAddr() & (burstSize
- 1);
612 unsigned int dram_pkt_count
= divCeil(offset
+ size
, burstSize
);
614 // check local buffers and do not accept if full
617 if (readQueueFull(dram_pkt_count
)) {
618 DPRINTF(DRAM
, "Read queue full, not accepting\n");
619 // remember that we have to retry this port
624 addToReadQueue(pkt
, dram_pkt_count
);
626 bytesReadSys
+= size
;
629 assert(pkt
->isWrite());
631 if (writeQueueFull(dram_pkt_count
)) {
632 DPRINTF(DRAM
, "Write queue full, not accepting\n");
633 // remember that we have to retry this port
638 addToWriteQueue(pkt
, dram_pkt_count
);
640 bytesWrittenSys
+= size
;
648 DRAMCtrl::processRespondEvent()
651 "processRespondEvent(): Some req has reached its readyTime\n");
653 DRAMPacket
* dram_pkt
= respQueue
.front();
655 // if a read has reached its ready-time, decrement the number of reads
656 // At this point the packet has been handled and there is a possibility
657 // to switch to low-power mode if no other packet is available
658 --dram_pkt
->rankRef
.readEntries
;
659 DPRINTF(DRAM
, "number of read entries for rank %d is %d\n",
660 dram_pkt
->rank
, dram_pkt
->rankRef
.readEntries
);
662 // counter should at least indicate one outstanding request
664 assert(dram_pkt
->rankRef
.outstandingEvents
> 0);
665 // read response received, decrement count
666 --dram_pkt
->rankRef
.outstandingEvents
;
668 // at this moment should not have transitioned to a low-power state
669 assert((dram_pkt
->rankRef
.pwrState
!= PWR_SREF
) &&
670 (dram_pkt
->rankRef
.pwrState
!= PWR_PRE_PDN
) &&
671 (dram_pkt
->rankRef
.pwrState
!= PWR_ACT_PDN
));
673 // track if this is the last packet before idling
674 // and that there are no outstanding commands to this rank
675 if (dram_pkt
->rankRef
.isQueueEmpty() &&
676 dram_pkt
->rankRef
.outstandingEvents
== 0) {
677 // verify that there are no events scheduled
678 assert(!dram_pkt
->rankRef
.activateEvent
.scheduled());
679 assert(!dram_pkt
->rankRef
.prechargeEvent
.scheduled());
681 // if coming from active state, schedule power event to
682 // active power-down else go to precharge power-down
683 DPRINTF(DRAMState
, "Rank %d sleep at tick %d; current power state is "
684 "%d\n", dram_pkt
->rank
, curTick(), dram_pkt
->rankRef
.pwrState
);
686 // default to ACT power-down unless already in IDLE state
687 // could be in IDLE if PRE issued before data returned
688 PowerState next_pwr_state
= PWR_ACT_PDN
;
689 if (dram_pkt
->rankRef
.pwrState
== PWR_IDLE
) {
690 next_pwr_state
= PWR_PRE_PDN
;
693 dram_pkt
->rankRef
.powerDownSleep(next_pwr_state
, curTick());
696 if (dram_pkt
->burstHelper
) {
697 // it is a split packet
698 dram_pkt
->burstHelper
->burstsServiced
++;
699 if (dram_pkt
->burstHelper
->burstsServiced
==
700 dram_pkt
->burstHelper
->burstCount
) {
701 // we have now serviced all children packets of a system packet
702 // so we can now respond to the requester
703 // @todo we probably want to have a different front end and back
704 // end latency for split packets
705 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
706 delete dram_pkt
->burstHelper
;
707 dram_pkt
->burstHelper
= NULL
;
710 // it is not a split packet
711 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
714 delete respQueue
.front();
715 respQueue
.pop_front();
717 if (!respQueue
.empty()) {
718 assert(respQueue
.front()->readyTime
>= curTick());
719 assert(!respondEvent
.scheduled());
720 schedule(respondEvent
, respQueue
.front()->readyTime
);
722 // if there is nothing left in any queue, signal a drain
723 if (drainState() == DrainState::Draining
&&
724 writeQueue
.empty() && readQueue
.empty() && allRanksDrained()) {
726 DPRINTF(Drain
, "DRAM controller done draining\n");
731 // We have made a location in the queue available at this point,
732 // so if there is a read that was forced to wait, retry now
740 DRAMCtrl::chooseNext(std::deque
<DRAMPacket
*>& queue
, Tick extra_col_delay
)
742 // This method does the arbitration between requests. The chosen
743 // packet is simply moved to the head of the queue. The other
744 // methods know that this is the place to look. For example, with
745 // FCFS, this method does nothing
746 assert(!queue
.empty());
748 // bool to indicate if a packet to an available rank is found
749 bool found_packet
= false;
750 if (queue
.size() == 1) {
751 DRAMPacket
* dram_pkt
= queue
.front();
752 // available rank corresponds to state refresh idle
753 if (ranks
[dram_pkt
->rank
]->inRefIdleState()) {
755 DPRINTF(DRAM
, "Single request, going to a free rank\n");
757 DPRINTF(DRAM
, "Single request, going to a busy rank\n");
762 if (memSchedPolicy
== Enums::fcfs
) {
763 // check if there is a packet going to a free rank
764 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
765 DRAMPacket
* dram_pkt
= *i
;
766 if (ranks
[dram_pkt
->rank
]->inRefIdleState()) {
768 queue
.push_front(dram_pkt
);
773 } else if (memSchedPolicy
== Enums::frfcfs
) {
774 found_packet
= reorderQueue(queue
, extra_col_delay
);
776 panic("No scheduling policy chosen\n");
781 DRAMCtrl::reorderQueue(std::deque
<DRAMPacket
*>& queue
, Tick extra_col_delay
)
783 // Only determine this if needed
784 vector
<uint32_t> earliest_banks(ranksPerChannel
, 0);
786 // Has minBankPrep been called to populate earliest_banks?
787 bool filled_earliest_banks
= false;
788 // can the PRE/ACT sequence be done without impacting utlization?
789 bool hidden_bank_prep
= false;
791 // search for seamless row hits first, if no seamless row hit is
792 // found then determine if there are other packets that can be issued
793 // without incurring additional bus delay due to bank timing
794 // Will select closed rows first to enable more open row possibilies
795 // in future selections
796 bool found_hidden_bank
= false;
798 // remember if we found a row hit, not seamless, but bank prepped
800 bool found_prepped_pkt
= false;
802 // if we have no row hit, prepped or not, and no seamless packet,
803 // just go for the earliest possible
804 bool found_earliest_pkt
= false;
806 auto selected_pkt_it
= queue
.end();
808 // time we need to issue a column command to be seamless
809 const Tick min_col_at
= std::max(nextBurstAt
+ extra_col_delay
, curTick());
811 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
812 DRAMPacket
* dram_pkt
= *i
;
813 const Bank
& bank
= dram_pkt
->bankRef
;
814 const Tick col_allowed_at
= dram_pkt
->isRead
? bank
.rdAllowedAt
:
817 // check if rank is not doing a refresh and thus is available, if not,
818 // jump to the next packet
819 if (dram_pkt
->rankRef
.inRefIdleState()) {
820 // check if it is a row hit
821 if (bank
.openRow
== dram_pkt
->row
) {
822 // no additional rank-to-rank or same bank-group
823 // delays, or we switched read/write and might as well
824 // go for the row hit
825 if (col_allowed_at
<= min_col_at
) {
826 // FCFS within the hits, giving priority to
827 // commands that can issue seamlessly, without
828 // additional delay, such as same rank accesses
829 // and/or different bank-group accesses
830 DPRINTF(DRAM
, "Seamless row buffer hit\n");
832 // no need to look through the remaining queue entries
834 } else if (!found_hidden_bank
&& !found_prepped_pkt
) {
835 // if we did not find a packet to a closed row that can
836 // issue the bank commands without incurring delay, and
837 // did not yet find a packet to a prepped row, remember
840 found_prepped_pkt
= true;
841 DPRINTF(DRAM
, "Prepped row buffer hit\n");
843 } else if (!found_earliest_pkt
) {
844 // if we have not initialised the bank status, do it
845 // now, and only once per scheduling decisions
846 if (!filled_earliest_banks
) {
847 // determine entries with earliest bank delay
848 std::tie(earliest_banks
, hidden_bank_prep
) =
849 minBankPrep(queue
, min_col_at
);
850 filled_earliest_banks
= true;
853 // bank is amongst first available banks
854 // minBankPrep will give priority to packets that can
856 if (bits(earliest_banks
[dram_pkt
->rank
],
857 dram_pkt
->bank
, dram_pkt
->bank
)) {
858 found_earliest_pkt
= true;
859 found_hidden_bank
= hidden_bank_prep
;
861 // give priority to packets that can issue
862 // bank commands 'behind the scenes'
863 // any additional delay if any will be due to
864 // col-to-col command requirements
865 if (hidden_bank_prep
|| !found_prepped_pkt
)
872 if (selected_pkt_it
!= queue
.end()) {
873 DRAMPacket
* selected_pkt
= *selected_pkt_it
;
874 queue
.erase(selected_pkt_it
);
875 queue
.push_front(selected_pkt
);
883 DRAMCtrl::accessAndRespond(PacketPtr pkt
, Tick static_latency
)
885 DPRINTF(DRAM
, "Responding to Address %lld.. ",pkt
->getAddr());
887 bool needsResponse
= pkt
->needsResponse();
888 // do the actual memory access which also turns the packet into a
892 // turn packet around to go back to requester if response expected
894 // access already turned the packet into a response
895 assert(pkt
->isResponse());
896 // response_time consumes the static latency and is charged also
897 // with headerDelay that takes into account the delay provided by
898 // the xbar and also the payloadDelay that takes into account the
899 // number of data beats.
900 Tick response_time
= curTick() + static_latency
+ pkt
->headerDelay
+
902 // Here we reset the timing of the packet before sending it out.
903 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
905 // queue the packet in the response queue to be sent out after
906 // the static latency has passed
907 port
.schedTimingResp(pkt
, response_time
, true);
909 // @todo the packet is going to be deleted, and the DRAMPacket
910 // is still having a pointer to it
911 pendingDelete
.reset(pkt
);
914 DPRINTF(DRAM
, "Done\n");
920 DRAMCtrl::activateBank(Rank
& rank_ref
, Bank
& bank_ref
,
921 Tick act_tick
, uint32_t row
)
923 assert(rank_ref
.actTicks
.size() == activationLimit
);
925 DPRINTF(DRAM
, "Activate at tick %d\n", act_tick
);
927 // update the open row
928 assert(bank_ref
.openRow
== Bank::NO_ROW
);
929 bank_ref
.openRow
= row
;
931 // start counting anew, this covers both the case when we
932 // auto-precharged, and when this access is forced to
934 bank_ref
.bytesAccessed
= 0;
935 bank_ref
.rowAccesses
= 0;
937 ++rank_ref
.numBanksActive
;
938 assert(rank_ref
.numBanksActive
<= banksPerRank
);
940 DPRINTF(DRAM
, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
941 bank_ref
.bank
, rank_ref
.rank
, act_tick
,
942 ranks
[rank_ref
.rank
]->numBanksActive
);
944 rank_ref
.cmdList
.push_back(Command(MemCommand::ACT
, bank_ref
.bank
,
947 DPRINTF(DRAMPower
, "%llu,ACT,%d,%d\n", divCeil(act_tick
, tCK
) -
948 timeStampOffset
, bank_ref
.bank
, rank_ref
.rank
);
950 // The next access has to respect tRAS for this bank
951 bank_ref
.preAllowedAt
= act_tick
+ tRAS
;
953 // Respect the row-to-column command delay for both read and write cmds
954 bank_ref
.rdAllowedAt
= std::max(act_tick
+ tRCD
, bank_ref
.rdAllowedAt
);
955 bank_ref
.wrAllowedAt
= std::max(act_tick
+ tRCD
, bank_ref
.wrAllowedAt
);
957 // start by enforcing tRRD
958 for (int i
= 0; i
< banksPerRank
; i
++) {
959 // next activate to any bank in this rank must not happen
961 if (bankGroupArch
&& (bank_ref
.bankgr
== rank_ref
.banks
[i
].bankgr
)) {
962 // bank group architecture requires longer delays between
963 // ACT commands within the same bank group. Use tRRD_L
965 rank_ref
.banks
[i
].actAllowedAt
= std::max(act_tick
+ tRRD_L
,
966 rank_ref
.banks
[i
].actAllowedAt
);
968 // use shorter tRRD value when either
969 // 1) bank group architecture is not supportted
970 // 2) bank is in a different bank group
971 rank_ref
.banks
[i
].actAllowedAt
= std::max(act_tick
+ tRRD
,
972 rank_ref
.banks
[i
].actAllowedAt
);
976 // next, we deal with tXAW, if the activation limit is disabled
977 // then we directly schedule an activate power event
978 if (!rank_ref
.actTicks
.empty()) {
980 if (rank_ref
.actTicks
.back() &&
981 (act_tick
- rank_ref
.actTicks
.back()) < tXAW
) {
982 panic("Got %d activates in window %d (%llu - %llu) which "
983 "is smaller than %llu\n", activationLimit
, act_tick
-
984 rank_ref
.actTicks
.back(), act_tick
,
985 rank_ref
.actTicks
.back(), tXAW
);
988 // shift the times used for the book keeping, the last element
989 // (highest index) is the oldest one and hence the lowest value
990 rank_ref
.actTicks
.pop_back();
992 // record an new activation (in the future)
993 rank_ref
.actTicks
.push_front(act_tick
);
995 // cannot activate more than X times in time window tXAW, push the
996 // next one (the X + 1'st activate) to be tXAW away from the
997 // oldest in our window of X
998 if (rank_ref
.actTicks
.back() &&
999 (act_tick
- rank_ref
.actTicks
.back()) < tXAW
) {
1000 DPRINTF(DRAM
, "Enforcing tXAW with X = %d, next activate "
1001 "no earlier than %llu\n", activationLimit
,
1002 rank_ref
.actTicks
.back() + tXAW
);
1003 for (int j
= 0; j
< banksPerRank
; j
++)
1004 // next activate must not happen before end of window
1005 rank_ref
.banks
[j
].actAllowedAt
=
1006 std::max(rank_ref
.actTicks
.back() + tXAW
,
1007 rank_ref
.banks
[j
].actAllowedAt
);
1011 // at the point when this activate takes place, make sure we
1012 // transition to the active power state
1013 if (!rank_ref
.activateEvent
.scheduled())
1014 schedule(rank_ref
.activateEvent
, act_tick
);
1015 else if (rank_ref
.activateEvent
.when() > act_tick
)
1016 // move it sooner in time
1017 reschedule(rank_ref
.activateEvent
, act_tick
);
1021 DRAMCtrl::prechargeBank(Rank
& rank_ref
, Bank
& bank
, Tick pre_at
, bool trace
)
1023 // make sure the bank has an open row
1024 assert(bank
.openRow
!= Bank::NO_ROW
);
1026 // sample the bytes per activate here since we are closing
1028 bytesPerActivate
.sample(bank
.bytesAccessed
);
1030 bank
.openRow
= Bank::NO_ROW
;
1032 // no precharge allowed before this one
1033 bank
.preAllowedAt
= pre_at
;
1035 Tick pre_done_at
= pre_at
+ tRP
;
1037 bank
.actAllowedAt
= std::max(bank
.actAllowedAt
, pre_done_at
);
1039 assert(rank_ref
.numBanksActive
!= 0);
1040 --rank_ref
.numBanksActive
;
1042 DPRINTF(DRAM
, "Precharging bank %d, rank %d at tick %lld, now got "
1043 "%d active\n", bank
.bank
, rank_ref
.rank
, pre_at
,
1044 rank_ref
.numBanksActive
);
1048 rank_ref
.cmdList
.push_back(Command(MemCommand::PRE
, bank
.bank
,
1050 DPRINTF(DRAMPower
, "%llu,PRE,%d,%d\n", divCeil(pre_at
, tCK
) -
1051 timeStampOffset
, bank
.bank
, rank_ref
.rank
);
1053 // if we look at the current number of active banks we might be
1054 // tempted to think the DRAM is now idle, however this can be
1055 // undone by an activate that is scheduled to happen before we
1056 // would have reached the idle state, so schedule an event and
1057 // rather check once we actually make it to the point in time when
1058 // the (last) precharge takes place
1059 if (!rank_ref
.prechargeEvent
.scheduled()) {
1060 schedule(rank_ref
.prechargeEvent
, pre_done_at
);
1061 // New event, increment count
1062 ++rank_ref
.outstandingEvents
;
1063 } else if (rank_ref
.prechargeEvent
.when() < pre_done_at
) {
1064 reschedule(rank_ref
.prechargeEvent
, pre_done_at
);
1069 DRAMCtrl::doDRAMAccess(DRAMPacket
* dram_pkt
)
1071 DPRINTF(DRAM
, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1072 dram_pkt
->addr
, dram_pkt
->rank
, dram_pkt
->bank
, dram_pkt
->row
);
1075 Rank
& rank
= dram_pkt
->rankRef
;
1077 // are we in or transitioning to a low-power state and have not scheduled
1078 // a power-up event?
1079 // if so, wake up from power down to issue RD/WR burst
1080 if (rank
.inLowPowerState
) {
1081 assert(rank
.pwrState
!= PWR_SREF
);
1082 rank
.scheduleWakeUpEvent(tXP
);
1086 Bank
& bank
= dram_pkt
->bankRef
;
1088 // for the state we need to track if it is a row hit or not
1089 bool row_hit
= true;
1091 // Determine the access latency and update the bank state
1092 if (bank
.openRow
== dram_pkt
->row
) {
1097 // If there is a page open, precharge it.
1098 if (bank
.openRow
!= Bank::NO_ROW
) {
1099 prechargeBank(rank
, bank
, std::max(bank
.preAllowedAt
, curTick()));
1102 // next we need to account for the delay in activating the
1104 Tick act_tick
= std::max(bank
.actAllowedAt
, curTick());
1106 // Record the activation and deal with all the global timing
1107 // constraints caused be a new activation (tRRD and tXAW)
1108 activateBank(rank
, bank
, act_tick
, dram_pkt
->row
);
1111 // respect any constraints on the command (e.g. tRCD or tCCD)
1112 const Tick col_allowed_at
= dram_pkt
->isRead
?
1113 bank
.rdAllowedAt
: bank
.wrAllowedAt
;
1115 // we need to wait until the bus is available before we can issue
1116 // the command; need minimum of tBURST between commands
1117 Tick cmd_at
= std::max({col_allowed_at
, nextBurstAt
, curTick()});
1119 // update the packet ready time
1120 dram_pkt
->readyTime
= cmd_at
+ tCL
+ tBURST
;
1122 // update the time for the next read/write burst for each
1123 // bank (add a max with tCCD/tCCD_L/tCCD_L_WR here)
1126 for (int j
= 0; j
< ranksPerChannel
; j
++) {
1127 for (int i
= 0; i
< banksPerRank
; i
++) {
1128 // next burst to same bank group in this rank must not happen
1129 // before tCCD_L. Different bank group timing requirement is
1130 // tBURST; Add tCS for different ranks
1131 if (dram_pkt
->rank
== j
) {
1132 if (bankGroupArch
&&
1133 (bank
.bankgr
== ranks
[j
]->banks
[i
].bankgr
)) {
1134 // bank group architecture requires longer delays between
1135 // RD/WR burst commands to the same bank group.
1136 // tCCD_L is default requirement for same BG timing
1137 // tCCD_L_WR is required for write-to-write
1138 // Need to also take bus turnaround delays into account
1139 dly_to_rd_cmd
= dram_pkt
->isRead
?
1140 tCCD_L
: std::max(tCCD_L
, wrToRdDly
);
1141 dly_to_wr_cmd
= dram_pkt
->isRead
?
1142 std::max(tCCD_L
, rdToWrDly
) : tCCD_L_WR
;
1144 // tBURST is default requirement for diff BG timing
1145 // Need to also take bus turnaround delays into account
1146 dly_to_rd_cmd
= dram_pkt
->isRead
? tBURST
: wrToRdDly
;
1147 dly_to_wr_cmd
= dram_pkt
->isRead
? rdToWrDly
: tBURST
;
1150 // different rank is by default in a different bank group and
1151 // doesn't require longer tCCD or additional RTW, WTR delays
1152 // Need to account for rank-to-rank switching with tCS
1153 dly_to_wr_cmd
= rankToRankDly
;
1154 dly_to_rd_cmd
= rankToRankDly
;
1156 ranks
[j
]->banks
[i
].rdAllowedAt
= std::max(cmd_at
+ dly_to_rd_cmd
,
1157 ranks
[j
]->banks
[i
].rdAllowedAt
);
1158 ranks
[j
]->banks
[i
].wrAllowedAt
= std::max(cmd_at
+ dly_to_wr_cmd
,
1159 ranks
[j
]->banks
[i
].wrAllowedAt
);
1163 // Save rank of current access
1164 activeRank
= dram_pkt
->rank
;
1166 // If this is a write, we also need to respect the write recovery
1167 // time before a precharge, in the case of a read, respect the
1168 // read to precharge constraint
1169 bank
.preAllowedAt
= std::max(bank
.preAllowedAt
,
1170 dram_pkt
->isRead
? cmd_at
+ tRTP
:
1171 dram_pkt
->readyTime
+ tWR
);
1173 // increment the bytes accessed and the accesses per row
1174 bank
.bytesAccessed
+= burstSize
;
1177 // if we reached the max, then issue with an auto-precharge
1178 bool auto_precharge
= pageMgmt
== Enums::close
||
1179 bank
.rowAccesses
== maxAccessesPerRow
;
1181 // if we did not hit the limit, we might still want to
1183 if (!auto_precharge
&&
1184 (pageMgmt
== Enums::open_adaptive
||
1185 pageMgmt
== Enums::close_adaptive
)) {
1186 // a twist on the open and close page policies:
1187 // 1) open_adaptive page policy does not blindly keep the
1188 // page open, but close it if there are no row hits, and there
1189 // are bank conflicts in the queue
1190 // 2) close_adaptive page policy does not blindly close the
1191 // page, but closes it only if there are no row hits in the queue.
1192 // In this case, only force an auto precharge when there
1193 // are no same page hits in the queue
1194 bool got_more_hits
= false;
1195 bool got_bank_conflict
= false;
1197 // either look at the read queue or write queue
1198 const deque
<DRAMPacket
*>& queue
= dram_pkt
->isRead
? readQueue
:
1200 auto p
= queue
.begin();
1201 // make sure we are not considering the packet that we are
1202 // currently dealing with (which is the head of the queue)
1205 // keep on looking until we find a hit or reach the end of the queue
1206 // 1) if a hit is found, then both open and close adaptive policies keep
1208 // 2) if no hit is found, got_bank_conflict is set to true if a bank
1209 // conflict request is waiting in the queue
1210 while (!got_more_hits
&& p
!= queue
.end()) {
1211 bool same_rank_bank
= (dram_pkt
->rank
== (*p
)->rank
) &&
1212 (dram_pkt
->bank
== (*p
)->bank
);
1213 bool same_row
= dram_pkt
->row
== (*p
)->row
;
1214 got_more_hits
|= same_rank_bank
&& same_row
;
1215 got_bank_conflict
|= same_rank_bank
&& !same_row
;
1219 // auto pre-charge when either
1220 // 1) open_adaptive policy, we have not got any more hits, and
1221 // have a bank conflict
1222 // 2) close_adaptive policy and we have not got any more hits
1223 auto_precharge
= !got_more_hits
&&
1224 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
);
1227 // DRAMPower trace command to be written
1228 std::string mem_cmd
= dram_pkt
->isRead
? "RD" : "WR";
1230 // MemCommand required for DRAMPower library
1231 MemCommand::cmds command
= (mem_cmd
== "RD") ? MemCommand::RD
:
1234 // Update bus state to reflect when previous command was issued
1235 nextBurstAt
= cmd_at
+ tBURST
;
1237 DPRINTF(DRAM
, "Access to %lld, ready at %lld next burst at %lld.\n",
1238 dram_pkt
->addr
, dram_pkt
->readyTime
, nextBurstAt
);
1240 dram_pkt
->rankRef
.cmdList
.push_back(Command(command
, dram_pkt
->bank
,
1243 DPRINTF(DRAMPower
, "%llu,%s,%d,%d\n", divCeil(cmd_at
, tCK
) -
1244 timeStampOffset
, mem_cmd
, dram_pkt
->bank
, dram_pkt
->rank
);
1246 // if this access should use auto-precharge, then we are
1247 // closing the row after the read/write burst
1248 if (auto_precharge
) {
1249 // if auto-precharge push a PRE command at the correct tick to the
1250 // list used by DRAMPower library to calculate power
1251 prechargeBank(rank
, bank
, std::max(curTick(), bank
.preAllowedAt
));
1253 DPRINTF(DRAM
, "Auto-precharged bank: %d\n", dram_pkt
->bankId
);
1256 // Update the minimum timing between the requests, this is a
1257 // conservative estimate of when we have to schedule the next
1258 // request to not introduce any unecessary bubbles. In most cases
1259 // we will wake up sooner than we have to.
1260 nextReqTime
= nextBurstAt
- (tRP
+ tRCD
);
1262 // Update the stats and schedule the next request
1263 if (dram_pkt
->isRead
) {
1267 bytesReadDRAM
+= burstSize
;
1268 perBankRdBursts
[dram_pkt
->bankId
]++;
1270 // Update latency stats
1271 totMemAccLat
+= dram_pkt
->readyTime
- dram_pkt
->entryTime
;
1272 totBusLat
+= tBURST
;
1273 totQLat
+= cmd_at
- dram_pkt
->entryTime
;
1278 bytesWritten
+= burstSize
;
1279 perBankWrBursts
[dram_pkt
->bankId
]++;
1284 DRAMCtrl::processNextReqEvent()
1287 for (auto r
: ranks
) {
1288 if (!r
->inRefIdleState()) {
1289 if (r
->pwrState
!= PWR_SREF
) {
1290 // rank is busy refreshing
1291 DPRINTF(DRAMState
, "Rank %d is not available\n", r
->rank
);
1294 // let the rank know that if it was waiting to drain, it
1295 // is now done and ready to proceed
1296 r
->checkDrainDone();
1299 // check if we were in self-refresh and haven't started
1300 // to transition out
1301 if ((r
->pwrState
== PWR_SREF
) && r
->inLowPowerState
) {
1302 DPRINTF(DRAMState
, "Rank %d is in self-refresh\n", r
->rank
);
1303 // if we have commands queued to this rank and we don't have
1304 // a minimum number of active commands enqueued,
1305 // exit self-refresh
1306 if (r
->forceSelfRefreshExit()) {
1307 DPRINTF(DRAMState
, "rank %d was in self refresh and"
1308 " should wake up\n", r
->rank
);
1309 //wake up from self-refresh
1310 r
->scheduleWakeUpEvent(tXS
);
1311 // things are brought back into action once a refresh is
1312 // performed after self-refresh
1313 // continue with selection for other ranks
1319 if (busyRanks
== ranksPerChannel
) {
1320 // if all ranks are refreshing wait for them to finish
1321 // and stall this state machine without taking any further
1322 // action, and do not schedule a new nextReqEvent
1326 // pre-emptively set to false. Overwrite if in transitioning to
1328 bool switched_cmd_type
= false;
1329 if (busState
!= busStateNext
) {
1330 if (busState
== READ
) {
1331 DPRINTF(DRAM
, "Switching to writes after %d reads with %d reads "
1332 "waiting\n", readsThisTime
, readQueue
.size());
1334 // sample and reset the read-related stats as we are now
1335 // transitioning to writes, and all reads are done
1336 rdPerTurnAround
.sample(readsThisTime
);
1339 // now proceed to do the actual writes
1340 switched_cmd_type
= true;
1342 DPRINTF(DRAM
, "Switching to reads after %d writes with %d writes "
1343 "waiting\n", writesThisTime
, writeQueue
.size());
1345 wrPerTurnAround
.sample(writesThisTime
);
1348 switched_cmd_type
= true;
1350 // update busState to match next state until next transition
1351 busState
= busStateNext
;
1354 // when we get here it is either a read or a write
1355 if (busState
== READ
) {
1357 // track if we should switch or not
1358 bool switch_to_writes
= false;
1360 if (readQueue
.empty()) {
1361 // In the case there is no read request to go next,
1362 // trigger writes if we have passed the low threshold (or
1363 // if we are draining)
1364 if (!writeQueue
.empty() &&
1365 (drainState() == DrainState::Draining
||
1366 writeQueue
.size() > writeLowThreshold
)) {
1368 switch_to_writes
= true;
1370 // check if we are drained
1371 // not done draining until in PWR_IDLE state
1372 // ensuring all banks are closed and
1373 // have exited low power states
1374 if (drainState() == DrainState::Draining
&&
1375 respQueue
.empty() && allRanksDrained()) {
1377 DPRINTF(Drain
, "DRAM controller done draining\n");
1381 // nothing to do, not even any point in scheduling an
1382 // event for the next request
1386 // bool to check if there is a read to a free rank
1387 bool found_read
= false;
1389 // Figure out which read request goes next, and move it to the
1390 // front of the read queue
1391 // If we are changing command type, incorporate the minimum
1392 // bus turnaround delay which will be tCS (different rank) case
1393 found_read
= chooseNext(readQueue
, switched_cmd_type
? tCS
: 0);
1395 // if no read to an available rank is found then return
1396 // at this point. There could be writes to the available ranks
1397 // which are above the required threshold. However, to
1398 // avoid adding more complexity to the code, return and wait
1399 // for a refresh event to kick things into action again.
1403 DRAMPacket
* dram_pkt
= readQueue
.front();
1404 assert(dram_pkt
->rankRef
.inRefIdleState());
1406 doDRAMAccess(dram_pkt
);
1408 // At this point we're done dealing with the request
1409 readQueue
.pop_front();
1411 // Every respQueue which will generate an event, increment count
1412 ++dram_pkt
->rankRef
.outstandingEvents
;
1415 assert(dram_pkt
->size
<= burstSize
);
1416 assert(dram_pkt
->readyTime
>= curTick());
1418 // Insert into response queue. It will be sent back to the
1419 // requestor at its readyTime
1420 if (respQueue
.empty()) {
1421 assert(!respondEvent
.scheduled());
1422 schedule(respondEvent
, dram_pkt
->readyTime
);
1424 assert(respQueue
.back()->readyTime
<= dram_pkt
->readyTime
);
1425 assert(respondEvent
.scheduled());
1428 respQueue
.push_back(dram_pkt
);
1430 // we have so many writes that we have to transition
1431 if (writeQueue
.size() > writeHighThreshold
) {
1432 switch_to_writes
= true;
1436 // switching to writes, either because the read queue is empty
1437 // and the writes have passed the low threshold (or we are
1438 // draining), or because the writes hit the hight threshold
1439 if (switch_to_writes
) {
1440 // transition to writing
1441 busStateNext
= WRITE
;
1444 // bool to check if write to free rank is found
1445 bool found_write
= false;
1447 // If we are changing command type, incorporate the minimum
1448 // bus turnaround delay
1449 found_write
= chooseNext(writeQueue
,
1450 switched_cmd_type
? std::min(tRTW
, tCS
) : 0);
1452 // if there are no writes to a rank that is available to service
1453 // requests (i.e. rank is in refresh idle state) are found then
1454 // return. There could be reads to the available ranks. However, to
1455 // avoid adding more complexity to the code, return at this point and
1456 // wait for a refresh event to kick things into action again.
1460 DRAMPacket
* dram_pkt
= writeQueue
.front();
1461 assert(dram_pkt
->rankRef
.inRefIdleState());
1463 assert(dram_pkt
->size
<= burstSize
);
1465 doDRAMAccess(dram_pkt
);
1467 writeQueue
.pop_front();
1469 // removed write from queue, decrement count
1470 --dram_pkt
->rankRef
.writeEntries
;
1472 // Schedule write done event to decrement event count
1473 // after the readyTime has been reached
1474 // Only schedule latest write event to minimize events
1475 // required; only need to ensure that final event scheduled covers
1476 // the time that writes are outstanding and bus is active
1477 // to holdoff power-down entry events
1478 if (!dram_pkt
->rankRef
.writeDoneEvent
.scheduled()) {
1479 schedule(dram_pkt
->rankRef
.writeDoneEvent
, dram_pkt
->readyTime
);
1480 // New event, increment count
1481 ++dram_pkt
->rankRef
.outstandingEvents
;
1483 } else if (dram_pkt
->rankRef
.writeDoneEvent
.when() <
1484 dram_pkt
-> readyTime
) {
1485 reschedule(dram_pkt
->rankRef
.writeDoneEvent
, dram_pkt
->readyTime
);
1488 isInWriteQueue
.erase(burstAlign(dram_pkt
->addr
));
1491 // If we emptied the write queue, or got sufficiently below the
1492 // threshold (using the minWritesPerSwitch as the hysteresis) and
1493 // are not draining, or we have reads waiting and have done enough
1494 // writes, then switch to reads.
1495 if (writeQueue
.empty() ||
1496 (writeQueue
.size() + minWritesPerSwitch
< writeLowThreshold
&&
1497 drainState() != DrainState::Draining
) ||
1498 (!readQueue
.empty() && writesThisTime
>= minWritesPerSwitch
)) {
1499 // turn the bus back around for reads again
1500 busStateNext
= READ
;
1502 // note that the we switch back to reads also in the idle
1503 // case, which eventually will check for any draining and
1504 // also pause any further scheduling if there is really
1508 // It is possible that a refresh to another rank kicks things back into
1509 // action before reaching this point.
1510 if (!nextReqEvent
.scheduled())
1511 schedule(nextReqEvent
, std::max(nextReqTime
, curTick()));
1513 // If there is space available and we have writes waiting then let
1514 // them retry. This is done here to ensure that the retry does not
1515 // cause a nextReqEvent to be scheduled before we do so as part of
1516 // the next request processing
1517 if (retryWrReq
&& writeQueue
.size() < writeBufferSize
) {
1519 port
.sendRetryReq();
1523 pair
<vector
<uint32_t>, bool>
1524 DRAMCtrl::minBankPrep(const deque
<DRAMPacket
*>& queue
,
1525 Tick min_col_at
) const
1527 Tick min_act_at
= MaxTick
;
1528 vector
<uint32_t> bank_mask(ranksPerChannel
, 0);
1530 // latest Tick for which ACT can occur without incurring additoinal
1531 // delay on the data bus
1532 const Tick hidden_act_max
= std::max(min_col_at
- tRCD
, curTick());
1534 // Flag condition when burst can issue back-to-back with previous burst
1535 bool found_seamless_bank
= false;
1537 // Flag condition when bank can be opened without incurring additional
1538 // delay on the data bus
1539 bool hidden_bank_prep
= false;
1541 // determine if we have queued transactions targetting the
1543 vector
<bool> got_waiting(ranksPerChannel
* banksPerRank
, false);
1544 for (const auto& p
: queue
) {
1545 if (p
->rankRef
.inRefIdleState())
1546 got_waiting
[p
->bankId
] = true;
1549 // Find command with optimal bank timing
1550 // Will prioritize commands that can issue seamlessly.
1551 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1552 for (int j
= 0; j
< banksPerRank
; j
++) {
1553 uint16_t bank_id
= i
* banksPerRank
+ j
;
1555 // if we have waiting requests for the bank, and it is
1556 // amongst the first available, update the mask
1557 if (got_waiting
[bank_id
]) {
1558 // make sure this rank is not currently refreshing.
1559 assert(ranks
[i
]->inRefIdleState());
1560 // simplistic approximation of when the bank can issue
1561 // an activate, ignoring any rank-to-rank switching
1562 // cost in this calculation
1563 Tick act_at
= ranks
[i
]->banks
[j
].openRow
== Bank::NO_ROW
?
1564 std::max(ranks
[i
]->banks
[j
].actAllowedAt
, curTick()) :
1565 std::max(ranks
[i
]->banks
[j
].preAllowedAt
, curTick()) + tRP
;
1567 // When is the earliest the R/W burst can issue?
1568 const Tick col_allowed_at
= (busState
== READ
) ?
1569 ranks
[i
]->banks
[j
].rdAllowedAt
:
1570 ranks
[i
]->banks
[j
].wrAllowedAt
;
1571 Tick col_at
= std::max(col_allowed_at
, act_at
+ tRCD
);
1573 // bank can issue burst back-to-back (seamlessly) with
1575 bool new_seamless_bank
= col_at
<= min_col_at
;
1577 // if we found a new seamless bank or we have no
1578 // seamless banks, and got a bank with an earlier
1579 // activate time, it should be added to the bit mask
1580 if (new_seamless_bank
||
1581 (!found_seamless_bank
&& act_at
<= min_act_at
)) {
1582 // if we did not have a seamless bank before, and
1583 // we do now, reset the bank mask, also reset it
1584 // if we have not yet found a seamless bank and
1585 // the activate time is smaller than what we have
1587 if (!found_seamless_bank
&&
1588 (new_seamless_bank
|| act_at
< min_act_at
)) {
1589 std::fill(bank_mask
.begin(), bank_mask
.end(), 0);
1592 found_seamless_bank
|= new_seamless_bank
;
1594 // ACT can occur 'behind the scenes'
1595 hidden_bank_prep
= act_at
<= hidden_act_max
;
1597 // set the bit corresponding to the available bank
1598 replaceBits(bank_mask
[i
], j
, j
, 1);
1599 min_act_at
= act_at
;
1605 return make_pair(bank_mask
, hidden_bank_prep
);
1608 DRAMCtrl::Rank::Rank(DRAMCtrl
& _memory
, const DRAMCtrlParams
* _p
, int rank
)
1609 : EventManager(&_memory
), memory(_memory
),
1610 pwrStateTrans(PWR_IDLE
), pwrStatePostRefresh(PWR_IDLE
),
1611 pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE
),
1612 refreshState(REF_IDLE
), inLowPowerState(false), rank(rank
),
1613 readEntries(0), writeEntries(0), outstandingEvents(0),
1614 wakeUpAllowedAt(0), power(_p
, false), banks(_p
->banks_per_rank
),
1615 numBanksActive(0), actTicks(_p
->activation_limit
, 0),
1616 writeDoneEvent([this]{ processWriteDoneEvent(); }, name()),
1617 activateEvent([this]{ processActivateEvent(); }, name()),
1618 prechargeEvent([this]{ processPrechargeEvent(); }, name()),
1619 refreshEvent([this]{ processRefreshEvent(); }, name()),
1620 powerEvent([this]{ processPowerEvent(); }, name()),
1621 wakeUpEvent([this]{ processWakeUpEvent(); }, name())
1623 for (int b
= 0; b
< _p
->banks_per_rank
; b
++) {
1625 // GDDR addressing of banks to BG is linear.
1626 // Here we assume that all DRAM generations address bank groups as
1628 if (_p
->bank_groups_per_rank
> 0) {
1629 // Simply assign lower bits to bank group in order to
1630 // rotate across bank groups as banks are incremented
1631 // e.g. with 4 banks per bank group and 16 banks total:
1632 // banks 0,4,8,12 are in bank group 0
1633 // banks 1,5,9,13 are in bank group 1
1634 // banks 2,6,10,14 are in bank group 2
1635 // banks 3,7,11,15 are in bank group 3
1636 banks
[b
].bankgr
= b
% _p
->bank_groups_per_rank
;
1638 // No bank groups; simply assign to bank number
1639 banks
[b
].bankgr
= b
;
1645 DRAMCtrl::Rank::startup(Tick ref_tick
)
1647 assert(ref_tick
> curTick());
1649 pwrStateTick
= curTick();
1651 // kick off the refresh, and give ourselves enough time to
1653 schedule(refreshEvent
, ref_tick
);
1657 DRAMCtrl::Rank::suspend()
1659 deschedule(refreshEvent
);
1664 // don't automatically transition back to LP state after next REF
1665 pwrStatePostRefresh
= PWR_IDLE
;
1669 DRAMCtrl::Rank::isQueueEmpty() const
1671 // check commmands in Q based on current bus direction
1672 bool no_queued_cmds
= ((memory
.busStateNext
== READ
) && (readEntries
== 0))
1673 || ((memory
.busStateNext
== WRITE
) &&
1674 (writeEntries
== 0));
1675 return no_queued_cmds
;
1679 DRAMCtrl::Rank::checkDrainDone()
1681 // if this rank was waiting to drain it is now able to proceed to
1683 if (refreshState
== REF_DRAIN
) {
1684 DPRINTF(DRAM
, "Refresh drain done, now precharging\n");
1686 refreshState
= REF_PD_EXIT
;
1688 // hand control back to the refresh event loop
1689 schedule(refreshEvent
, curTick());
1694 DRAMCtrl::Rank::flushCmdList()
1696 // at the moment sort the list of commands and update the counters
1697 // for DRAMPower libray when doing a refresh
1698 sort(cmdList
.begin(), cmdList
.end(), DRAMCtrl::sortTime
);
1700 auto next_iter
= cmdList
.begin();
1701 // push to commands to DRAMPower
1702 for ( ; next_iter
!= cmdList
.end() ; ++next_iter
) {
1703 Command cmd
= *next_iter
;
1704 if (cmd
.timeStamp
<= curTick()) {
1705 // Move all commands at or before curTick to DRAMPower
1706 power
.powerlib
.doCommand(cmd
.type
, cmd
.bank
,
1707 divCeil(cmd
.timeStamp
, memory
.tCK
) -
1708 memory
.timeStampOffset
);
1710 // done - found all commands at or before curTick()
1711 // next_iter references the 1st command after curTick
1715 // reset cmdList to only contain commands after curTick
1716 // if there are no commands after curTick, updated cmdList will be empty
1717 // in this case, next_iter is cmdList.end()
1718 cmdList
.assign(next_iter
, cmdList
.end());
1722 DRAMCtrl::Rank::processActivateEvent()
1724 // we should transition to the active state as soon as any bank is active
1725 if (pwrState
!= PWR_ACT
)
1726 // note that at this point numBanksActive could be back at
1727 // zero again due to a precharge scheduled in the future
1728 schedulePowerEvent(PWR_ACT
, curTick());
1732 DRAMCtrl::Rank::processPrechargeEvent()
1734 // counter should at least indicate one outstanding request
1735 // for this precharge
1736 assert(outstandingEvents
> 0);
1737 // precharge complete, decrement count
1738 --outstandingEvents
;
1740 // if we reached zero, then special conditions apply as we track
1741 // if all banks are precharged for the power models
1742 if (numBanksActive
== 0) {
1743 // no reads to this rank in the Q and no pending
1744 // RD/WR or refresh commands
1745 if (isQueueEmpty() && outstandingEvents
== 0) {
1746 // should still be in ACT state since bank still open
1747 assert(pwrState
== PWR_ACT
);
1749 // All banks closed - switch to precharge power down state.
1750 DPRINTF(DRAMState
, "Rank %d sleep at tick %d\n",
1752 powerDownSleep(PWR_PRE_PDN
, curTick());
1754 // we should transition to the idle state when the last bank
1756 schedulePowerEvent(PWR_IDLE
, curTick());
1762 DRAMCtrl::Rank::processWriteDoneEvent()
1764 // counter should at least indicate one outstanding request
1766 assert(outstandingEvents
> 0);
1767 // Write transfer on bus has completed
1768 // decrement per rank counter
1769 --outstandingEvents
;
1773 DRAMCtrl::Rank::processRefreshEvent()
1775 // when first preparing the refresh, remember when it was due
1776 if ((refreshState
== REF_IDLE
) || (refreshState
== REF_SREF_EXIT
)) {
1777 // remember when the refresh is due
1778 refreshDueAt
= curTick();
1781 refreshState
= REF_DRAIN
;
1783 // make nonzero while refresh is pending to ensure
1784 // power down and self-refresh are not entered
1785 ++outstandingEvents
;
1787 DPRINTF(DRAM
, "Refresh due\n");
1790 // let any scheduled read or write to the same rank go ahead,
1791 // after which it will
1792 // hand control back to this event loop
1793 if (refreshState
== REF_DRAIN
) {
1794 // if a request is at the moment being handled and this request is
1795 // accessing the current rank then wait for it to finish
1796 if ((rank
== memory
.activeRank
)
1797 && (memory
.nextReqEvent
.scheduled())) {
1798 // hand control over to the request loop until it is
1800 DPRINTF(DRAM
, "Refresh awaiting draining\n");
1804 refreshState
= REF_PD_EXIT
;
1808 // at this point, ensure that rank is not in a power-down state
1809 if (refreshState
== REF_PD_EXIT
) {
1810 // if rank was sleeping and we have't started exit process,
1811 // wake-up for refresh
1812 if (inLowPowerState
) {
1813 DPRINTF(DRAM
, "Wake Up for refresh\n");
1814 // save state and return after refresh completes
1815 scheduleWakeUpEvent(memory
.tXP
);
1818 refreshState
= REF_PRE
;
1822 // at this point, ensure that all banks are precharged
1823 if (refreshState
== REF_PRE
) {
1824 // precharge any active bank
1825 if (numBanksActive
!= 0) {
1826 // at the moment, we use a precharge all even if there is
1827 // only a single bank open
1828 DPRINTF(DRAM
, "Precharging all\n");
1830 // first determine when we can precharge
1831 Tick pre_at
= curTick();
1833 for (auto &b
: banks
) {
1834 // respect both causality and any existing bank
1835 // constraints, some banks could already have a
1836 // (auto) precharge scheduled
1837 pre_at
= std::max(b
.preAllowedAt
, pre_at
);
1840 // make sure all banks per rank are precharged, and for those that
1841 // already are, update their availability
1842 Tick act_allowed_at
= pre_at
+ memory
.tRP
;
1844 for (auto &b
: banks
) {
1845 if (b
.openRow
!= Bank::NO_ROW
) {
1846 memory
.prechargeBank(*this, b
, pre_at
, false);
1848 b
.actAllowedAt
= std::max(b
.actAllowedAt
, act_allowed_at
);
1849 b
.preAllowedAt
= std::max(b
.preAllowedAt
, pre_at
);
1853 // precharge all banks in rank
1854 cmdList
.push_back(Command(MemCommand::PREA
, 0, pre_at
));
1856 DPRINTF(DRAMPower
, "%llu,PREA,0,%d\n",
1857 divCeil(pre_at
, memory
.tCK
) -
1858 memory
.timeStampOffset
, rank
);
1859 } else if ((pwrState
== PWR_IDLE
) && (outstandingEvents
== 1)) {
1860 // Banks are closed, have transitioned to IDLE state, and
1861 // no outstanding ACT,RD/WR,Auto-PRE sequence scheduled
1862 DPRINTF(DRAM
, "All banks already precharged, starting refresh\n");
1864 // go ahead and kick the power state machine into gear since
1865 // we are already idle
1866 schedulePowerEvent(PWR_REF
, curTick());
1868 // banks state is closed but haven't transitioned pwrState to IDLE
1869 // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled
1870 // should have outstanding precharge event in this case
1871 assert(prechargeEvent
.scheduled());
1872 // will start refresh when pwrState transitions to IDLE
1875 assert(numBanksActive
== 0);
1877 // wait for all banks to be precharged, at which point the
1878 // power state machine will transition to the idle state, and
1879 // automatically move to a refresh, at that point it will also
1880 // call this method to get the refresh event loop going again
1884 // last but not least we perform the actual refresh
1885 if (refreshState
== REF_START
) {
1886 // should never get here with any banks active
1887 assert(numBanksActive
== 0);
1888 assert(pwrState
== PWR_REF
);
1890 Tick ref_done_at
= curTick() + memory
.tRFC
;
1892 for (auto &b
: banks
) {
1893 b
.actAllowedAt
= ref_done_at
;
1896 // at the moment this affects all ranks
1897 cmdList
.push_back(Command(MemCommand::REF
, 0, curTick()));
1902 DPRINTF(DRAMPower
, "%llu,REF,0,%d\n", divCeil(curTick(), memory
.tCK
) -
1903 memory
.timeStampOffset
, rank
);
1905 // Update for next refresh
1906 refreshDueAt
+= memory
.tREFI
;
1908 // make sure we did not wait so long that we cannot make up
1910 if (refreshDueAt
< ref_done_at
) {
1911 fatal("Refresh was delayed so long we cannot catch up\n");
1914 // Run the refresh and schedule event to transition power states
1915 // when refresh completes
1916 refreshState
= REF_RUN
;
1917 schedule(refreshEvent
, ref_done_at
);
1921 if (refreshState
== REF_RUN
) {
1922 // should never get here with any banks active
1923 assert(numBanksActive
== 0);
1924 assert(pwrState
== PWR_REF
);
1926 assert(!powerEvent
.scheduled());
1928 if ((memory
.drainState() == DrainState::Draining
) ||
1929 (memory
.drainState() == DrainState::Drained
)) {
1930 // if draining, do not re-enter low-power mode.
1931 // simply go to IDLE and wait
1932 schedulePowerEvent(PWR_IDLE
, curTick());
1934 // At the moment, we sleep when the refresh ends and wait to be
1935 // woken up again if previously in a low-power state.
1936 if (pwrStatePostRefresh
!= PWR_IDLE
) {
1937 // power State should be power Refresh
1938 assert(pwrState
== PWR_REF
);
1939 DPRINTF(DRAMState
, "Rank %d sleeping after refresh and was in "
1940 "power state %d before refreshing\n", rank
,
1941 pwrStatePostRefresh
);
1942 powerDownSleep(pwrState
, curTick());
1944 // Force PRE power-down if there are no outstanding commands
1945 // in Q after refresh.
1946 } else if (isQueueEmpty()) {
1947 // still have refresh event outstanding but there should
1948 // be no other events outstanding
1949 assert(outstandingEvents
== 1);
1950 DPRINTF(DRAMState
, "Rank %d sleeping after refresh but was NOT"
1951 " in a low power state before refreshing\n", rank
);
1952 powerDownSleep(PWR_PRE_PDN
, curTick());
1955 // move to the idle power state once the refresh is done, this
1956 // will also move the refresh state machine to the refresh
1958 schedulePowerEvent(PWR_IDLE
, curTick());
1962 // At this point, we have completed the current refresh.
1963 // In the SREF bypass case, we do not get to this state in the
1964 // refresh STM and therefore can always schedule next event.
1965 // Compensate for the delay in actually performing the refresh
1966 // when scheduling the next one
1967 schedule(refreshEvent
, refreshDueAt
- memory
.tRP
);
1969 DPRINTF(DRAMState
, "Refresh done at %llu and next refresh"
1970 " at %llu\n", curTick(), refreshDueAt
);
1975 DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state
, Tick tick
)
1977 // respect causality
1978 assert(tick
>= curTick());
1980 if (!powerEvent
.scheduled()) {
1981 DPRINTF(DRAMState
, "Scheduling power event at %llu to state %d\n",
1984 // insert the new transition
1985 pwrStateTrans
= pwr_state
;
1987 schedule(powerEvent
, tick
);
1989 panic("Scheduled power event at %llu to state %d, "
1990 "with scheduled event at %llu to %d\n", tick
, pwr_state
,
1991 powerEvent
.when(), pwrStateTrans
);
1996 DRAMCtrl::Rank::powerDownSleep(PowerState pwr_state
, Tick tick
)
1998 // if low power state is active low, schedule to active low power state.
1999 // in reality tCKE is needed to enter active low power. This is neglected
2000 // here and could be added in the future.
2001 if (pwr_state
== PWR_ACT_PDN
) {
2002 schedulePowerEvent(pwr_state
, tick
);
2003 // push command to DRAMPower
2004 cmdList
.push_back(Command(MemCommand::PDN_F_ACT
, 0, tick
));
2005 DPRINTF(DRAMPower
, "%llu,PDN_F_ACT,0,%d\n", divCeil(tick
,
2006 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2007 } else if (pwr_state
== PWR_PRE_PDN
) {
2008 // if low power state is precharge low, schedule to precharge low
2009 // power state. In reality tCKE is needed to enter active low power.
2010 // This is neglected here.
2011 schedulePowerEvent(pwr_state
, tick
);
2012 //push Command to DRAMPower
2013 cmdList
.push_back(Command(MemCommand::PDN_F_PRE
, 0, tick
));
2014 DPRINTF(DRAMPower
, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick
,
2015 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2016 } else if (pwr_state
== PWR_REF
) {
2017 // if a refresh just occurred
2018 // transition to PRE_PDN now that all banks are closed
2019 // precharge power down requires tCKE to enter. For simplicity
2020 // this is not considered.
2021 schedulePowerEvent(PWR_PRE_PDN
, tick
);
2022 //push Command to DRAMPower
2023 cmdList
.push_back(Command(MemCommand::PDN_F_PRE
, 0, tick
));
2024 DPRINTF(DRAMPower
, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick
,
2025 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2026 } else if (pwr_state
== PWR_SREF
) {
2027 // should only enter SREF after PRE-PD wakeup to do a refresh
2028 assert(pwrStatePostRefresh
== PWR_PRE_PDN
);
2029 // self refresh requires time tCKESR to enter. For simplicity,
2030 // this is not considered.
2031 schedulePowerEvent(PWR_SREF
, tick
);
2032 // push Command to DRAMPower
2033 cmdList
.push_back(Command(MemCommand::SREN
, 0, tick
));
2034 DPRINTF(DRAMPower
, "%llu,SREN,0,%d\n", divCeil(tick
,
2035 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2037 // Ensure that we don't power-down and back up in same tick
2038 // Once we commit to PD entry, do it and wait for at least 1tCK
2039 // This could be replaced with tCKE if/when that is added to the model
2040 wakeUpAllowedAt
= tick
+ memory
.tCK
;
2042 // Transitioning to a low power state, set flag
2043 inLowPowerState
= true;
2047 DRAMCtrl::Rank::scheduleWakeUpEvent(Tick exit_delay
)
2049 Tick wake_up_tick
= std::max(curTick(), wakeUpAllowedAt
);
2051 DPRINTF(DRAMState
, "Scheduling wake-up for rank %d at tick %d\n",
2052 rank
, wake_up_tick
);
2054 // if waking for refresh, hold previous state
2055 // else reset state back to IDLE
2056 if (refreshState
== REF_PD_EXIT
) {
2057 pwrStatePostRefresh
= pwrState
;
2059 // don't automatically transition back to LP state after next REF
2060 pwrStatePostRefresh
= PWR_IDLE
;
2063 // schedule wake-up with event to ensure entry has completed before
2064 // we try to wake-up
2065 schedule(wakeUpEvent
, wake_up_tick
);
2067 for (auto &b
: banks
) {
2068 // respect both causality and any existing bank
2069 // constraints, some banks could already have a
2070 // (auto) precharge scheduled
2071 b
.wrAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.wrAllowedAt
);
2072 b
.rdAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.rdAllowedAt
);
2073 b
.preAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.preAllowedAt
);
2074 b
.actAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.actAllowedAt
);
2076 // Transitioning out of low power state, clear flag
2077 inLowPowerState
= false;
2079 // push to DRAMPower
2080 // use pwrStateTrans for cases where we have a power event scheduled
2081 // to enter low power that has not yet been processed
2082 if (pwrStateTrans
== PWR_ACT_PDN
) {
2083 cmdList
.push_back(Command(MemCommand::PUP_ACT
, 0, wake_up_tick
));
2084 DPRINTF(DRAMPower
, "%llu,PUP_ACT,0,%d\n", divCeil(wake_up_tick
,
2085 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2087 } else if (pwrStateTrans
== PWR_PRE_PDN
) {
2088 cmdList
.push_back(Command(MemCommand::PUP_PRE
, 0, wake_up_tick
));
2089 DPRINTF(DRAMPower
, "%llu,PUP_PRE,0,%d\n", divCeil(wake_up_tick
,
2090 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2091 } else if (pwrStateTrans
== PWR_SREF
) {
2092 cmdList
.push_back(Command(MemCommand::SREX
, 0, wake_up_tick
));
2093 DPRINTF(DRAMPower
, "%llu,SREX,0,%d\n", divCeil(wake_up_tick
,
2094 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2099 DRAMCtrl::Rank::processWakeUpEvent()
2101 // Should be in a power-down or self-refresh state
2102 assert((pwrState
== PWR_ACT_PDN
) || (pwrState
== PWR_PRE_PDN
) ||
2103 (pwrState
== PWR_SREF
));
2105 // Check current state to determine transition state
2106 if (pwrState
== PWR_ACT_PDN
) {
2107 // banks still open, transition to PWR_ACT
2108 schedulePowerEvent(PWR_ACT
, curTick());
2110 // transitioning from a precharge power-down or self-refresh state
2111 // banks are closed - transition to PWR_IDLE
2112 schedulePowerEvent(PWR_IDLE
, curTick());
2117 DRAMCtrl::Rank::processPowerEvent()
2119 assert(curTick() >= pwrStateTick
);
2120 // remember where we were, and for how long
2121 Tick duration
= curTick() - pwrStateTick
;
2122 PowerState prev_state
= pwrState
;
2124 // update the accounting
2125 pwrStateTime
[prev_state
] += duration
;
2127 // track to total idle time
2128 if ((prev_state
== PWR_PRE_PDN
) || (prev_state
== PWR_ACT_PDN
) ||
2129 (prev_state
== PWR_SREF
)) {
2130 totalIdleTime
+= duration
;
2133 pwrState
= pwrStateTrans
;
2134 pwrStateTick
= curTick();
2136 // if rank was refreshing, make sure to start scheduling requests again
2137 if (prev_state
== PWR_REF
) {
2138 // bus IDLED prior to REF
2139 // counter should be one for refresh command only
2140 assert(outstandingEvents
== 1);
2141 // REF complete, decrement count and go back to IDLE
2142 --outstandingEvents
;
2143 refreshState
= REF_IDLE
;
2145 DPRINTF(DRAMState
, "Was refreshing for %llu ticks\n", duration
);
2146 // if moving back to power-down after refresh
2147 if (pwrState
!= PWR_IDLE
) {
2148 assert(pwrState
== PWR_PRE_PDN
);
2149 DPRINTF(DRAMState
, "Switching to power down state after refreshing"
2150 " rank %d at %llu tick\n", rank
, curTick());
2153 // completed refresh event, ensure next request is scheduled
2154 if (!memory
.nextReqEvent
.scheduled()) {
2155 DPRINTF(DRAM
, "Scheduling next request after refreshing"
2156 " rank %d\n", rank
);
2157 schedule(memory
.nextReqEvent
, curTick());
2161 if ((pwrState
== PWR_ACT
) && (refreshState
== REF_PD_EXIT
)) {
2162 // have exited ACT PD
2163 assert(prev_state
== PWR_ACT_PDN
);
2165 // go back to REF event and close banks
2166 refreshState
= REF_PRE
;
2167 schedule(refreshEvent
, curTick());
2168 } else if (pwrState
== PWR_IDLE
) {
2169 DPRINTF(DRAMState
, "All banks precharged\n");
2170 if (prev_state
== PWR_SREF
) {
2171 // set refresh state to REF_SREF_EXIT, ensuring inRefIdleState
2172 // continues to return false during tXS after SREF exit
2173 // Schedule a refresh which kicks things back into action
2175 refreshState
= REF_SREF_EXIT
;
2176 schedule(refreshEvent
, curTick() + memory
.tXS
);
2178 // if we have a pending refresh, and are now moving to
2179 // the idle state, directly transition to, or schedule refresh
2180 if ((refreshState
== REF_PRE
) || (refreshState
== REF_PD_EXIT
)) {
2181 // ensure refresh is restarted only after final PRE command.
2182 // do not restart refresh if controller is in an intermediate
2183 // state, after PRE_PDN exit, when banks are IDLE but an
2184 // ACT is scheduled.
2185 if (!activateEvent
.scheduled()) {
2186 // there should be nothing waiting at this point
2187 assert(!powerEvent
.scheduled());
2188 if (refreshState
== REF_PD_EXIT
) {
2189 // exiting PRE PD, will be in IDLE until tXP expires
2190 // and then should transition to PWR_REF state
2191 assert(prev_state
== PWR_PRE_PDN
);
2192 schedulePowerEvent(PWR_REF
, curTick() + memory
.tXP
);
2193 } else if (refreshState
== REF_PRE
) {
2194 // can directly move to PWR_REF state and proceed below
2198 // must have PRE scheduled to transition back to IDLE
2199 // and re-kick off refresh
2200 assert(prechargeEvent
.scheduled());
2206 // transition to the refresh state and re-start refresh process
2207 // refresh state machine will schedule the next power state transition
2208 if (pwrState
== PWR_REF
) {
2209 // completed final PRE for refresh or exiting power-down
2210 assert(refreshState
== REF_PRE
|| refreshState
== REF_PD_EXIT
);
2212 // exited PRE PD for refresh, with no pending commands
2213 // bypass auto-refresh and go straight to SREF, where memory
2214 // will issue refresh immediately upon entry
2215 if (pwrStatePostRefresh
== PWR_PRE_PDN
&& isQueueEmpty() &&
2216 (memory
.drainState() != DrainState::Draining
) &&
2217 (memory
.drainState() != DrainState::Drained
)) {
2218 DPRINTF(DRAMState
, "Rank %d bypassing refresh and transitioning "
2219 "to self refresh at %11u tick\n", rank
, curTick());
2220 powerDownSleep(PWR_SREF
, curTick());
2222 // Since refresh was bypassed, remove event by decrementing count
2223 assert(outstandingEvents
== 1);
2224 --outstandingEvents
;
2226 // reset state back to IDLE temporarily until SREF is entered
2227 pwrState
= PWR_IDLE
;
2229 // Not bypassing refresh for SREF entry
2231 DPRINTF(DRAMState
, "Refreshing\n");
2233 // there should be nothing waiting at this point
2234 assert(!powerEvent
.scheduled());
2236 // kick the refresh event loop into action again, and that
2237 // in turn will schedule a transition to the idle power
2238 // state once the refresh is done
2239 schedule(refreshEvent
, curTick());
2241 // Banks transitioned to IDLE, start REF
2242 refreshState
= REF_START
;
2249 DRAMCtrl::Rank::updatePowerStats()
2251 // All commands up to refresh have completed
2252 // flush cmdList to DRAMPower
2255 // Call the function that calculates window energy at intermediate update
2256 // events like at refresh, stats dump as well as at simulation exit.
2257 // Window starts at the last time the calcWindowEnergy function was called
2258 // and is upto current time.
2259 power
.powerlib
.calcWindowEnergy(divCeil(curTick(), memory
.tCK
) -
2260 memory
.timeStampOffset
);
2262 // Get the energy from DRAMPower
2263 Data::MemoryPowerModel::Energy energy
= power
.powerlib
.getEnergy();
2265 // The energy components inside the power lib are calculated over
2266 // the window so accumulate into the corresponding gem5 stat
2267 actEnergy
+= energy
.act_energy
* memory
.devicesPerRank
;
2268 preEnergy
+= energy
.pre_energy
* memory
.devicesPerRank
;
2269 readEnergy
+= energy
.read_energy
* memory
.devicesPerRank
;
2270 writeEnergy
+= energy
.write_energy
* memory
.devicesPerRank
;
2271 refreshEnergy
+= energy
.ref_energy
* memory
.devicesPerRank
;
2272 actBackEnergy
+= energy
.act_stdby_energy
* memory
.devicesPerRank
;
2273 preBackEnergy
+= energy
.pre_stdby_energy
* memory
.devicesPerRank
;
2274 actPowerDownEnergy
+= energy
.f_act_pd_energy
* memory
.devicesPerRank
;
2275 prePowerDownEnergy
+= energy
.f_pre_pd_energy
* memory
.devicesPerRank
;
2276 selfRefreshEnergy
+= energy
.sref_energy
* memory
.devicesPerRank
;
2278 // Accumulate window energy into the total energy.
2279 totalEnergy
+= energy
.window_energy
* memory
.devicesPerRank
;
2280 // Average power must not be accumulated but calculated over the time
2281 // since last stats reset. SimClock::Frequency is tick period not tick
2284 // power (mW) = ----------- * ----------
2285 // time (tick) tick_frequency
2286 averagePower
= (totalEnergy
.value() /
2287 (curTick() - memory
.lastStatsResetTick
)) *
2288 (SimClock::Frequency
/ 1000000000.0);
2292 DRAMCtrl::Rank::computeStats()
2294 DPRINTF(DRAM
,"Computing stats due to a dump callback\n");
2299 // final update of power state times
2300 pwrStateTime
[pwrState
] += (curTick() - pwrStateTick
);
2301 pwrStateTick
= curTick();
2306 DRAMCtrl::Rank::resetStats() {
2307 // The only way to clear the counters in DRAMPower is to call
2308 // calcWindowEnergy function as that then calls clearCounters. The
2309 // clearCounters method itself is private.
2310 power
.powerlib
.calcWindowEnergy(divCeil(curTick(), memory
.tCK
) -
2311 memory
.timeStampOffset
);
2316 DRAMCtrl::Rank::regStats()
2320 .name(name() + ".memoryStateTime")
2321 .desc("Time in different power states");
2322 pwrStateTime
.subname(0, "IDLE");
2323 pwrStateTime
.subname(1, "REF");
2324 pwrStateTime
.subname(2, "SREF");
2325 pwrStateTime
.subname(3, "PRE_PDN");
2326 pwrStateTime
.subname(4, "ACT");
2327 pwrStateTime
.subname(5, "ACT_PDN");
2330 .name(name() + ".actEnergy")
2331 .desc("Energy for activate commands per rank (pJ)");
2334 .name(name() + ".preEnergy")
2335 .desc("Energy for precharge commands per rank (pJ)");
2338 .name(name() + ".readEnergy")
2339 .desc("Energy for read commands per rank (pJ)");
2342 .name(name() + ".writeEnergy")
2343 .desc("Energy for write commands per rank (pJ)");
2346 .name(name() + ".refreshEnergy")
2347 .desc("Energy for refresh commands per rank (pJ)");
2350 .name(name() + ".actBackEnergy")
2351 .desc("Energy for active background per rank (pJ)");
2354 .name(name() + ".preBackEnergy")
2355 .desc("Energy for precharge background per rank (pJ)");
2358 .name(name() + ".actPowerDownEnergy")
2359 .desc("Energy for active power-down per rank (pJ)");
2362 .name(name() + ".prePowerDownEnergy")
2363 .desc("Energy for precharge power-down per rank (pJ)");
2366 .name(name() + ".selfRefreshEnergy")
2367 .desc("Energy for self refresh per rank (pJ)");
2370 .name(name() + ".totalEnergy")
2371 .desc("Total energy per rank (pJ)");
2374 .name(name() + ".averagePower")
2375 .desc("Core power per rank (mW)");
2378 .name(name() + ".totalIdleTime")
2379 .desc("Total Idle time Per DRAM Rank");
2381 Stats::registerDumpCallback(new RankDumpCallback(this));
2382 Stats::registerResetCallback(new RankResetCallback(this));
2385 DRAMCtrl::regStats()
2387 using namespace Stats
;
2389 AbstractMemory::regStats();
2391 for (auto r
: ranks
) {
2395 registerResetCallback(new MemResetCallback(this));
2398 .name(name() + ".readReqs")
2399 .desc("Number of read requests accepted");
2402 .name(name() + ".writeReqs")
2403 .desc("Number of write requests accepted");
2406 .name(name() + ".readBursts")
2407 .desc("Number of DRAM read bursts, "
2408 "including those serviced by the write queue");
2411 .name(name() + ".writeBursts")
2412 .desc("Number of DRAM write bursts, "
2413 "including those merged in the write queue");
2416 .name(name() + ".servicedByWrQ")
2417 .desc("Number of DRAM read bursts serviced by the write queue");
2420 .name(name() + ".mergedWrBursts")
2421 .desc("Number of DRAM write bursts merged with an existing one");
2424 .name(name() + ".neitherReadNorWriteReqs")
2425 .desc("Number of requests that are neither read nor write");
2428 .init(banksPerRank
* ranksPerChannel
)
2429 .name(name() + ".perBankRdBursts")
2430 .desc("Per bank write bursts");
2433 .init(banksPerRank
* ranksPerChannel
)
2434 .name(name() + ".perBankWrBursts")
2435 .desc("Per bank write bursts");
2438 .name(name() + ".avgRdQLen")
2439 .desc("Average read queue length when enqueuing")
2443 .name(name() + ".avgWrQLen")
2444 .desc("Average write queue length when enqueuing")
2448 .name(name() + ".totQLat")
2449 .desc("Total ticks spent queuing");
2452 .name(name() + ".totBusLat")
2453 .desc("Total ticks spent in databus transfers");
2456 .name(name() + ".totMemAccLat")
2457 .desc("Total ticks spent from burst creation until serviced "
2461 .name(name() + ".avgQLat")
2462 .desc("Average queueing delay per DRAM burst")
2465 avgQLat
= totQLat
/ (readBursts
- servicedByWrQ
);
2468 .name(name() + ".avgBusLat")
2469 .desc("Average bus latency per DRAM burst")
2472 avgBusLat
= totBusLat
/ (readBursts
- servicedByWrQ
);
2475 .name(name() + ".avgMemAccLat")
2476 .desc("Average memory access latency per DRAM burst")
2479 avgMemAccLat
= totMemAccLat
/ (readBursts
- servicedByWrQ
);
2482 .name(name() + ".numRdRetry")
2483 .desc("Number of times read queue was full causing retry");
2486 .name(name() + ".numWrRetry")
2487 .desc("Number of times write queue was full causing retry");
2490 .name(name() + ".readRowHits")
2491 .desc("Number of row buffer hits during reads");
2494 .name(name() + ".writeRowHits")
2495 .desc("Number of row buffer hits during writes");
2498 .name(name() + ".readRowHitRate")
2499 .desc("Row buffer hit rate for reads")
2502 readRowHitRate
= (readRowHits
/ (readBursts
- servicedByWrQ
)) * 100;
2505 .name(name() + ".writeRowHitRate")
2506 .desc("Row buffer hit rate for writes")
2509 writeRowHitRate
= (writeRowHits
/ (writeBursts
- mergedWrBursts
)) * 100;
2512 .init(ceilLog2(burstSize
) + 1)
2513 .name(name() + ".readPktSize")
2514 .desc("Read request sizes (log2)");
2517 .init(ceilLog2(burstSize
) + 1)
2518 .name(name() + ".writePktSize")
2519 .desc("Write request sizes (log2)");
2522 .init(readBufferSize
)
2523 .name(name() + ".rdQLenPdf")
2524 .desc("What read queue length does an incoming req see");
2527 .init(writeBufferSize
)
2528 .name(name() + ".wrQLenPdf")
2529 .desc("What write queue length does an incoming req see");
2532 .init(maxAccessesPerRow
)
2533 .name(name() + ".bytesPerActivate")
2534 .desc("Bytes accessed per row activation")
2538 .init(readBufferSize
)
2539 .name(name() + ".rdPerTurnAround")
2540 .desc("Reads before turning the bus around for writes")
2544 .init(writeBufferSize
)
2545 .name(name() + ".wrPerTurnAround")
2546 .desc("Writes before turning the bus around for reads")
2550 .name(name() + ".bytesReadDRAM")
2551 .desc("Total number of bytes read from DRAM");
2554 .name(name() + ".bytesReadWrQ")
2555 .desc("Total number of bytes read from write queue");
2558 .name(name() + ".bytesWritten")
2559 .desc("Total number of bytes written to DRAM");
2562 .name(name() + ".bytesReadSys")
2563 .desc("Total read bytes from the system interface side");
2566 .name(name() + ".bytesWrittenSys")
2567 .desc("Total written bytes from the system interface side");
2570 .name(name() + ".avgRdBW")
2571 .desc("Average DRAM read bandwidth in MiByte/s")
2574 avgRdBW
= (bytesReadDRAM
/ 1000000) / simSeconds
;
2577 .name(name() + ".avgWrBW")
2578 .desc("Average achieved write bandwidth in MiByte/s")
2581 avgWrBW
= (bytesWritten
/ 1000000) / simSeconds
;
2584 .name(name() + ".avgRdBWSys")
2585 .desc("Average system read bandwidth in MiByte/s")
2588 avgRdBWSys
= (bytesReadSys
/ 1000000) / simSeconds
;
2591 .name(name() + ".avgWrBWSys")
2592 .desc("Average system write bandwidth in MiByte/s")
2595 avgWrBWSys
= (bytesWrittenSys
/ 1000000) / simSeconds
;
2598 .name(name() + ".peakBW")
2599 .desc("Theoretical peak bandwidth in MiByte/s")
2602 peakBW
= (SimClock::Frequency
/ tBURST
) * burstSize
/ 1000000;
2605 .name(name() + ".busUtil")
2606 .desc("Data bus utilization in percentage")
2608 busUtil
= (avgRdBW
+ avgWrBW
) / peakBW
* 100;
2611 .name(name() + ".totGap")
2612 .desc("Total gap between requests");
2615 .name(name() + ".avgGap")
2616 .desc("Average gap between requests")
2619 avgGap
= totGap
/ (readReqs
+ writeReqs
);
2621 // Stats for DRAM Power calculation based on Micron datasheet
2623 .name(name() + ".busUtilRead")
2624 .desc("Data bus utilization in percentage for reads")
2627 busUtilRead
= avgRdBW
/ peakBW
* 100;
2630 .name(name() + ".busUtilWrite")
2631 .desc("Data bus utilization in percentage for writes")
2634 busUtilWrite
= avgWrBW
/ peakBW
* 100;
2637 .name(name() + ".pageHitRate")
2638 .desc("Row buffer hit rate, read and write combined")
2641 pageHitRate
= (writeRowHits
+ readRowHits
) /
2642 (writeBursts
- mergedWrBursts
+ readBursts
- servicedByWrQ
) * 100;
2646 DRAMCtrl::recvFunctional(PacketPtr pkt
)
2648 // rely on the abstract memory
2649 functionalAccess(pkt
);
2653 DRAMCtrl::getSlavePort(const string
&if_name
, PortID idx
)
2655 if (if_name
!= "port") {
2656 return MemObject::getSlavePort(if_name
, idx
);
2665 // if there is anything in any of our internal queues, keep track
2667 if (!(writeQueue
.empty() && readQueue
.empty() && respQueue
.empty() &&
2668 allRanksDrained())) {
2670 DPRINTF(Drain
, "DRAM controller not drained, write: %d, read: %d,"
2671 " resp: %d\n", writeQueue
.size(), readQueue
.size(),
2674 // the only queue that is not drained automatically over time
2675 // is the write queue, thus kick things into action if needed
2676 if (!writeQueue
.empty() && !nextReqEvent
.scheduled()) {
2677 schedule(nextReqEvent
, curTick());
2680 // also need to kick off events to exit self-refresh
2681 for (auto r
: ranks
) {
2682 // force self-refresh exit, which in turn will issue auto-refresh
2683 if (r
->pwrState
== PWR_SREF
) {
2684 DPRINTF(DRAM
,"Rank%d: Forcing self-refresh wakeup in drain\n",
2686 r
->scheduleWakeUpEvent(tXS
);
2690 return DrainState::Draining
;
2692 return DrainState::Drained
;
2697 DRAMCtrl::allRanksDrained() const
2699 // true until proven false
2700 bool all_ranks_drained
= true;
2701 for (auto r
: ranks
) {
2702 // then verify that the power state is IDLE ensuring all banks are
2703 // closed and rank is not in a low power state. Also verify that rank
2704 // is idle from a refresh point of view.
2705 all_ranks_drained
= r
->inPwrIdleState() && r
->inRefIdleState() &&
2708 return all_ranks_drained
;
2712 DRAMCtrl::drainResume()
2714 if (!isTimingMode
&& system()->isTimingMode()) {
2715 // if we switched to timing mode, kick things into action,
2716 // and behave as if we restored from a checkpoint
2718 } else if (isTimingMode
&& !system()->isTimingMode()) {
2719 // if we switch from timing mode, stop the refresh events to
2720 // not cause issues with KVM
2721 for (auto r
: ranks
) {
2727 isTimingMode
= system()->isTimingMode();
2730 DRAMCtrl::MemoryPort::MemoryPort(const std::string
& name
, DRAMCtrl
& _memory
)
2731 : QueuedSlavePort(name
, &_memory
, queue
), queue(_memory
, *this),
2736 DRAMCtrl::MemoryPort::getAddrRanges() const
2738 AddrRangeList ranges
;
2739 ranges
.push_back(memory
.getAddrRange());
2744 DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt
)
2746 pkt
->pushLabel(memory
.name());
2748 if (!queue
.checkFunctional(pkt
)) {
2749 // Default implementation of SimpleTimingPort::recvFunctional()
2750 // calls recvAtomic() and throws away the latency; we can save a
2751 // little here by just not calculating the latency.
2752 memory
.recvFunctional(pkt
);
2759 DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt
)
2761 return memory
.recvAtomic(pkt
);
2765 DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt
)
2767 // pass it to the memory controller
2768 return memory
.recvTimingReq(pkt
);
2772 DRAMCtrlParams::create()
2774 return new DRAMCtrl(this);