2 * Copyright (c) 2010-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
45 #include "base/bitfield.hh"
46 #include "base/trace.hh"
47 #include "debug/DRAM.hh"
48 #include "debug/DRAMPower.hh"
49 #include "debug/DRAMState.hh"
50 #include "debug/Drain.hh"
51 #include "mem/dram_ctrl.hh"
52 #include "sim/system.hh"
57 DRAMCtrl::DRAMCtrl(const DRAMCtrlParams
* p
) :
59 port(name() + ".port", *this),
60 retryRdReq(false), retryWrReq(false),
62 nextReqEvent(this), respondEvent(this), activateEvent(this),
63 prechargeEvent(this), refreshEvent(this), powerEvent(this),
65 deviceSize(p
->device_size
),
66 deviceBusWidth(p
->device_bus_width
), burstLength(p
->burst_length
),
67 deviceRowBufferSize(p
->device_rowbuffer_size
),
68 devicesPerRank(p
->devices_per_rank
),
69 burstSize((devicesPerRank
* burstLength
* deviceBusWidth
) / 8),
70 rowBufferSize(devicesPerRank
* deviceRowBufferSize
),
71 columnsPerRowBuffer(rowBufferSize
/ burstSize
),
72 columnsPerStripe(range
.granularity() / burstSize
),
73 ranksPerChannel(p
->ranks_per_channel
),
74 bankGroupsPerRank(p
->bank_groups_per_rank
),
75 bankGroupArch(p
->bank_groups_per_rank
> 0),
76 banksPerRank(p
->banks_per_rank
), channels(p
->channels
), rowsPerBank(0),
77 readBufferSize(p
->read_buffer_size
),
78 writeBufferSize(p
->write_buffer_size
),
79 writeHighThreshold(writeBufferSize
* p
->write_high_thresh_perc
/ 100.0),
80 writeLowThreshold(writeBufferSize
* p
->write_low_thresh_perc
/ 100.0),
81 minWritesPerSwitch(p
->min_writes_per_switch
),
82 writesThisTime(0), readsThisTime(0),
83 tCK(p
->tCK
), tWTR(p
->tWTR
), tRTW(p
->tRTW
), tCS(p
->tCS
), tBURST(p
->tBURST
),
84 tCCD_L(p
->tCCD_L
), tRCD(p
->tRCD
), tCL(p
->tCL
), tRP(p
->tRP
), tRAS(p
->tRAS
),
85 tWR(p
->tWR
), tRTP(p
->tRTP
), tRFC(p
->tRFC
), tREFI(p
->tREFI
), tRRD(p
->tRRD
),
86 tRRD_L(p
->tRRD_L
), tXAW(p
->tXAW
), activationLimit(p
->activation_limit
),
87 memSchedPolicy(p
->mem_sched_policy
), addrMapping(p
->addr_mapping
),
88 pageMgmt(p
->page_policy
),
89 maxAccessesPerRow(p
->max_accesses_per_row
),
90 frontendLatency(p
->static_frontend_latency
),
91 backendLatency(p
->static_backend_latency
),
92 busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE
),
93 pwrStateTrans(PWR_IDLE
), pwrState(PWR_IDLE
), prevArrival(0),
94 nextReqTime(0), pwrStateTick(0), numBanksActive(0),
95 activeRank(0), timeStampOffset(0)
97 // create the bank states based on the dimensions of the ranks and
99 banks
.resize(ranksPerChannel
);
101 //create list of drampower objects. For each rank 1 drampower instance.
102 for (int i
= 0; i
< ranksPerChannel
; i
++) {
103 DRAMPower drampower
= DRAMPower(p
, false);
104 rankPower
.emplace_back(drampower
);
107 actTicks
.resize(ranksPerChannel
);
108 for (size_t c
= 0; c
< ranksPerChannel
; ++c
) {
109 banks
[c
].resize(banksPerRank
);
110 actTicks
[c
].resize(activationLimit
, 0);
113 // set the bank indices
114 for (int r
= 0; r
< ranksPerChannel
; r
++) {
115 for (int b
= 0; b
< banksPerRank
; b
++) {
116 banks
[r
][b
].rank
= r
;
117 banks
[r
][b
].bank
= b
;
118 // GDDR addressing of banks to BG is linear.
119 // Here we assume that all DRAM generations address bank groups as
122 // Simply assign lower bits to bank group in order to
123 // rotate across bank groups as banks are incremented
124 // e.g. with 4 banks per bank group and 16 banks total:
125 // banks 0,4,8,12 are in bank group 0
126 // banks 1,5,9,13 are in bank group 1
127 // banks 2,6,10,14 are in bank group 2
128 // banks 3,7,11,15 are in bank group 3
129 banks
[r
][b
].bankgr
= b
% bankGroupsPerRank
;
131 // No bank groups; simply assign to bank number
132 banks
[r
][b
].bankgr
= b
;
137 // perform a basic check of the write thresholds
138 if (p
->write_low_thresh_perc
>= p
->write_high_thresh_perc
)
139 fatal("Write buffer low threshold %d must be smaller than the "
140 "high threshold %d\n", p
->write_low_thresh_perc
,
141 p
->write_high_thresh_perc
);
143 // determine the rows per bank by looking at the total capacity
144 uint64_t capacity
= ULL(1) << ceilLog2(AbstractMemory::size());
146 // determine the dram actual capacity from the DRAM config in Mbytes
147 uint64_t deviceCapacity
= deviceSize
/ (1024 * 1024) * devicesPerRank
*
150 // if actual DRAM size does not match memory capacity in system warn!
151 if (deviceCapacity
!= capacity
/ (1024 * 1024))
152 warn("DRAM device capacity (%d Mbytes) does not match the "
153 "address range assigned (%d Mbytes)\n", deviceCapacity
,
154 capacity
/ (1024 * 1024));
156 DPRINTF(DRAM
, "Memory capacity %lld (%lld) bytes\n", capacity
,
157 AbstractMemory::size());
159 DPRINTF(DRAM
, "Row buffer size %d bytes with %d columns per row buffer\n",
160 rowBufferSize
, columnsPerRowBuffer
);
162 rowsPerBank
= capacity
/ (rowBufferSize
* banksPerRank
* ranksPerChannel
);
164 // a bit of sanity checks on the interleaving
165 if (range
.interleaved()) {
166 if (channels
!= range
.stripes())
167 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
168 name(), range
.stripes(), channels
);
170 if (addrMapping
== Enums::RoRaBaChCo
) {
171 if (rowBufferSize
!= range
.granularity()) {
172 fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
173 "address map\n", name());
175 } else if (addrMapping
== Enums::RoRaBaCoCh
||
176 addrMapping
== Enums::RoCoRaBaCh
) {
177 // for the interleavings with channel bits in the bottom,
178 // if the system uses a channel striping granularity that
179 // is larger than the DRAM burst size, then map the
180 // sequential accesses within a stripe to a number of
181 // columns in the DRAM, effectively placing some of the
182 // lower-order column bits as the least-significant bits
183 // of the address (above the ones denoting the burst size)
184 assert(columnsPerStripe
>= 1);
186 // channel striping has to be done at a granularity that
187 // is equal or larger to a cache line
188 if (system()->cacheLineSize() > range
.granularity()) {
189 fatal("Channel interleaving of %s must be at least as large "
190 "as the cache line size\n", name());
193 // ...and equal or smaller than the row-buffer size
194 if (rowBufferSize
< range
.granularity()) {
195 fatal("Channel interleaving of %s must be at most as large "
196 "as the row-buffer size\n", name());
198 // this is essentially the check above, so just to be sure
199 assert(columnsPerStripe
<= columnsPerRowBuffer
);
203 // some basic sanity checks
204 if (tREFI
<= tRP
|| tREFI
<= tRFC
) {
205 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
209 // basic bank group architecture checks ->
211 // must have at least one bank per bank group
212 if (bankGroupsPerRank
> banksPerRank
) {
213 fatal("banks per rank (%d) must be equal to or larger than "
214 "banks groups per rank (%d)\n",
215 banksPerRank
, bankGroupsPerRank
);
217 // must have same number of banks in each bank group
218 if ((banksPerRank
% bankGroupsPerRank
) != 0) {
219 fatal("Banks per rank (%d) must be evenly divisible by bank groups "
220 "per rank (%d) for equal banks per bank group\n",
221 banksPerRank
, bankGroupsPerRank
);
223 // tCCD_L should be greater than minimal, back-to-back burst delay
224 if (tCCD_L
<= tBURST
) {
225 fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
226 "bank groups per rank (%d) is greater than 1\n",
227 tCCD_L
, tBURST
, bankGroupsPerRank
);
229 // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
230 // some datasheets might specify it equal to tRRD
232 fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
233 "bank groups per rank (%d) is greater than 1\n",
234 tRRD_L
, tRRD
, bankGroupsPerRank
);
243 AbstractMemory::init();
245 if (!port
.isConnected()) {
246 fatal("DRAMCtrl %s is unconnected!\n", name());
248 port
.sendRangeChange();
255 // timestamp offset should be in clock cycles for DRAMPower
256 timeStampOffset
= divCeil(curTick(), tCK
);
257 // update the start tick for the precharge accounting to the
259 pwrStateTick
= curTick();
261 // shift the bus busy time sufficiently far ahead that we never
262 // have to worry about negative values when computing the time for
263 // the next request, this will add an insignificant bubble at the
264 // start of simulation
265 busBusyUntil
= curTick() + tRP
+ tRCD
+ tCL
;
267 // kick off the refresh, and give ourselves enough time to
269 schedule(refreshEvent
, curTick() + tREFI
- tRP
);
273 DRAMCtrl::recvAtomic(PacketPtr pkt
)
275 DPRINTF(DRAM
, "recvAtomic: %s 0x%x\n", pkt
->cmdString(), pkt
->getAddr());
277 // do the actual memory access and turn the packet into a response
281 if (!pkt
->memInhibitAsserted() && pkt
->hasData()) {
282 // this value is not supposed to be accurate, just enough to
283 // keep things going, mimic a closed page
284 latency
= tRP
+ tRCD
+ tCL
;
290 DRAMCtrl::readQueueFull(unsigned int neededEntries
) const
292 DPRINTF(DRAM
, "Read queue limit %d, current size %d, entries needed %d\n",
293 readBufferSize
, readQueue
.size() + respQueue
.size(),
297 (readQueue
.size() + respQueue
.size() + neededEntries
) > readBufferSize
;
301 DRAMCtrl::writeQueueFull(unsigned int neededEntries
) const
303 DPRINTF(DRAM
, "Write queue limit %d, current size %d, entries needed %d\n",
304 writeBufferSize
, writeQueue
.size(), neededEntries
);
305 return (writeQueue
.size() + neededEntries
) > writeBufferSize
;
308 DRAMCtrl::DRAMPacket
*
309 DRAMCtrl::decodeAddr(PacketPtr pkt
, Addr dramPktAddr
, unsigned size
,
312 // decode the address based on the address mapping scheme, with
313 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
314 // channel, respectively
317 // use a 64-bit unsigned during the computations as the row is
318 // always the top bits, and check before creating the DRAMPacket
321 // truncate the address to a DRAM burst, which makes it unique to
322 // a specific column, row, bank, rank and channel
323 Addr addr
= dramPktAddr
/ burstSize
;
325 // we have removed the lowest order address bits that denote the
326 // position within the column
327 if (addrMapping
== Enums::RoRaBaChCo
) {
328 // the lowest order bits denote the column to ensure that
329 // sequential cache lines occupy the same row
330 addr
= addr
/ columnsPerRowBuffer
;
332 // take out the channel part of the address
333 addr
= addr
/ channels
;
335 // after the channel bits, get the bank bits to interleave
337 bank
= addr
% banksPerRank
;
338 addr
= addr
/ banksPerRank
;
340 // after the bank, we get the rank bits which thus interleaves
342 rank
= addr
% ranksPerChannel
;
343 addr
= addr
/ ranksPerChannel
;
345 // lastly, get the row bits
346 row
= addr
% rowsPerBank
;
347 addr
= addr
/ rowsPerBank
;
348 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
349 // take out the lower-order column bits
350 addr
= addr
/ columnsPerStripe
;
352 // take out the channel part of the address
353 addr
= addr
/ channels
;
355 // next, the higher-order column bites
356 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
358 // after the column bits, we get the bank bits to interleave
360 bank
= addr
% banksPerRank
;
361 addr
= addr
/ banksPerRank
;
363 // after the bank, we get the rank bits which thus interleaves
365 rank
= addr
% ranksPerChannel
;
366 addr
= addr
/ ranksPerChannel
;
368 // lastly, get the row bits
369 row
= addr
% rowsPerBank
;
370 addr
= addr
/ rowsPerBank
;
371 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
372 // optimise for closed page mode and utilise maximum
373 // parallelism of the DRAM (at the cost of power)
375 // take out the lower-order column bits
376 addr
= addr
/ columnsPerStripe
;
378 // take out the channel part of the address, not that this has
379 // to match with how accesses are interleaved between the
380 // controllers in the address mapping
381 addr
= addr
/ channels
;
383 // start with the bank bits, as this provides the maximum
384 // opportunity for parallelism between requests
385 bank
= addr
% banksPerRank
;
386 addr
= addr
/ banksPerRank
;
388 // next get the rank bits
389 rank
= addr
% ranksPerChannel
;
390 addr
= addr
/ ranksPerChannel
;
392 // next, the higher-order column bites
393 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
395 // lastly, get the row bits
396 row
= addr
% rowsPerBank
;
397 addr
= addr
/ rowsPerBank
;
399 panic("Unknown address mapping policy chosen!");
401 assert(rank
< ranksPerChannel
);
402 assert(bank
< banksPerRank
);
403 assert(row
< rowsPerBank
);
404 assert(row
< Bank::NO_ROW
);
406 DPRINTF(DRAM
, "Address: %lld Rank %d Bank %d Row %d\n",
407 dramPktAddr
, rank
, bank
, row
);
409 // create the corresponding DRAM packet with the entry time and
410 // ready time set to the current tick, the latter will be updated
412 uint16_t bank_id
= banksPerRank
* rank
+ bank
;
413 return new DRAMPacket(pkt
, isRead
, rank
, bank
, row
, bank_id
, dramPktAddr
,
414 size
, banks
[rank
][bank
]);
418 DRAMCtrl::addToReadQueue(PacketPtr pkt
, unsigned int pktCount
)
420 // only add to the read queue here. whenever the request is
421 // eventually done, set the readyTime, and call schedule()
422 assert(!pkt
->isWrite());
424 assert(pktCount
!= 0);
426 // if the request size is larger than burst size, the pkt is split into
427 // multiple DRAM packets
428 // Note if the pkt starting address is not aligened to burst size, the
429 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
430 // are aligned to burst size boundaries. This is to ensure we accurately
431 // check read packets against packets in write queue.
432 Addr addr
= pkt
->getAddr();
433 unsigned pktsServicedByWrQ
= 0;
434 BurstHelper
* burst_helper
= NULL
;
435 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
436 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
437 pkt
->getAddr() + pkt
->getSize()) - addr
;
438 readPktSize
[ceilLog2(size
)]++;
441 // First check write buffer to see if the data is already at
443 bool foundInWrQ
= false;
444 for (auto i
= writeQueue
.begin(); i
!= writeQueue
.end(); ++i
) {
445 // check if the read is subsumed in the write entry we are
447 if ((*i
)->addr
<= addr
&&
448 (addr
+ size
) <= ((*i
)->addr
+ (*i
)->size
)) {
452 DPRINTF(DRAM
, "Read to addr %lld with size %d serviced by "
453 "write queue\n", addr
, size
);
454 bytesReadWrQ
+= burstSize
;
459 // If not found in the write q, make a DRAM packet and
460 // push it onto the read queue
463 // Make the burst helper for split packets
464 if (pktCount
> 1 && burst_helper
== NULL
) {
465 DPRINTF(DRAM
, "Read to addr %lld translates to %d "
466 "dram requests\n", pkt
->getAddr(), pktCount
);
467 burst_helper
= new BurstHelper(pktCount
);
470 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, true);
471 dram_pkt
->burstHelper
= burst_helper
;
473 assert(!readQueueFull(1));
474 rdQLenPdf
[readQueue
.size() + respQueue
.size()]++;
476 DPRINTF(DRAM
, "Adding to read queue\n");
478 readQueue
.push_back(dram_pkt
);
481 avgRdQLen
= readQueue
.size() + respQueue
.size();
484 // Starting address of next dram pkt (aligend to burstSize boundary)
485 addr
= (addr
| (burstSize
- 1)) + 1;
488 // If all packets are serviced by write queue, we send the repsonse back
489 if (pktsServicedByWrQ
== pktCount
) {
490 accessAndRespond(pkt
, frontendLatency
);
494 // Update how many split packets are serviced by write queue
495 if (burst_helper
!= NULL
)
496 burst_helper
->burstsServiced
= pktsServicedByWrQ
;
498 // If we are not already scheduled to get a request out of the
500 if (!nextReqEvent
.scheduled()) {
501 DPRINTF(DRAM
, "Request scheduled immediately\n");
502 schedule(nextReqEvent
, curTick());
507 DRAMCtrl::addToWriteQueue(PacketPtr pkt
, unsigned int pktCount
)
509 // only add to the write queue here. whenever the request is
510 // eventually done, set the readyTime, and call schedule()
511 assert(pkt
->isWrite());
513 // if the request size is larger than burst size, the pkt is split into
514 // multiple DRAM packets
515 Addr addr
= pkt
->getAddr();
516 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
517 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
518 pkt
->getAddr() + pkt
->getSize()) - addr
;
519 writePktSize
[ceilLog2(size
)]++;
522 // see if we can merge with an existing item in the write
523 // queue and keep track of whether we have merged or not so we
524 // can stop at that point and also avoid enqueueing a new
527 auto w
= writeQueue
.begin();
529 while(!merged
&& w
!= writeQueue
.end()) {
530 // either of the two could be first, if they are the same
531 // it does not matter which way we go
532 if ((*w
)->addr
>= addr
) {
533 // the existing one starts after the new one, figure
534 // out where the new one ends with respect to the
536 if ((addr
+ size
) >= ((*w
)->addr
+ (*w
)->size
)) {
537 // check if the existing one is completely
538 // subsumed in the new one
539 DPRINTF(DRAM
, "Merging write covering existing burst\n");
541 // update both the address and the size
544 } else if ((addr
+ size
) >= (*w
)->addr
&&
545 ((*w
)->addr
+ (*w
)->size
- addr
) <= burstSize
) {
546 // the new one is just before or partially
547 // overlapping with the existing one, and together
548 // they fit within a burst
549 DPRINTF(DRAM
, "Merging write before existing burst\n");
551 // the existing queue item needs to be adjusted with
552 // respect to both address and size
553 (*w
)->size
= (*w
)->addr
+ (*w
)->size
- addr
;
557 // the new one starts after the current one, figure
558 // out where the existing one ends with respect to the
560 if (((*w
)->addr
+ (*w
)->size
) >= (addr
+ size
)) {
561 // check if the new one is completely subsumed in the
563 DPRINTF(DRAM
, "Merging write into existing burst\n");
565 // no adjustments necessary
566 } else if (((*w
)->addr
+ (*w
)->size
) >= addr
&&
567 (addr
+ size
- (*w
)->addr
) <= burstSize
) {
568 // the existing one is just before or partially
569 // overlapping with the new one, and together
570 // they fit within a burst
571 DPRINTF(DRAM
, "Merging write after existing burst\n");
573 // the address is right, and only the size has
575 (*w
)->size
= addr
+ size
- (*w
)->addr
;
581 // if the item was not merged we need to create a new write
584 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, false);
586 assert(writeQueue
.size() < writeBufferSize
);
587 wrQLenPdf
[writeQueue
.size()]++;
589 DPRINTF(DRAM
, "Adding to write queue\n");
591 writeQueue
.push_back(dram_pkt
);
594 avgWrQLen
= writeQueue
.size();
596 // keep track of the fact that this burst effectively
597 // disappeared as it was merged with an existing one
601 // Starting address of next dram pkt (aligend to burstSize boundary)
602 addr
= (addr
| (burstSize
- 1)) + 1;
605 // we do not wait for the writes to be send to the actual memory,
606 // but instead take responsibility for the consistency here and
607 // snoop the write queue for any upcoming reads
608 // @todo, if a pkt size is larger than burst size, we might need a
609 // different front end latency
610 accessAndRespond(pkt
, frontendLatency
);
612 // If we are not already scheduled to get a request out of the
614 if (!nextReqEvent
.scheduled()) {
615 DPRINTF(DRAM
, "Request scheduled immediately\n");
616 schedule(nextReqEvent
, curTick());
621 DRAMCtrl::printQs() const {
622 DPRINTF(DRAM
, "===READ QUEUE===\n\n");
623 for (auto i
= readQueue
.begin() ; i
!= readQueue
.end() ; ++i
) {
624 DPRINTF(DRAM
, "Read %lu\n", (*i
)->addr
);
626 DPRINTF(DRAM
, "\n===RESP QUEUE===\n\n");
627 for (auto i
= respQueue
.begin() ; i
!= respQueue
.end() ; ++i
) {
628 DPRINTF(DRAM
, "Response %lu\n", (*i
)->addr
);
630 DPRINTF(DRAM
, "\n===WRITE QUEUE===\n\n");
631 for (auto i
= writeQueue
.begin() ; i
!= writeQueue
.end() ; ++i
) {
632 DPRINTF(DRAM
, "Write %lu\n", (*i
)->addr
);
637 DRAMCtrl::recvTimingReq(PacketPtr pkt
)
639 /// @todo temporary hack to deal with memory corruption issues until
640 /// 4-phase transactions are complete
641 for (int x
= 0; x
< pendingDelete
.size(); x
++)
642 delete pendingDelete
[x
];
643 pendingDelete
.clear();
645 // This is where we enter from the outside world
646 DPRINTF(DRAM
, "recvTimingReq: request %s addr %lld size %d\n",
647 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
649 // simply drop inhibited packets for now
650 if (pkt
->memInhibitAsserted()) {
651 DPRINTF(DRAM
, "Inhibited packet -- Dropping it now\n");
652 pendingDelete
.push_back(pkt
);
656 // Calc avg gap between requests
657 if (prevArrival
!= 0) {
658 totGap
+= curTick() - prevArrival
;
660 prevArrival
= curTick();
663 // Find out how many dram packets a pkt translates to
664 // If the burst size is equal or larger than the pkt size, then a pkt
665 // translates to only one dram packet. Otherwise, a pkt translates to
666 // multiple dram packets
667 unsigned size
= pkt
->getSize();
668 unsigned offset
= pkt
->getAddr() & (burstSize
- 1);
669 unsigned int dram_pkt_count
= divCeil(offset
+ size
, burstSize
);
671 // check local buffers and do not accept if full
674 if (readQueueFull(dram_pkt_count
)) {
675 DPRINTF(DRAM
, "Read queue full, not accepting\n");
676 // remember that we have to retry this port
681 addToReadQueue(pkt
, dram_pkt_count
);
683 bytesReadSys
+= size
;
685 } else if (pkt
->isWrite()) {
687 if (writeQueueFull(dram_pkt_count
)) {
688 DPRINTF(DRAM
, "Write queue full, not accepting\n");
689 // remember that we have to retry this port
694 addToWriteQueue(pkt
, dram_pkt_count
);
696 bytesWrittenSys
+= size
;
699 DPRINTF(DRAM
,"Neither read nor write, ignore timing\n");
700 neitherReadNorWrite
++;
701 accessAndRespond(pkt
, 1);
708 DRAMCtrl::processRespondEvent()
711 "processRespondEvent(): Some req has reached its readyTime\n");
713 DRAMPacket
* dram_pkt
= respQueue
.front();
715 if (dram_pkt
->burstHelper
) {
716 // it is a split packet
717 dram_pkt
->burstHelper
->burstsServiced
++;
718 if (dram_pkt
->burstHelper
->burstsServiced
==
719 dram_pkt
->burstHelper
->burstCount
) {
720 // we have now serviced all children packets of a system packet
721 // so we can now respond to the requester
722 // @todo we probably want to have a different front end and back
723 // end latency for split packets
724 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
725 delete dram_pkt
->burstHelper
;
726 dram_pkt
->burstHelper
= NULL
;
729 // it is not a split packet
730 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
733 delete respQueue
.front();
734 respQueue
.pop_front();
736 if (!respQueue
.empty()) {
737 assert(respQueue
.front()->readyTime
>= curTick());
738 assert(!respondEvent
.scheduled());
739 schedule(respondEvent
, respQueue
.front()->readyTime
);
741 // if there is nothing left in any queue, signal a drain
742 if (writeQueue
.empty() && readQueue
.empty() &&
744 DPRINTF(Drain
, "DRAM controller done draining\n");
745 drainManager
->signalDrainDone();
750 // We have made a location in the queue available at this point,
751 // so if there is a read that was forced to wait, retry now
759 DRAMCtrl::chooseNext(std::deque
<DRAMPacket
*>& queue
, bool switched_cmd_type
)
761 // This method does the arbitration between requests. The chosen
762 // packet is simply moved to the head of the queue. The other
763 // methods know that this is the place to look. For example, with
764 // FCFS, this method does nothing
765 assert(!queue
.empty());
767 if (queue
.size() == 1) {
768 DPRINTF(DRAM
, "Single request, nothing to do\n");
772 if (memSchedPolicy
== Enums::fcfs
) {
773 // Do nothing, since the correct request is already head
774 } else if (memSchedPolicy
== Enums::frfcfs
) {
775 reorderQueue(queue
, switched_cmd_type
);
777 panic("No scheduling policy chosen\n");
781 DRAMCtrl::reorderQueue(std::deque
<DRAMPacket
*>& queue
, bool switched_cmd_type
)
783 // Only determine this when needed
784 uint64_t earliest_banks
= 0;
786 // Search for row hits first, if no row hit is found then schedule the
787 // packet to one of the earliest banks available
788 bool found_earliest_pkt
= false;
789 bool found_prepped_diff_rank_pkt
= false;
790 auto selected_pkt_it
= queue
.begin();
792 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
793 DRAMPacket
* dram_pkt
= *i
;
794 const Bank
& bank
= dram_pkt
->bankRef
;
795 // Check if it is a row hit
796 if (bank
.openRow
== dram_pkt
->row
) {
797 if (dram_pkt
->rank
== activeRank
|| switched_cmd_type
) {
798 // FCFS within the hits, giving priority to commands
799 // that access the same rank as the previous burst
800 // to minimize bus turnaround delays
801 // Only give rank prioity when command type is not changing
802 DPRINTF(DRAM
, "Row buffer hit\n");
805 } else if (!found_prepped_diff_rank_pkt
) {
806 // found row hit for command on different rank than prev burst
808 found_prepped_diff_rank_pkt
= true;
810 } else if (!found_earliest_pkt
& !found_prepped_diff_rank_pkt
) {
812 // haven't found an entry with a row hit to a new rank
813 if (earliest_banks
== 0)
814 // Determine entries with earliest bank prep delay
815 // Function will give priority to commands that access the
816 // same rank as previous burst and can prep the bank seamlessly
817 earliest_banks
= minBankPrep(queue
, switched_cmd_type
);
819 // FCFS - Bank is first available bank
820 if (bits(earliest_banks
, dram_pkt
->bankId
, dram_pkt
->bankId
)) {
821 // Remember the packet to be scheduled to one of the earliest
822 // banks available, FCFS amongst the earliest banks
824 found_earliest_pkt
= true;
829 DRAMPacket
* selected_pkt
= *selected_pkt_it
;
830 queue
.erase(selected_pkt_it
);
831 queue
.push_front(selected_pkt
);
835 DRAMCtrl::accessAndRespond(PacketPtr pkt
, Tick static_latency
)
837 DPRINTF(DRAM
, "Responding to Address %lld.. ",pkt
->getAddr());
839 bool needsResponse
= pkt
->needsResponse();
840 // do the actual memory access which also turns the packet into a
844 // turn packet around to go back to requester if response expected
846 // access already turned the packet into a response
847 assert(pkt
->isResponse());
849 // @todo someone should pay for this
850 pkt
->firstWordDelay
= pkt
->lastWordDelay
= 0;
852 // queue the packet in the response queue to be sent out after
853 // the static latency has passed
854 port
.schedTimingResp(pkt
, curTick() + static_latency
);
856 // @todo the packet is going to be deleted, and the DRAMPacket
857 // is still having a pointer to it
858 pendingDelete
.push_back(pkt
);
861 DPRINTF(DRAM
, "Done\n");
867 DRAMCtrl::activateBank(Bank
& bank
, Tick act_tick
, uint32_t row
)
869 // get the rank index from the bank
870 uint8_t rank
= bank
.rank
;
872 assert(actTicks
[rank
].size() == activationLimit
);
874 DPRINTF(DRAM
, "Activate at tick %d\n", act_tick
);
876 // update the open row
877 assert(bank
.openRow
== Bank::NO_ROW
);
880 // start counting anew, this covers both the case when we
881 // auto-precharged, and when this access is forced to
883 bank
.bytesAccessed
= 0;
884 bank
.rowAccesses
= 0;
887 assert(numBanksActive
<= banksPerRank
* ranksPerChannel
);
889 DPRINTF(DRAM
, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
890 bank
.bank
, bank
.rank
, act_tick
, numBanksActive
);
892 rankPower
[bank
.rank
].powerlib
.doCommand(MemCommand::ACT
, bank
.bank
,
893 divCeil(act_tick
, tCK
) -
896 DPRINTF(DRAMPower
, "%llu,ACT,%d,%d\n", divCeil(act_tick
, tCK
) -
897 timeStampOffset
, bank
.bank
, bank
.rank
);
899 // The next access has to respect tRAS for this bank
900 bank
.preAllowedAt
= act_tick
+ tRAS
;
902 // Respect the row-to-column command delay
903 bank
.colAllowedAt
= std::max(act_tick
+ tRCD
, bank
.colAllowedAt
);
905 // start by enforcing tRRD
906 for(int i
= 0; i
< banksPerRank
; i
++) {
907 // next activate to any bank in this rank must not happen
909 if (bankGroupArch
&& (bank
.bankgr
== banks
[rank
][i
].bankgr
)) {
910 // bank group architecture requires longer delays between
911 // ACT commands within the same bank group. Use tRRD_L
913 banks
[rank
][i
].actAllowedAt
= std::max(act_tick
+ tRRD_L
,
914 banks
[rank
][i
].actAllowedAt
);
916 // use shorter tRRD value when either
917 // 1) bank group architecture is not supportted
918 // 2) bank is in a different bank group
919 banks
[rank
][i
].actAllowedAt
= std::max(act_tick
+ tRRD
,
920 banks
[rank
][i
].actAllowedAt
);
924 // next, we deal with tXAW, if the activation limit is disabled
925 // then we directly schedule an activate power event
926 if (!actTicks
[rank
].empty()) {
928 if (actTicks
[rank
].back() &&
929 (act_tick
- actTicks
[rank
].back()) < tXAW
) {
930 panic("Got %d activates in window %d (%llu - %llu) which "
931 "is smaller than %llu\n", activationLimit
, act_tick
-
932 actTicks
[rank
].back(), act_tick
, actTicks
[rank
].back(),
936 // shift the times used for the book keeping, the last element
937 // (highest index) is the oldest one and hence the lowest value
938 actTicks
[rank
].pop_back();
940 // record an new activation (in the future)
941 actTicks
[rank
].push_front(act_tick
);
943 // cannot activate more than X times in time window tXAW, push the
944 // next one (the X + 1'st activate) to be tXAW away from the
945 // oldest in our window of X
946 if (actTicks
[rank
].back() &&
947 (act_tick
- actTicks
[rank
].back()) < tXAW
) {
948 DPRINTF(DRAM
, "Enforcing tXAW with X = %d, next activate "
949 "no earlier than %llu\n", activationLimit
,
950 actTicks
[rank
].back() + tXAW
);
951 for(int j
= 0; j
< banksPerRank
; j
++)
952 // next activate must not happen before end of window
953 banks
[rank
][j
].actAllowedAt
=
954 std::max(actTicks
[rank
].back() + tXAW
,
955 banks
[rank
][j
].actAllowedAt
);
959 // at the point when this activate takes place, make sure we
960 // transition to the active power state
961 if (!activateEvent
.scheduled())
962 schedule(activateEvent
, act_tick
);
963 else if (activateEvent
.when() > act_tick
)
964 // move it sooner in time
965 reschedule(activateEvent
, act_tick
);
969 DRAMCtrl::processActivateEvent()
971 // we should transition to the active state as soon as any bank is active
972 if (pwrState
!= PWR_ACT
)
973 // note that at this point numBanksActive could be back at
974 // zero again due to a precharge scheduled in the future
975 schedulePowerEvent(PWR_ACT
, curTick());
979 DRAMCtrl::prechargeBank(Bank
& bank
, Tick pre_at
, bool trace
)
981 // make sure the bank has an open row
982 assert(bank
.openRow
!= Bank::NO_ROW
);
984 // sample the bytes per activate here since we are closing
986 bytesPerActivate
.sample(bank
.bytesAccessed
);
988 bank
.openRow
= Bank::NO_ROW
;
990 // no precharge allowed before this one
991 bank
.preAllowedAt
= pre_at
;
993 Tick pre_done_at
= pre_at
+ tRP
;
995 bank
.actAllowedAt
= std::max(bank
.actAllowedAt
, pre_done_at
);
997 assert(numBanksActive
!= 0);
1000 DPRINTF(DRAM
, "Precharging bank %d, rank %d at tick %lld, now got "
1001 "%d active\n", bank
.bank
, bank
.rank
, pre_at
, numBanksActive
);
1005 rankPower
[bank
.rank
].powerlib
.doCommand(MemCommand::PRE
, bank
.bank
,
1006 divCeil(pre_at
, tCK
) -
1008 DPRINTF(DRAMPower
, "%llu,PRE,%d,%d\n", divCeil(pre_at
, tCK
) -
1009 timeStampOffset
, bank
.bank
, bank
.rank
);
1011 // if we look at the current number of active banks we might be
1012 // tempted to think the DRAM is now idle, however this can be
1013 // undone by an activate that is scheduled to happen before we
1014 // would have reached the idle state, so schedule an event and
1015 // rather check once we actually make it to the point in time when
1016 // the (last) precharge takes place
1017 if (!prechargeEvent
.scheduled())
1018 schedule(prechargeEvent
, pre_done_at
);
1019 else if (prechargeEvent
.when() < pre_done_at
)
1020 reschedule(prechargeEvent
, pre_done_at
);
1024 DRAMCtrl::processPrechargeEvent()
1026 // if we reached zero, then special conditions apply as we track
1027 // if all banks are precharged for the power models
1028 if (numBanksActive
== 0) {
1029 // we should transition to the idle state when the last bank
1031 schedulePowerEvent(PWR_IDLE
, curTick());
1036 DRAMCtrl::doDRAMAccess(DRAMPacket
* dram_pkt
)
1038 DPRINTF(DRAM
, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1039 dram_pkt
->addr
, dram_pkt
->rank
, dram_pkt
->bank
, dram_pkt
->row
);
1042 Bank
& bank
= dram_pkt
->bankRef
;
1044 // for the state we need to track if it is a row hit or not
1045 bool row_hit
= true;
1047 // respect any constraints on the command (e.g. tRCD or tCCD)
1048 Tick cmd_at
= std::max(bank
.colAllowedAt
, curTick());
1050 // Determine the access latency and update the bank state
1051 if (bank
.openRow
== dram_pkt
->row
) {
1056 // If there is a page open, precharge it.
1057 if (bank
.openRow
!= Bank::NO_ROW
) {
1058 prechargeBank(bank
, std::max(bank
.preAllowedAt
, curTick()));
1061 // next we need to account for the delay in activating the
1063 Tick act_tick
= std::max(bank
.actAllowedAt
, curTick());
1065 // Record the activation and deal with all the global timing
1066 // constraints caused be a new activation (tRRD and tXAW)
1067 activateBank(bank
, act_tick
, dram_pkt
->row
);
1069 // issue the command as early as possible
1070 cmd_at
= bank
.colAllowedAt
;
1073 // we need to wait until the bus is available before we can issue
1075 cmd_at
= std::max(cmd_at
, busBusyUntil
- tCL
);
1077 // update the packet ready time
1078 dram_pkt
->readyTime
= cmd_at
+ tCL
+ tBURST
;
1080 // only one burst can use the bus at any one point in time
1081 assert(dram_pkt
->readyTime
- busBusyUntil
>= tBURST
);
1083 // update the time for the next read/write burst for each
1084 // bank (add a max with tCCD/tCCD_L here)
1086 for(int j
= 0; j
< ranksPerChannel
; j
++) {
1087 for(int i
= 0; i
< banksPerRank
; i
++) {
1088 // next burst to same bank group in this rank must not happen
1089 // before tCCD_L. Different bank group timing requirement is
1090 // tBURST; Add tCS for different ranks
1091 if (dram_pkt
->rank
== j
) {
1092 if (bankGroupArch
&& (bank
.bankgr
== banks
[j
][i
].bankgr
)) {
1093 // bank group architecture requires longer delays between
1094 // RD/WR burst commands to the same bank group.
1095 // Use tCCD_L in this case
1098 // use tBURST (equivalent to tCCD_S), the shorter
1099 // cas-to-cas delay value, when either:
1100 // 1) bank group architecture is not supportted
1101 // 2) bank is in a different bank group
1105 // different rank is by default in a different bank group
1106 // use tBURST (equivalent to tCCD_S), which is the shorter
1107 // cas-to-cas delay in this case
1108 // Add tCS to account for rank-to-rank bus delay requirements
1109 cmd_dly
= tBURST
+ tCS
;
1111 banks
[j
][i
].colAllowedAt
= std::max(cmd_at
+ cmd_dly
,
1112 banks
[j
][i
].colAllowedAt
);
1116 // Save rank of current access
1117 activeRank
= dram_pkt
->rank
;
1119 // If this is a write, we also need to respect the write recovery
1120 // time before a precharge, in the case of a read, respect the
1121 // read to precharge constraint
1122 bank
.preAllowedAt
= std::max(bank
.preAllowedAt
,
1123 dram_pkt
->isRead
? cmd_at
+ tRTP
:
1124 dram_pkt
->readyTime
+ tWR
);
1126 // increment the bytes accessed and the accesses per row
1127 bank
.bytesAccessed
+= burstSize
;
1130 // if we reached the max, then issue with an auto-precharge
1131 bool auto_precharge
= pageMgmt
== Enums::close
||
1132 bank
.rowAccesses
== maxAccessesPerRow
;
1134 // if we did not hit the limit, we might still want to
1136 if (!auto_precharge
&&
1137 (pageMgmt
== Enums::open_adaptive
||
1138 pageMgmt
== Enums::close_adaptive
)) {
1139 // a twist on the open and close page policies:
1140 // 1) open_adaptive page policy does not blindly keep the
1141 // page open, but close it if there are no row hits, and there
1142 // are bank conflicts in the queue
1143 // 2) close_adaptive page policy does not blindly close the
1144 // page, but closes it only if there are no row hits in the queue.
1145 // In this case, only force an auto precharge when there
1146 // are no same page hits in the queue
1147 bool got_more_hits
= false;
1148 bool got_bank_conflict
= false;
1150 // either look at the read queue or write queue
1151 const deque
<DRAMPacket
*>& queue
= dram_pkt
->isRead
? readQueue
:
1153 auto p
= queue
.begin();
1154 // make sure we are not considering the packet that we are
1155 // currently dealing with (which is the head of the queue)
1158 // keep on looking until we have found required condition or
1160 while (!(got_more_hits
&&
1161 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
)) &&
1163 bool same_rank_bank
= (dram_pkt
->rank
== (*p
)->rank
) &&
1164 (dram_pkt
->bank
== (*p
)->bank
);
1165 bool same_row
= dram_pkt
->row
== (*p
)->row
;
1166 got_more_hits
|= same_rank_bank
&& same_row
;
1167 got_bank_conflict
|= same_rank_bank
&& !same_row
;
1171 // auto pre-charge when either
1172 // 1) open_adaptive policy, we have not got any more hits, and
1173 // have a bank conflict
1174 // 2) close_adaptive policy and we have not got any more hits
1175 auto_precharge
= !got_more_hits
&&
1176 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
);
1179 // DRAMPower trace command to be written
1180 std::string mem_cmd
= dram_pkt
->isRead
? "RD" : "WR";
1182 // MemCommand required for DRAMPower library
1183 MemCommand::cmds command
= (mem_cmd
== "RD") ? MemCommand::RD
:
1186 // if this access should use auto-precharge, then we are
1188 if (auto_precharge
) {
1189 // if auto-precharge push a PRE command at the correct tick to the
1190 // list used by DRAMPower library to calculate power
1191 prechargeBank(bank
, std::max(curTick(), bank
.preAllowedAt
));
1193 DPRINTF(DRAM
, "Auto-precharged bank: %d\n", dram_pkt
->bankId
);
1197 busBusyUntil
= dram_pkt
->readyTime
;
1199 DPRINTF(DRAM
, "Access to %lld, ready at %lld bus busy until %lld.\n",
1200 dram_pkt
->addr
, dram_pkt
->readyTime
, busBusyUntil
);
1202 rankPower
[dram_pkt
->rank
].powerlib
.doCommand(command
, dram_pkt
->bank
,
1203 divCeil(cmd_at
, tCK
) -
1206 DPRINTF(DRAMPower
, "%llu,%s,%d,%d\n", divCeil(cmd_at
, tCK
) -
1207 timeStampOffset
, mem_cmd
, dram_pkt
->bank
, dram_pkt
->rank
);
1209 // Update the minimum timing between the requests, this is a
1210 // conservative estimate of when we have to schedule the next
1211 // request to not introduce any unecessary bubbles. In most cases
1212 // we will wake up sooner than we have to.
1213 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1215 // Update the stats and schedule the next request
1216 if (dram_pkt
->isRead
) {
1220 bytesReadDRAM
+= burstSize
;
1221 perBankRdBursts
[dram_pkt
->bankId
]++;
1223 // Update latency stats
1224 totMemAccLat
+= dram_pkt
->readyTime
- dram_pkt
->entryTime
;
1225 totBusLat
+= tBURST
;
1226 totQLat
+= cmd_at
- dram_pkt
->entryTime
;
1231 bytesWritten
+= burstSize
;
1232 perBankWrBursts
[dram_pkt
->bankId
]++;
1237 DRAMCtrl::processNextReqEvent()
1239 // pre-emptively set to false. Overwrite if in READ_TO_WRITE
1240 // or WRITE_TO_READ state
1241 bool switched_cmd_type
= false;
1242 if (busState
== READ_TO_WRITE
) {
1243 DPRINTF(DRAM
, "Switching to writes after %d reads with %d reads "
1244 "waiting\n", readsThisTime
, readQueue
.size());
1246 // sample and reset the read-related stats as we are now
1247 // transitioning to writes, and all reads are done
1248 rdPerTurnAround
.sample(readsThisTime
);
1251 // now proceed to do the actual writes
1253 switched_cmd_type
= true;
1254 } else if (busState
== WRITE_TO_READ
) {
1255 DPRINTF(DRAM
, "Switching to reads after %d writes with %d writes "
1256 "waiting\n", writesThisTime
, writeQueue
.size());
1258 wrPerTurnAround
.sample(writesThisTime
);
1262 switched_cmd_type
= true;
1265 if (refreshState
!= REF_IDLE
) {
1266 // if a refresh waiting for this event loop to finish, then hand
1267 // over now, and do not schedule a new nextReqEvent
1268 if (refreshState
== REF_DRAIN
) {
1269 DPRINTF(DRAM
, "Refresh drain done, now precharging\n");
1271 refreshState
= REF_PRE
;
1273 // hand control back to the refresh event loop
1274 schedule(refreshEvent
, curTick());
1277 // let the refresh finish before issuing any further requests
1281 // when we get here it is either a read or a write
1282 if (busState
== READ
) {
1284 // track if we should switch or not
1285 bool switch_to_writes
= false;
1287 if (readQueue
.empty()) {
1288 // In the case there is no read request to go next,
1289 // trigger writes if we have passed the low threshold (or
1290 // if we are draining)
1291 if (!writeQueue
.empty() &&
1292 (drainManager
|| writeQueue
.size() > writeLowThreshold
)) {
1294 switch_to_writes
= true;
1296 // check if we are drained
1297 if (respQueue
.empty () && drainManager
) {
1298 DPRINTF(Drain
, "DRAM controller done draining\n");
1299 drainManager
->signalDrainDone();
1300 drainManager
= NULL
;
1303 // nothing to do, not even any point in scheduling an
1304 // event for the next request
1308 // Figure out which read request goes next, and move it to the
1309 // front of the read queue
1310 chooseNext(readQueue
, switched_cmd_type
);
1312 DRAMPacket
* dram_pkt
= readQueue
.front();
1314 // here we get a bit creative and shift the bus busy time not
1315 // just the tWTR, but also a CAS latency to capture the fact
1316 // that we are allowed to prepare a new bank, but not issue a
1317 // read command until after tWTR, in essence we capture a
1318 // bubble on the data bus that is tWTR + tCL
1319 if (switched_cmd_type
&& dram_pkt
->rank
== activeRank
) {
1320 busBusyUntil
+= tWTR
+ tCL
;
1323 doDRAMAccess(dram_pkt
);
1325 // At this point we're done dealing with the request
1326 readQueue
.pop_front();
1329 assert(dram_pkt
->size
<= burstSize
);
1330 assert(dram_pkt
->readyTime
>= curTick());
1332 // Insert into response queue. It will be sent back to the
1333 // requestor at its readyTime
1334 if (respQueue
.empty()) {
1335 assert(!respondEvent
.scheduled());
1336 schedule(respondEvent
, dram_pkt
->readyTime
);
1338 assert(respQueue
.back()->readyTime
<= dram_pkt
->readyTime
);
1339 assert(respondEvent
.scheduled());
1342 respQueue
.push_back(dram_pkt
);
1344 // we have so many writes that we have to transition
1345 if (writeQueue
.size() > writeHighThreshold
) {
1346 switch_to_writes
= true;
1350 // switching to writes, either because the read queue is empty
1351 // and the writes have passed the low threshold (or we are
1352 // draining), or because the writes hit the hight threshold
1353 if (switch_to_writes
) {
1354 // transition to writing
1355 busState
= READ_TO_WRITE
;
1358 chooseNext(writeQueue
, switched_cmd_type
);
1359 DRAMPacket
* dram_pkt
= writeQueue
.front();
1361 assert(dram_pkt
->size
<= burstSize
);
1363 // add a bubble to the data bus, as defined by the
1364 // tRTW when access is to the same rank as previous burst
1365 // Different rank timing is handled with tCS, which is
1366 // applied to colAllowedAt
1367 if (switched_cmd_type
&& dram_pkt
->rank
== activeRank
) {
1368 busBusyUntil
+= tRTW
;
1371 doDRAMAccess(dram_pkt
);
1373 writeQueue
.pop_front();
1376 // If we emptied the write queue, or got sufficiently below the
1377 // threshold (using the minWritesPerSwitch as the hysteresis) and
1378 // are not draining, or we have reads waiting and have done enough
1379 // writes, then switch to reads.
1380 if (writeQueue
.empty() ||
1381 (writeQueue
.size() + minWritesPerSwitch
< writeLowThreshold
&&
1383 (!readQueue
.empty() && writesThisTime
>= minWritesPerSwitch
)) {
1384 // turn the bus back around for reads again
1385 busState
= WRITE_TO_READ
;
1387 // note that the we switch back to reads also in the idle
1388 // case, which eventually will check for any draining and
1389 // also pause any further scheduling if there is really
1394 schedule(nextReqEvent
, std::max(nextReqTime
, curTick()));
1396 // If there is space available and we have writes waiting then let
1397 // them retry. This is done here to ensure that the retry does not
1398 // cause a nextReqEvent to be scheduled before we do so as part of
1399 // the next request processing
1400 if (retryWrReq
&& writeQueue
.size() < writeBufferSize
) {
1407 DRAMCtrl::minBankPrep(const deque
<DRAMPacket
*>& queue
,
1408 bool switched_cmd_type
) const
1410 uint64_t bank_mask
= 0;
1411 Tick min_act_at
= MaxTick
;
1413 uint64_t bank_mask_same_rank
= 0;
1414 Tick min_act_at_same_rank
= MaxTick
;
1416 // Give precedence to commands that access same rank as previous command
1417 bool same_rank_match
= false;
1419 // determine if we have queued transactions targetting the
1421 vector
<bool> got_waiting(ranksPerChannel
* banksPerRank
, false);
1422 for (auto p
= queue
.begin(); p
!= queue
.end(); ++p
) {
1423 got_waiting
[(*p
)->bankId
] = true;
1426 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1427 for (int j
= 0; j
< banksPerRank
; j
++) {
1428 uint8_t bank_id
= i
* banksPerRank
+ j
;
1430 // if we have waiting requests for the bank, and it is
1431 // amongst the first available, update the mask
1432 if (got_waiting
[bank_id
]) {
1433 // simplistic approximation of when the bank can issue
1434 // an activate, ignoring any rank-to-rank switching
1435 // cost in this calculation
1436 Tick act_at
= banks
[i
][j
].openRow
== Bank::NO_ROW
?
1437 banks
[i
][j
].actAllowedAt
:
1438 std::max(banks
[i
][j
].preAllowedAt
, curTick()) + tRP
;
1440 // prioritize commands that access the
1441 // same rank as previous burst
1442 // Calculate bank mask separately for the case and
1443 // evaluate after loop iterations complete
1444 if (i
== activeRank
&& ranksPerChannel
> 1) {
1445 if (act_at
<= min_act_at_same_rank
) {
1446 // reset same rank bank mask if new minimum is found
1447 // and previous minimum could not immediately send ACT
1448 if (act_at
< min_act_at_same_rank
&&
1449 min_act_at_same_rank
> curTick())
1450 bank_mask_same_rank
= 0;
1452 // Set flag indicating that a same rank
1453 // opportunity was found
1454 same_rank_match
= true;
1456 // set the bit corresponding to the available bank
1457 replaceBits(bank_mask_same_rank
, bank_id
, bank_id
, 1);
1458 min_act_at_same_rank
= act_at
;
1461 if (act_at
<= min_act_at
) {
1462 // reset bank mask if new minimum is found
1463 // and either previous minimum could not immediately send ACT
1464 if (act_at
< min_act_at
&& min_act_at
> curTick())
1466 // set the bit corresponding to the available bank
1467 replaceBits(bank_mask
, bank_id
, bank_id
, 1);
1468 min_act_at
= act_at
;
1475 // Determine the earliest time when the next burst can issue based
1476 // on the current busBusyUntil delay.
1477 // Offset by tRCD to correlate with ACT timing variables
1478 Tick min_cmd_at
= busBusyUntil
- tCL
- tRCD
;
1480 // Prioritize same rank accesses that can issue B2B
1481 // Only optimize for same ranks when the command type
1482 // does not change; do not want to unnecessarily incur tWTR
1484 // Resulting FCFS prioritization Order is:
1485 // 1) Commands that access the same rank as previous burst
1486 // and can prep the bank seamlessly.
1487 // 2) Commands (any rank) with earliest bank prep
1488 if (!switched_cmd_type
&& same_rank_match
&&
1489 min_act_at_same_rank
<= min_cmd_at
) {
1490 bank_mask
= bank_mask_same_rank
;
1497 DRAMCtrl::processRefreshEvent()
1499 // when first preparing the refresh, remember when it was due
1500 if (refreshState
== REF_IDLE
) {
1501 // remember when the refresh is due
1502 refreshDueAt
= curTick();
1505 refreshState
= REF_DRAIN
;
1507 DPRINTF(DRAM
, "Refresh due\n");
1510 // let any scheduled read or write go ahead, after which it will
1511 // hand control back to this event loop
1512 if (refreshState
== REF_DRAIN
) {
1513 if (nextReqEvent
.scheduled()) {
1514 // hand control over to the request loop until it is
1516 DPRINTF(DRAM
, "Refresh awaiting draining\n");
1520 refreshState
= REF_PRE
;
1524 // at this point, ensure that all banks are precharged
1525 if (refreshState
== REF_PRE
) {
1526 // precharge any active bank if we are not already in the idle
1528 if (pwrState
!= PWR_IDLE
) {
1529 // at the moment, we use a precharge all even if there is
1530 // only a single bank open
1531 DPRINTF(DRAM
, "Precharging all\n");
1533 // first determine when we can precharge
1534 Tick pre_at
= curTick();
1535 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1536 for (int j
= 0; j
< banksPerRank
; j
++) {
1537 // respect both causality and any existing bank
1538 // constraints, some banks could already have a
1539 // (auto) precharge scheduled
1540 pre_at
= std::max(banks
[i
][j
].preAllowedAt
, pre_at
);
1544 // make sure all banks are precharged, and for those that
1545 // already are, update their availability
1546 Tick act_allowed_at
= pre_at
+ tRP
;
1548 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1549 for (int j
= 0; j
< banksPerRank
; j
++) {
1550 if (banks
[i
][j
].openRow
!= Bank::NO_ROW
) {
1551 prechargeBank(banks
[i
][j
], pre_at
, false);
1553 banks
[i
][j
].actAllowedAt
=
1554 std::max(banks
[i
][j
].actAllowedAt
, act_allowed_at
);
1555 banks
[i
][j
].preAllowedAt
=
1556 std::max(banks
[i
][j
].preAllowedAt
, pre_at
);
1560 // at the moment this affects all ranks
1561 rankPower
[i
].powerlib
.doCommand(MemCommand::PREA
, 0,
1562 divCeil(pre_at
, tCK
) -
1565 DPRINTF(DRAMPower
, "%llu,PREA,0,%d\n", divCeil(pre_at
, tCK
) -
1566 timeStampOffset
, i
);
1569 DPRINTF(DRAM
, "All banks already precharged, starting refresh\n");
1571 // go ahead and kick the power state machine into gear if
1572 // we are already idle
1573 schedulePowerEvent(PWR_REF
, curTick());
1576 refreshState
= REF_RUN
;
1577 assert(numBanksActive
== 0);
1579 // wait for all banks to be precharged, at which point the
1580 // power state machine will transition to the idle state, and
1581 // automatically move to a refresh, at that point it will also
1582 // call this method to get the refresh event loop going again
1586 // last but not least we perform the actual refresh
1587 if (refreshState
== REF_RUN
) {
1588 // should never get here with any banks active
1589 assert(numBanksActive
== 0);
1590 assert(pwrState
== PWR_REF
);
1592 Tick ref_done_at
= curTick() + tRFC
;
1594 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1595 for (int j
= 0; j
< banksPerRank
; j
++) {
1596 banks
[i
][j
].actAllowedAt
= ref_done_at
;
1599 // at the moment this affects all ranks
1600 rankPower
[i
].powerlib
.doCommand(MemCommand::REF
, 0,
1601 divCeil(curTick(), tCK
) -
1604 // at the moment sort the list of commands and update the counters
1605 // for DRAMPower libray when doing a refresh
1606 sort(rankPower
[i
].powerlib
.cmdList
.begin(),
1607 rankPower
[i
].powerlib
.cmdList
.end(), DRAMCtrl::sortTime
);
1609 // update the counters for DRAMPower, passing false to
1610 // indicate that this is not the last command in the
1611 // list. DRAMPower requires this information for the
1612 // correct calculation of the background energy at the end
1613 // of the simulation. Ideally we would want to call this
1614 // function with true once at the end of the
1615 // simulation. However, the discarded energy is extremly
1616 // small and does not effect the final results.
1617 rankPower
[i
].powerlib
.updateCounters(false);
1619 // call the energy function
1620 rankPower
[i
].powerlib
.calcEnergy();
1623 updatePowerStats(i
);
1625 DPRINTF(DRAMPower
, "%llu,REF,0,%d\n", divCeil(curTick(), tCK
) -
1626 timeStampOffset
, i
);
1629 // make sure we did not wait so long that we cannot make up
1631 if (refreshDueAt
+ tREFI
< ref_done_at
) {
1632 fatal("Refresh was delayed so long we cannot catch up\n");
1635 // compensate for the delay in actually performing the refresh
1636 // when scheduling the next one
1637 schedule(refreshEvent
, refreshDueAt
+ tREFI
- tRP
);
1639 assert(!powerEvent
.scheduled());
1641 // move to the idle power state once the refresh is done, this
1642 // will also move the refresh state machine to the refresh
1644 schedulePowerEvent(PWR_IDLE
, ref_done_at
);
1646 DPRINTF(DRAMState
, "Refresh done at %llu and next refresh at %llu\n",
1647 ref_done_at
, refreshDueAt
+ tREFI
);
1652 DRAMCtrl::schedulePowerEvent(PowerState pwr_state
, Tick tick
)
1654 // respect causality
1655 assert(tick
>= curTick());
1657 if (!powerEvent
.scheduled()) {
1658 DPRINTF(DRAMState
, "Scheduling power event at %llu to state %d\n",
1661 // insert the new transition
1662 pwrStateTrans
= pwr_state
;
1664 schedule(powerEvent
, tick
);
1666 panic("Scheduled power event at %llu to state %d, "
1667 "with scheduled event at %llu to %d\n", tick
, pwr_state
,
1668 powerEvent
.when(), pwrStateTrans
);
1673 DRAMCtrl::processPowerEvent()
1675 // remember where we were, and for how long
1676 Tick duration
= curTick() - pwrStateTick
;
1677 PowerState prev_state
= pwrState
;
1679 // update the accounting
1680 pwrStateTime
[prev_state
] += duration
;
1682 pwrState
= pwrStateTrans
;
1683 pwrStateTick
= curTick();
1685 if (pwrState
== PWR_IDLE
) {
1686 DPRINTF(DRAMState
, "All banks precharged\n");
1688 // if we were refreshing, make sure we start scheduling requests again
1689 if (prev_state
== PWR_REF
) {
1690 DPRINTF(DRAMState
, "Was refreshing for %llu ticks\n", duration
);
1691 assert(pwrState
== PWR_IDLE
);
1693 // kick things into action again
1694 refreshState
= REF_IDLE
;
1695 assert(!nextReqEvent
.scheduled());
1696 schedule(nextReqEvent
, curTick());
1698 assert(prev_state
== PWR_ACT
);
1700 // if we have a pending refresh, and are now moving to
1701 // the idle state, direclty transition to a refresh
1702 if (refreshState
== REF_RUN
) {
1703 // there should be nothing waiting at this point
1704 assert(!powerEvent
.scheduled());
1706 // update the state in zero time and proceed below
1712 // we transition to the refresh state, let the refresh state
1713 // machine know of this state update and let it deal with the
1714 // scheduling of the next power state transition as well as the
1715 // following refresh
1716 if (pwrState
== PWR_REF
) {
1717 DPRINTF(DRAMState
, "Refreshing\n");
1718 // kick the refresh event loop into action again, and that
1719 // in turn will schedule a transition to the idle power
1720 // state once the refresh is done
1721 assert(refreshState
== REF_RUN
);
1722 processRefreshEvent();
1727 DRAMCtrl::updatePowerStats(uint8_t rank
)
1729 // Get the energy and power from DRAMPower
1730 Data::MemoryPowerModel::Energy energy
=
1731 rankPower
[rank
].powerlib
.getEnergy();
1732 Data::MemoryPowerModel::Power power
=
1733 rankPower
[rank
].powerlib
.getPower();
1735 actEnergy
[rank
] = energy
.act_energy
* devicesPerRank
;
1736 preEnergy
[rank
] = energy
.pre_energy
* devicesPerRank
;
1737 readEnergy
[rank
] = energy
.read_energy
* devicesPerRank
;
1738 writeEnergy
[rank
] = energy
.write_energy
* devicesPerRank
;
1739 refreshEnergy
[rank
] = energy
.ref_energy
* devicesPerRank
;
1740 actBackEnergy
[rank
] = energy
.act_stdby_energy
* devicesPerRank
;
1741 preBackEnergy
[rank
] = energy
.pre_stdby_energy
* devicesPerRank
;
1742 totalEnergy
[rank
] = energy
.total_energy
* devicesPerRank
;
1743 averagePower
[rank
] = power
.average_power
* devicesPerRank
;
1747 DRAMCtrl::regStats()
1749 using namespace Stats
;
1751 AbstractMemory::regStats();
1754 .name(name() + ".readReqs")
1755 .desc("Number of read requests accepted");
1758 .name(name() + ".writeReqs")
1759 .desc("Number of write requests accepted");
1762 .name(name() + ".readBursts")
1763 .desc("Number of DRAM read bursts, "
1764 "including those serviced by the write queue");
1767 .name(name() + ".writeBursts")
1768 .desc("Number of DRAM write bursts, "
1769 "including those merged in the write queue");
1772 .name(name() + ".servicedByWrQ")
1773 .desc("Number of DRAM read bursts serviced by the write queue");
1776 .name(name() + ".mergedWrBursts")
1777 .desc("Number of DRAM write bursts merged with an existing one");
1780 .name(name() + ".neitherReadNorWriteReqs")
1781 .desc("Number of requests that are neither read nor write");
1784 .init(banksPerRank
* ranksPerChannel
)
1785 .name(name() + ".perBankRdBursts")
1786 .desc("Per bank write bursts");
1789 .init(banksPerRank
* ranksPerChannel
)
1790 .name(name() + ".perBankWrBursts")
1791 .desc("Per bank write bursts");
1794 .name(name() + ".avgRdQLen")
1795 .desc("Average read queue length when enqueuing")
1799 .name(name() + ".avgWrQLen")
1800 .desc("Average write queue length when enqueuing")
1804 .name(name() + ".totQLat")
1805 .desc("Total ticks spent queuing");
1808 .name(name() + ".totBusLat")
1809 .desc("Total ticks spent in databus transfers");
1812 .name(name() + ".totMemAccLat")
1813 .desc("Total ticks spent from burst creation until serviced "
1817 .name(name() + ".avgQLat")
1818 .desc("Average queueing delay per DRAM burst")
1821 avgQLat
= totQLat
/ (readBursts
- servicedByWrQ
);
1824 .name(name() + ".avgBusLat")
1825 .desc("Average bus latency per DRAM burst")
1828 avgBusLat
= totBusLat
/ (readBursts
- servicedByWrQ
);
1831 .name(name() + ".avgMemAccLat")
1832 .desc("Average memory access latency per DRAM burst")
1835 avgMemAccLat
= totMemAccLat
/ (readBursts
- servicedByWrQ
);
1838 .name(name() + ".numRdRetry")
1839 .desc("Number of times read queue was full causing retry");
1842 .name(name() + ".numWrRetry")
1843 .desc("Number of times write queue was full causing retry");
1846 .name(name() + ".readRowHits")
1847 .desc("Number of row buffer hits during reads");
1850 .name(name() + ".writeRowHits")
1851 .desc("Number of row buffer hits during writes");
1854 .name(name() + ".readRowHitRate")
1855 .desc("Row buffer hit rate for reads")
1858 readRowHitRate
= (readRowHits
/ (readBursts
- servicedByWrQ
)) * 100;
1861 .name(name() + ".writeRowHitRate")
1862 .desc("Row buffer hit rate for writes")
1865 writeRowHitRate
= (writeRowHits
/ (writeBursts
- mergedWrBursts
)) * 100;
1868 .init(ceilLog2(burstSize
) + 1)
1869 .name(name() + ".readPktSize")
1870 .desc("Read request sizes (log2)");
1873 .init(ceilLog2(burstSize
) + 1)
1874 .name(name() + ".writePktSize")
1875 .desc("Write request sizes (log2)");
1878 .init(readBufferSize
)
1879 .name(name() + ".rdQLenPdf")
1880 .desc("What read queue length does an incoming req see");
1883 .init(writeBufferSize
)
1884 .name(name() + ".wrQLenPdf")
1885 .desc("What write queue length does an incoming req see");
1888 .init(maxAccessesPerRow
)
1889 .name(name() + ".bytesPerActivate")
1890 .desc("Bytes accessed per row activation")
1894 .init(readBufferSize
)
1895 .name(name() + ".rdPerTurnAround")
1896 .desc("Reads before turning the bus around for writes")
1900 .init(writeBufferSize
)
1901 .name(name() + ".wrPerTurnAround")
1902 .desc("Writes before turning the bus around for reads")
1906 .name(name() + ".bytesReadDRAM")
1907 .desc("Total number of bytes read from DRAM");
1910 .name(name() + ".bytesReadWrQ")
1911 .desc("Total number of bytes read from write queue");
1914 .name(name() + ".bytesWritten")
1915 .desc("Total number of bytes written to DRAM");
1918 .name(name() + ".bytesReadSys")
1919 .desc("Total read bytes from the system interface side");
1922 .name(name() + ".bytesWrittenSys")
1923 .desc("Total written bytes from the system interface side");
1926 .name(name() + ".avgRdBW")
1927 .desc("Average DRAM read bandwidth in MiByte/s")
1930 avgRdBW
= (bytesReadDRAM
/ 1000000) / simSeconds
;
1933 .name(name() + ".avgWrBW")
1934 .desc("Average achieved write bandwidth in MiByte/s")
1937 avgWrBW
= (bytesWritten
/ 1000000) / simSeconds
;
1940 .name(name() + ".avgRdBWSys")
1941 .desc("Average system read bandwidth in MiByte/s")
1944 avgRdBWSys
= (bytesReadSys
/ 1000000) / simSeconds
;
1947 .name(name() + ".avgWrBWSys")
1948 .desc("Average system write bandwidth in MiByte/s")
1951 avgWrBWSys
= (bytesWrittenSys
/ 1000000) / simSeconds
;
1954 .name(name() + ".peakBW")
1955 .desc("Theoretical peak bandwidth in MiByte/s")
1958 peakBW
= (SimClock::Frequency
/ tBURST
) * burstSize
/ 1000000;
1961 .name(name() + ".busUtil")
1962 .desc("Data bus utilization in percentage")
1965 busUtil
= (avgRdBW
+ avgWrBW
) / peakBW
* 100;
1968 .name(name() + ".totGap")
1969 .desc("Total gap between requests");
1972 .name(name() + ".avgGap")
1973 .desc("Average gap between requests")
1976 avgGap
= totGap
/ (readReqs
+ writeReqs
);
1978 // Stats for DRAM Power calculation based on Micron datasheet
1980 .name(name() + ".busUtilRead")
1981 .desc("Data bus utilization in percentage for reads")
1984 busUtilRead
= avgRdBW
/ peakBW
* 100;
1987 .name(name() + ".busUtilWrite")
1988 .desc("Data bus utilization in percentage for writes")
1991 busUtilWrite
= avgWrBW
/ peakBW
* 100;
1994 .name(name() + ".pageHitRate")
1995 .desc("Row buffer hit rate, read and write combined")
1998 pageHitRate
= (writeRowHits
+ readRowHits
) /
1999 (writeBursts
- mergedWrBursts
+ readBursts
- servicedByWrQ
) * 100;
2003 .name(name() + ".memoryStateTime")
2004 .desc("Time in different power states");
2005 pwrStateTime
.subname(0, "IDLE");
2006 pwrStateTime
.subname(1, "REF");
2007 pwrStateTime
.subname(2, "PRE_PDN");
2008 pwrStateTime
.subname(3, "ACT");
2009 pwrStateTime
.subname(4, "ACT_PDN");
2012 .init(ranksPerChannel
)
2013 .name(name() + ".actEnergy")
2014 .desc("Energy for activate commands per rank (pJ)");
2017 .init(ranksPerChannel
)
2018 .name(name() + ".preEnergy")
2019 .desc("Energy for precharge commands per rank (pJ)");
2022 .init(ranksPerChannel
)
2023 .name(name() + ".readEnergy")
2024 .desc("Energy for read commands per rank (pJ)");
2027 .init(ranksPerChannel
)
2028 .name(name() + ".writeEnergy")
2029 .desc("Energy for write commands per rank (pJ)");
2032 .init(ranksPerChannel
)
2033 .name(name() + ".refreshEnergy")
2034 .desc("Energy for refresh commands per rank (pJ)");
2037 .init(ranksPerChannel
)
2038 .name(name() + ".actBackEnergy")
2039 .desc("Energy for active background per rank (pJ)");
2042 .init(ranksPerChannel
)
2043 .name(name() + ".preBackEnergy")
2044 .desc("Energy for precharge background per rank (pJ)");
2047 .init(ranksPerChannel
)
2048 .name(name() + ".totalEnergy")
2049 .desc("Total energy per rank (pJ)");
2052 .init(ranksPerChannel
)
2053 .name(name() + ".averagePower")
2054 .desc("Core power per rank (mW)");
2058 DRAMCtrl::recvFunctional(PacketPtr pkt
)
2060 // rely on the abstract memory
2061 functionalAccess(pkt
);
2065 DRAMCtrl::getSlavePort(const string
&if_name
, PortID idx
)
2067 if (if_name
!= "port") {
2068 return MemObject::getSlavePort(if_name
, idx
);
2075 DRAMCtrl::drain(DrainManager
*dm
)
2077 unsigned int count
= port
.drain(dm
);
2079 // if there is anything in any of our internal queues, keep track
2081 if (!(writeQueue
.empty() && readQueue
.empty() &&
2082 respQueue
.empty())) {
2083 DPRINTF(Drain
, "DRAM controller not drained, write: %d, read: %d,"
2084 " resp: %d\n", writeQueue
.size(), readQueue
.size(),
2089 // the only part that is not drained automatically over time
2090 // is the write queue, thus kick things into action if needed
2091 if (!writeQueue
.empty() && !nextReqEvent
.scheduled()) {
2092 schedule(nextReqEvent
, curTick());
2097 setDrainState(Drainable::Draining
);
2099 setDrainState(Drainable::Drained
);
2103 DRAMCtrl::MemoryPort::MemoryPort(const std::string
& name
, DRAMCtrl
& _memory
)
2104 : QueuedSlavePort(name
, &_memory
, queue
), queue(_memory
, *this),
2109 DRAMCtrl::MemoryPort::getAddrRanges() const
2111 AddrRangeList ranges
;
2112 ranges
.push_back(memory
.getAddrRange());
2117 DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt
)
2119 pkt
->pushLabel(memory
.name());
2121 if (!queue
.checkFunctional(pkt
)) {
2122 // Default implementation of SimpleTimingPort::recvFunctional()
2123 // calls recvAtomic() and throws away the latency; we can save a
2124 // little here by just not calculating the latency.
2125 memory
.recvFunctional(pkt
);
2132 DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt
)
2134 return memory
.recvAtomic(pkt
);
2138 DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt
)
2140 // pass it to the memory controller
2141 return memory
.recvTimingReq(pkt
);
2145 DRAMCtrlParams::create()
2147 return new DRAMCtrl(this);