2 * Copyright (c) 2010-2016 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
47 #include "base/bitfield.hh"
48 #include "base/trace.hh"
49 #include "debug/DRAM.hh"
50 #include "debug/DRAMPower.hh"
51 #include "debug/DRAMState.hh"
52 #include "debug/Drain.hh"
53 #include "mem/dram_ctrl.hh"
54 #include "sim/system.hh"
59 DRAMCtrl::DRAMCtrl(const DRAMCtrlParams
* p
) :
61 port(name() + ".port", *this), isTimingMode(false),
62 retryRdReq(false), retryWrReq(false),
65 nextReqEvent(this), respondEvent(this),
66 deviceSize(p
->device_size
),
67 deviceBusWidth(p
->device_bus_width
), burstLength(p
->burst_length
),
68 deviceRowBufferSize(p
->device_rowbuffer_size
),
69 devicesPerRank(p
->devices_per_rank
),
70 burstSize((devicesPerRank
* burstLength
* deviceBusWidth
) / 8),
71 rowBufferSize(devicesPerRank
* deviceRowBufferSize
),
72 columnsPerRowBuffer(rowBufferSize
/ burstSize
),
73 columnsPerStripe(range
.interleaved() ? range
.granularity() / burstSize
: 1),
74 ranksPerChannel(p
->ranks_per_channel
),
75 bankGroupsPerRank(p
->bank_groups_per_rank
),
76 bankGroupArch(p
->bank_groups_per_rank
> 0),
77 banksPerRank(p
->banks_per_rank
), channels(p
->channels
), rowsPerBank(0),
78 readBufferSize(p
->read_buffer_size
),
79 writeBufferSize(p
->write_buffer_size
),
80 writeHighThreshold(writeBufferSize
* p
->write_high_thresh_perc
/ 100.0),
81 writeLowThreshold(writeBufferSize
* p
->write_low_thresh_perc
/ 100.0),
82 minWritesPerSwitch(p
->min_writes_per_switch
),
83 writesThisTime(0), readsThisTime(0),
84 tCK(p
->tCK
), tWTR(p
->tWTR
), tRTW(p
->tRTW
), tCS(p
->tCS
), tBURST(p
->tBURST
),
85 tCCD_L(p
->tCCD_L
), tRCD(p
->tRCD
), tCL(p
->tCL
), tRP(p
->tRP
), tRAS(p
->tRAS
),
86 tWR(p
->tWR
), tRTP(p
->tRTP
), tRFC(p
->tRFC
), tREFI(p
->tREFI
), tRRD(p
->tRRD
),
87 tRRD_L(p
->tRRD_L
), tXAW(p
->tXAW
), tXP(p
->tXP
), tXS(p
->tXS
),
88 activationLimit(p
->activation_limit
),
89 memSchedPolicy(p
->mem_sched_policy
), addrMapping(p
->addr_mapping
),
90 pageMgmt(p
->page_policy
),
91 maxAccessesPerRow(p
->max_accesses_per_row
),
92 frontendLatency(p
->static_frontend_latency
),
93 backendLatency(p
->static_backend_latency
),
94 busBusyUntil(0), prevArrival(0),
95 nextReqTime(0), activeRank(0), timeStampOffset(0)
97 // sanity check the ranks since we rely on bit slicing for the
99 fatal_if(!isPowerOf2(ranksPerChannel
), "DRAM rank count of %d is not "
100 "allowed, must be a power of two\n", ranksPerChannel
);
102 fatal_if(!isPowerOf2(burstSize
), "DRAM burst size %d is not allowed, "
103 "must be a power of two\n", burstSize
);
105 for (int i
= 0; i
< ranksPerChannel
; i
++) {
106 Rank
* rank
= new Rank(*this, p
);
107 ranks
.push_back(rank
);
109 rank
->actTicks
.resize(activationLimit
, 0);
110 rank
->banks
.resize(banksPerRank
);
113 for (int b
= 0; b
< banksPerRank
; b
++) {
114 rank
->banks
[b
].bank
= b
;
115 // GDDR addressing of banks to BG is linear.
116 // Here we assume that all DRAM generations address bank groups as
119 // Simply assign lower bits to bank group in order to
120 // rotate across bank groups as banks are incremented
121 // e.g. with 4 banks per bank group and 16 banks total:
122 // banks 0,4,8,12 are in bank group 0
123 // banks 1,5,9,13 are in bank group 1
124 // banks 2,6,10,14 are in bank group 2
125 // banks 3,7,11,15 are in bank group 3
126 rank
->banks
[b
].bankgr
= b
% bankGroupsPerRank
;
128 // No bank groups; simply assign to bank number
129 rank
->banks
[b
].bankgr
= b
;
134 // perform a basic check of the write thresholds
135 if (p
->write_low_thresh_perc
>= p
->write_high_thresh_perc
)
136 fatal("Write buffer low threshold %d must be smaller than the "
137 "high threshold %d\n", p
->write_low_thresh_perc
,
138 p
->write_high_thresh_perc
);
140 // determine the rows per bank by looking at the total capacity
141 uint64_t capacity
= ULL(1) << ceilLog2(AbstractMemory::size());
143 // determine the dram actual capacity from the DRAM config in Mbytes
144 uint64_t deviceCapacity
= deviceSize
/ (1024 * 1024) * devicesPerRank
*
147 // if actual DRAM size does not match memory capacity in system warn!
148 if (deviceCapacity
!= capacity
/ (1024 * 1024))
149 warn("DRAM device capacity (%d Mbytes) does not match the "
150 "address range assigned (%d Mbytes)\n", deviceCapacity
,
151 capacity
/ (1024 * 1024));
153 DPRINTF(DRAM
, "Memory capacity %lld (%lld) bytes\n", capacity
,
154 AbstractMemory::size());
156 DPRINTF(DRAM
, "Row buffer size %d bytes with %d columns per row buffer\n",
157 rowBufferSize
, columnsPerRowBuffer
);
159 rowsPerBank
= capacity
/ (rowBufferSize
* banksPerRank
* ranksPerChannel
);
161 // some basic sanity checks
162 if (tREFI
<= tRP
|| tREFI
<= tRFC
) {
163 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
167 // basic bank group architecture checks ->
169 // must have at least one bank per bank group
170 if (bankGroupsPerRank
> banksPerRank
) {
171 fatal("banks per rank (%d) must be equal to or larger than "
172 "banks groups per rank (%d)\n",
173 banksPerRank
, bankGroupsPerRank
);
175 // must have same number of banks in each bank group
176 if ((banksPerRank
% bankGroupsPerRank
) != 0) {
177 fatal("Banks per rank (%d) must be evenly divisible by bank groups "
178 "per rank (%d) for equal banks per bank group\n",
179 banksPerRank
, bankGroupsPerRank
);
181 // tCCD_L should be greater than minimal, back-to-back burst delay
182 if (tCCD_L
<= tBURST
) {
183 fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
184 "bank groups per rank (%d) is greater than 1\n",
185 tCCD_L
, tBURST
, bankGroupsPerRank
);
187 // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
188 // some datasheets might specify it equal to tRRD
190 fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
191 "bank groups per rank (%d) is greater than 1\n",
192 tRRD_L
, tRRD
, bankGroupsPerRank
);
201 AbstractMemory::init();
203 if (!port
.isConnected()) {
204 fatal("DRAMCtrl %s is unconnected!\n", name());
206 port
.sendRangeChange();
209 // a bit of sanity checks on the interleaving, save it for here to
210 // ensure that the system pointer is initialised
211 if (range
.interleaved()) {
212 if (channels
!= range
.stripes())
213 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
214 name(), range
.stripes(), channels
);
216 if (addrMapping
== Enums::RoRaBaChCo
) {
217 if (rowBufferSize
!= range
.granularity()) {
218 fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
219 "address map\n", name());
221 } else if (addrMapping
== Enums::RoRaBaCoCh
||
222 addrMapping
== Enums::RoCoRaBaCh
) {
223 // for the interleavings with channel bits in the bottom,
224 // if the system uses a channel striping granularity that
225 // is larger than the DRAM burst size, then map the
226 // sequential accesses within a stripe to a number of
227 // columns in the DRAM, effectively placing some of the
228 // lower-order column bits as the least-significant bits
229 // of the address (above the ones denoting the burst size)
230 assert(columnsPerStripe
>= 1);
232 // channel striping has to be done at a granularity that
233 // is equal or larger to a cache line
234 if (system()->cacheLineSize() > range
.granularity()) {
235 fatal("Channel interleaving of %s must be at least as large "
236 "as the cache line size\n", name());
239 // ...and equal or smaller than the row-buffer size
240 if (rowBufferSize
< range
.granularity()) {
241 fatal("Channel interleaving of %s must be at most as large "
242 "as the row-buffer size\n", name());
244 // this is essentially the check above, so just to be sure
245 assert(columnsPerStripe
<= columnsPerRowBuffer
);
253 // remember the memory system mode of operation
254 isTimingMode
= system()->isTimingMode();
257 // timestamp offset should be in clock cycles for DRAMPower
258 timeStampOffset
= divCeil(curTick(), tCK
);
260 // update the start tick for the precharge accounting to the
262 for (auto r
: ranks
) {
263 r
->startup(curTick() + tREFI
- tRP
);
266 // shift the bus busy time sufficiently far ahead that we never
267 // have to worry about negative values when computing the time for
268 // the next request, this will add an insignificant bubble at the
269 // start of simulation
270 busBusyUntil
= curTick() + tRP
+ tRCD
+ tCL
;
275 DRAMCtrl::recvAtomic(PacketPtr pkt
)
277 DPRINTF(DRAM
, "recvAtomic: %s 0x%x\n", pkt
->cmdString(), pkt
->getAddr());
279 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
282 // do the actual memory access and turn the packet into a response
286 if (pkt
->hasData()) {
287 // this value is not supposed to be accurate, just enough to
288 // keep things going, mimic a closed page
289 latency
= tRP
+ tRCD
+ tCL
;
295 DRAMCtrl::readQueueFull(unsigned int neededEntries
) const
297 DPRINTF(DRAM
, "Read queue limit %d, current size %d, entries needed %d\n",
298 readBufferSize
, readQueue
.size() + respQueue
.size(),
302 (readQueue
.size() + respQueue
.size() + neededEntries
) > readBufferSize
;
306 DRAMCtrl::writeQueueFull(unsigned int neededEntries
) const
308 DPRINTF(DRAM
, "Write queue limit %d, current size %d, entries needed %d\n",
309 writeBufferSize
, writeQueue
.size(), neededEntries
);
310 return (writeQueue
.size() + neededEntries
) > writeBufferSize
;
313 DRAMCtrl::DRAMPacket
*
314 DRAMCtrl::decodeAddr(PacketPtr pkt
, Addr dramPktAddr
, unsigned size
,
317 // decode the address based on the address mapping scheme, with
318 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
319 // channel, respectively
322 // use a 64-bit unsigned during the computations as the row is
323 // always the top bits, and check before creating the DRAMPacket
326 // truncate the address to a DRAM burst, which makes it unique to
327 // a specific column, row, bank, rank and channel
328 Addr addr
= dramPktAddr
/ burstSize
;
330 // we have removed the lowest order address bits that denote the
331 // position within the column
332 if (addrMapping
== Enums::RoRaBaChCo
) {
333 // the lowest order bits denote the column to ensure that
334 // sequential cache lines occupy the same row
335 addr
= addr
/ columnsPerRowBuffer
;
337 // take out the channel part of the address
338 addr
= addr
/ channels
;
340 // after the channel bits, get the bank bits to interleave
342 bank
= addr
% banksPerRank
;
343 addr
= addr
/ banksPerRank
;
345 // after the bank, we get the rank bits which thus interleaves
347 rank
= addr
% ranksPerChannel
;
348 addr
= addr
/ ranksPerChannel
;
350 // lastly, get the row bits, no need to remove them from addr
351 row
= addr
% rowsPerBank
;
352 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
353 // take out the lower-order column bits
354 addr
= addr
/ columnsPerStripe
;
356 // take out the channel part of the address
357 addr
= addr
/ channels
;
359 // next, the higher-order column bites
360 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
362 // after the column bits, we get the bank bits to interleave
364 bank
= addr
% banksPerRank
;
365 addr
= addr
/ banksPerRank
;
367 // after the bank, we get the rank bits which thus interleaves
369 rank
= addr
% ranksPerChannel
;
370 addr
= addr
/ ranksPerChannel
;
372 // lastly, get the row bits, no need to remove them from addr
373 row
= addr
% rowsPerBank
;
374 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
375 // optimise for closed page mode and utilise maximum
376 // parallelism of the DRAM (at the cost of power)
378 // take out the lower-order column bits
379 addr
= addr
/ columnsPerStripe
;
381 // take out the channel part of the address, not that this has
382 // to match with how accesses are interleaved between the
383 // controllers in the address mapping
384 addr
= addr
/ channels
;
386 // start with the bank bits, as this provides the maximum
387 // opportunity for parallelism between requests
388 bank
= addr
% banksPerRank
;
389 addr
= addr
/ banksPerRank
;
391 // next get the rank bits
392 rank
= addr
% ranksPerChannel
;
393 addr
= addr
/ ranksPerChannel
;
395 // next, the higher-order column bites
396 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
398 // lastly, get the row bits, no need to remove them from addr
399 row
= addr
% rowsPerBank
;
401 panic("Unknown address mapping policy chosen!");
403 assert(rank
< ranksPerChannel
);
404 assert(bank
< banksPerRank
);
405 assert(row
< rowsPerBank
);
406 assert(row
< Bank::NO_ROW
);
408 DPRINTF(DRAM
, "Address: %lld Rank %d Bank %d Row %d\n",
409 dramPktAddr
, rank
, bank
, row
);
411 // create the corresponding DRAM packet with the entry time and
412 // ready time set to the current tick, the latter will be updated
414 uint16_t bank_id
= banksPerRank
* rank
+ bank
;
415 return new DRAMPacket(pkt
, isRead
, rank
, bank
, row
, bank_id
, dramPktAddr
,
416 size
, ranks
[rank
]->banks
[bank
], *ranks
[rank
]);
420 DRAMCtrl::addToReadQueue(PacketPtr pkt
, unsigned int pktCount
)
422 // only add to the read queue here. whenever the request is
423 // eventually done, set the readyTime, and call schedule()
424 assert(!pkt
->isWrite());
426 assert(pktCount
!= 0);
428 // if the request size is larger than burst size, the pkt is split into
429 // multiple DRAM packets
430 // Note if the pkt starting address is not aligened to burst size, the
431 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
432 // are aligned to burst size boundaries. This is to ensure we accurately
433 // check read packets against packets in write queue.
434 Addr addr
= pkt
->getAddr();
435 unsigned pktsServicedByWrQ
= 0;
436 BurstHelper
* burst_helper
= NULL
;
437 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
438 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
439 pkt
->getAddr() + pkt
->getSize()) - addr
;
440 readPktSize
[ceilLog2(size
)]++;
443 // First check write buffer to see if the data is already at
445 bool foundInWrQ
= false;
446 Addr burst_addr
= burstAlign(addr
);
447 // if the burst address is not present then there is no need
448 // looking any further
449 if (isInWriteQueue
.find(burst_addr
) != isInWriteQueue
.end()) {
450 for (const auto& p
: writeQueue
) {
451 // check if the read is subsumed in the write queue
452 // packet we are looking at
453 if (p
->addr
<= addr
&& (addr
+ size
) <= (p
->addr
+ p
->size
)) {
457 DPRINTF(DRAM
, "Read to addr %lld with size %d serviced by "
458 "write queue\n", addr
, size
);
459 bytesReadWrQ
+= burstSize
;
465 // If not found in the write q, make a DRAM packet and
466 // push it onto the read queue
469 // Make the burst helper for split packets
470 if (pktCount
> 1 && burst_helper
== NULL
) {
471 DPRINTF(DRAM
, "Read to addr %lld translates to %d "
472 "dram requests\n", pkt
->getAddr(), pktCount
);
473 burst_helper
= new BurstHelper(pktCount
);
476 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, true);
477 dram_pkt
->burstHelper
= burst_helper
;
479 assert(!readQueueFull(1));
480 rdQLenPdf
[readQueue
.size() + respQueue
.size()]++;
482 DPRINTF(DRAM
, "Adding to read queue\n");
484 readQueue
.push_back(dram_pkt
);
486 // increment read entries of the rank
487 ++dram_pkt
->rankRef
.readEntries
;
490 avgRdQLen
= readQueue
.size() + respQueue
.size();
493 // Starting address of next dram pkt (aligend to burstSize boundary)
494 addr
= (addr
| (burstSize
- 1)) + 1;
497 // If all packets are serviced by write queue, we send the repsonse back
498 if (pktsServicedByWrQ
== pktCount
) {
499 accessAndRespond(pkt
, frontendLatency
);
503 // Update how many split packets are serviced by write queue
504 if (burst_helper
!= NULL
)
505 burst_helper
->burstsServiced
= pktsServicedByWrQ
;
507 // If we are not already scheduled to get a request out of the
509 if (!nextReqEvent
.scheduled()) {
510 DPRINTF(DRAM
, "Request scheduled immediately\n");
511 schedule(nextReqEvent
, curTick());
516 DRAMCtrl::addToWriteQueue(PacketPtr pkt
, unsigned int pktCount
)
518 // only add to the write queue here. whenever the request is
519 // eventually done, set the readyTime, and call schedule()
520 assert(pkt
->isWrite());
522 // if the request size is larger than burst size, the pkt is split into
523 // multiple DRAM packets
524 Addr addr
= pkt
->getAddr();
525 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
526 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
527 pkt
->getAddr() + pkt
->getSize()) - addr
;
528 writePktSize
[ceilLog2(size
)]++;
531 // see if we can merge with an existing item in the write
532 // queue and keep track of whether we have merged or not
533 bool merged
= isInWriteQueue
.find(burstAlign(addr
)) !=
534 isInWriteQueue
.end();
536 // if the item was not merged we need to create a new write
539 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, false);
541 assert(writeQueue
.size() < writeBufferSize
);
542 wrQLenPdf
[writeQueue
.size()]++;
544 DPRINTF(DRAM
, "Adding to write queue\n");
546 writeQueue
.push_back(dram_pkt
);
547 isInWriteQueue
.insert(burstAlign(addr
));
548 assert(writeQueue
.size() == isInWriteQueue
.size());
551 avgWrQLen
= writeQueue
.size();
553 // increment write entries of the rank
554 ++dram_pkt
->rankRef
.writeEntries
;
556 DPRINTF(DRAM
, "Merging write burst with existing queue entry\n");
558 // keep track of the fact that this burst effectively
559 // disappeared as it was merged with an existing one
563 // Starting address of next dram pkt (aligend to burstSize boundary)
564 addr
= (addr
| (burstSize
- 1)) + 1;
567 // we do not wait for the writes to be send to the actual memory,
568 // but instead take responsibility for the consistency here and
569 // snoop the write queue for any upcoming reads
570 // @todo, if a pkt size is larger than burst size, we might need a
571 // different front end latency
572 accessAndRespond(pkt
, frontendLatency
);
574 // If we are not already scheduled to get a request out of the
576 if (!nextReqEvent
.scheduled()) {
577 DPRINTF(DRAM
, "Request scheduled immediately\n");
578 schedule(nextReqEvent
, curTick());
583 DRAMCtrl::printQs() const {
584 DPRINTF(DRAM
, "===READ QUEUE===\n\n");
585 for (auto i
= readQueue
.begin() ; i
!= readQueue
.end() ; ++i
) {
586 DPRINTF(DRAM
, "Read %lu\n", (*i
)->addr
);
588 DPRINTF(DRAM
, "\n===RESP QUEUE===\n\n");
589 for (auto i
= respQueue
.begin() ; i
!= respQueue
.end() ; ++i
) {
590 DPRINTF(DRAM
, "Response %lu\n", (*i
)->addr
);
592 DPRINTF(DRAM
, "\n===WRITE QUEUE===\n\n");
593 for (auto i
= writeQueue
.begin() ; i
!= writeQueue
.end() ; ++i
) {
594 DPRINTF(DRAM
, "Write %lu\n", (*i
)->addr
);
599 DRAMCtrl::recvTimingReq(PacketPtr pkt
)
601 // This is where we enter from the outside world
602 DPRINTF(DRAM
, "recvTimingReq: request %s addr %lld size %d\n",
603 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
605 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
608 panic_if(!(pkt
->isRead() || pkt
->isWrite()),
609 "Should only see read and writes at memory controller\n");
611 // Calc avg gap between requests
612 if (prevArrival
!= 0) {
613 totGap
+= curTick() - prevArrival
;
615 prevArrival
= curTick();
618 // Find out how many dram packets a pkt translates to
619 // If the burst size is equal or larger than the pkt size, then a pkt
620 // translates to only one dram packet. Otherwise, a pkt translates to
621 // multiple dram packets
622 unsigned size
= pkt
->getSize();
623 unsigned offset
= pkt
->getAddr() & (burstSize
- 1);
624 unsigned int dram_pkt_count
= divCeil(offset
+ size
, burstSize
);
626 // check local buffers and do not accept if full
629 if (readQueueFull(dram_pkt_count
)) {
630 DPRINTF(DRAM
, "Read queue full, not accepting\n");
631 // remember that we have to retry this port
636 addToReadQueue(pkt
, dram_pkt_count
);
638 bytesReadSys
+= size
;
641 assert(pkt
->isWrite());
643 if (writeQueueFull(dram_pkt_count
)) {
644 DPRINTF(DRAM
, "Write queue full, not accepting\n");
645 // remember that we have to retry this port
650 addToWriteQueue(pkt
, dram_pkt_count
);
652 bytesWrittenSys
+= size
;
660 DRAMCtrl::processRespondEvent()
663 "processRespondEvent(): Some req has reached its readyTime\n");
665 DRAMPacket
* dram_pkt
= respQueue
.front();
667 // if a read has reached its ready-time, decrement the number of reads
668 // At this point the packet has been handled and there is a possibility
669 // to switch to low-power mode if no other packet is available
670 --dram_pkt
->rankRef
.readEntries
;
671 DPRINTF(DRAM
, "number of read entries for rank %d is %d\n",
672 dram_pkt
->rank
, dram_pkt
->rankRef
.readEntries
);
674 // counter should at least indicate one outstanding request
676 assert(dram_pkt
->rankRef
.outstandingEvents
> 0);
677 // read response received, decrement count
678 --dram_pkt
->rankRef
.outstandingEvents
;
680 // at this moment should be either ACT or IDLE depending on
681 // if PRE has occurred to close all banks
682 assert((dram_pkt
->rankRef
.pwrState
== PWR_ACT
) ||
683 (dram_pkt
->rankRef
.pwrState
== PWR_IDLE
));
685 // track if this is the last packet before idling
686 // and that there are no outstanding commands to this rank
687 if (dram_pkt
->rankRef
.lowPowerEntryReady()) {
688 // verify that there are no events scheduled
689 assert(!dram_pkt
->rankRef
.activateEvent
.scheduled());
690 assert(!dram_pkt
->rankRef
.prechargeEvent
.scheduled());
691 assert(dram_pkt
->rankRef
.refreshState
== REF_IDLE
);
693 // if coming from active state, schedule power event to
694 // active power-down else go to precharge power-down
695 DPRINTF(DRAMState
, "Rank %d sleep at tick %d; current power state is "
696 "%d\n", dram_pkt
->rank
, curTick(), dram_pkt
->rankRef
.pwrState
);
698 // default to ACT power-down unless already in IDLE state
699 // could be in IDLE if PRE issued before data returned
700 PowerState next_pwr_state
= PWR_ACT_PDN
;
701 if (dram_pkt
->rankRef
.pwrState
== PWR_IDLE
) {
702 next_pwr_state
= PWR_PRE_PDN
;
705 dram_pkt
->rankRef
.powerDownSleep(next_pwr_state
, curTick());
708 if (dram_pkt
->burstHelper
) {
709 // it is a split packet
710 dram_pkt
->burstHelper
->burstsServiced
++;
711 if (dram_pkt
->burstHelper
->burstsServiced
==
712 dram_pkt
->burstHelper
->burstCount
) {
713 // we have now serviced all children packets of a system packet
714 // so we can now respond to the requester
715 // @todo we probably want to have a different front end and back
716 // end latency for split packets
717 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
718 delete dram_pkt
->burstHelper
;
719 dram_pkt
->burstHelper
= NULL
;
722 // it is not a split packet
723 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
726 delete respQueue
.front();
727 respQueue
.pop_front();
729 if (!respQueue
.empty()) {
730 assert(respQueue
.front()->readyTime
>= curTick());
731 assert(!respondEvent
.scheduled());
732 schedule(respondEvent
, respQueue
.front()->readyTime
);
734 // if there is nothing left in any queue, signal a drain
735 if (drainState() == DrainState::Draining
&&
736 writeQueue
.empty() && readQueue
.empty() && allRanksDrained()) {
738 DPRINTF(Drain
, "DRAM controller done draining\n");
743 // We have made a location in the queue available at this point,
744 // so if there is a read that was forced to wait, retry now
752 DRAMCtrl::chooseNext(std::deque
<DRAMPacket
*>& queue
, Tick extra_col_delay
)
754 // This method does the arbitration between requests. The chosen
755 // packet is simply moved to the head of the queue. The other
756 // methods know that this is the place to look. For example, with
757 // FCFS, this method does nothing
758 assert(!queue
.empty());
760 // bool to indicate if a packet to an available rank is found
761 bool found_packet
= false;
762 if (queue
.size() == 1) {
763 DRAMPacket
* dram_pkt
= queue
.front();
764 // available rank corresponds to state refresh idle
765 if (ranks
[dram_pkt
->rank
]->isAvailable()) {
767 DPRINTF(DRAM
, "Single request, going to a free rank\n");
769 DPRINTF(DRAM
, "Single request, going to a busy rank\n");
774 if (memSchedPolicy
== Enums::fcfs
) {
775 // check if there is a packet going to a free rank
776 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
777 DRAMPacket
* dram_pkt
= *i
;
778 if (ranks
[dram_pkt
->rank
]->isAvailable()) {
780 queue
.push_front(dram_pkt
);
785 } else if (memSchedPolicy
== Enums::frfcfs
) {
786 found_packet
= reorderQueue(queue
, extra_col_delay
);
788 panic("No scheduling policy chosen\n");
793 DRAMCtrl::reorderQueue(std::deque
<DRAMPacket
*>& queue
, Tick extra_col_delay
)
795 // Only determine this if needed
796 uint64_t earliest_banks
= 0;
797 bool hidden_bank_prep
= false;
799 // search for seamless row hits first, if no seamless row hit is
800 // found then determine if there are other packets that can be issued
801 // without incurring additional bus delay due to bank timing
802 // Will select closed rows first to enable more open row possibilies
803 // in future selections
804 bool found_hidden_bank
= false;
806 // remember if we found a row hit, not seamless, but bank prepped
808 bool found_prepped_pkt
= false;
810 // if we have no row hit, prepped or not, and no seamless packet,
811 // just go for the earliest possible
812 bool found_earliest_pkt
= false;
814 auto selected_pkt_it
= queue
.end();
816 // time we need to issue a column command to be seamless
817 const Tick min_col_at
= std::max(busBusyUntil
- tCL
+ extra_col_delay
,
820 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
821 DRAMPacket
* dram_pkt
= *i
;
822 const Bank
& bank
= dram_pkt
->bankRef
;
824 // check if rank is available, if not, jump to the next packet
825 if (dram_pkt
->rankRef
.isAvailable()) {
826 // check if it is a row hit
827 if (bank
.openRow
== dram_pkt
->row
) {
828 // no additional rank-to-rank or same bank-group
829 // delays, or we switched read/write and might as well
830 // go for the row hit
831 if (bank
.colAllowedAt
<= min_col_at
) {
832 // FCFS within the hits, giving priority to
833 // commands that can issue seamlessly, without
834 // additional delay, such as same rank accesses
835 // and/or different bank-group accesses
836 DPRINTF(DRAM
, "Seamless row buffer hit\n");
838 // no need to look through the remaining queue entries
840 } else if (!found_hidden_bank
&& !found_prepped_pkt
) {
841 // if we did not find a packet to a closed row that can
842 // issue the bank commands without incurring delay, and
843 // did not yet find a packet to a prepped row, remember
846 found_prepped_pkt
= true;
847 DPRINTF(DRAM
, "Prepped row buffer hit\n");
849 } else if (!found_earliest_pkt
) {
850 // if we have not initialised the bank status, do it
851 // now, and only once per scheduling decisions
852 if (earliest_banks
== 0) {
853 // determine entries with earliest bank delay
854 pair
<uint64_t, bool> bankStatus
=
855 minBankPrep(queue
, min_col_at
);
856 earliest_banks
= bankStatus
.first
;
857 hidden_bank_prep
= bankStatus
.second
;
860 // bank is amongst first available banks
861 // minBankPrep will give priority to packets that can
863 if (bits(earliest_banks
, dram_pkt
->bankId
, dram_pkt
->bankId
)) {
864 found_earliest_pkt
= true;
865 found_hidden_bank
= hidden_bank_prep
;
867 // give priority to packets that can issue
868 // bank commands 'behind the scenes'
869 // any additional delay if any will be due to
870 // col-to-col command requirements
871 if (hidden_bank_prep
|| !found_prepped_pkt
)
878 if (selected_pkt_it
!= queue
.end()) {
879 DRAMPacket
* selected_pkt
= *selected_pkt_it
;
880 queue
.erase(selected_pkt_it
);
881 queue
.push_front(selected_pkt
);
889 DRAMCtrl::accessAndRespond(PacketPtr pkt
, Tick static_latency
)
891 DPRINTF(DRAM
, "Responding to Address %lld.. ",pkt
->getAddr());
893 bool needsResponse
= pkt
->needsResponse();
894 // do the actual memory access which also turns the packet into a
898 // turn packet around to go back to requester if response expected
900 // access already turned the packet into a response
901 assert(pkt
->isResponse());
902 // response_time consumes the static latency and is charged also
903 // with headerDelay that takes into account the delay provided by
904 // the xbar and also the payloadDelay that takes into account the
905 // number of data beats.
906 Tick response_time
= curTick() + static_latency
+ pkt
->headerDelay
+
908 // Here we reset the timing of the packet before sending it out.
909 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
911 // queue the packet in the response queue to be sent out after
912 // the static latency has passed
913 port
.schedTimingResp(pkt
, response_time
, true);
915 // @todo the packet is going to be deleted, and the DRAMPacket
916 // is still having a pointer to it
917 pendingDelete
.reset(pkt
);
920 DPRINTF(DRAM
, "Done\n");
926 DRAMCtrl::activateBank(Rank
& rank_ref
, Bank
& bank_ref
,
927 Tick act_tick
, uint32_t row
)
929 assert(rank_ref
.actTicks
.size() == activationLimit
);
931 DPRINTF(DRAM
, "Activate at tick %d\n", act_tick
);
933 // update the open row
934 assert(bank_ref
.openRow
== Bank::NO_ROW
);
935 bank_ref
.openRow
= row
;
937 // start counting anew, this covers both the case when we
938 // auto-precharged, and when this access is forced to
940 bank_ref
.bytesAccessed
= 0;
941 bank_ref
.rowAccesses
= 0;
943 ++rank_ref
.numBanksActive
;
944 assert(rank_ref
.numBanksActive
<= banksPerRank
);
946 DPRINTF(DRAM
, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
947 bank_ref
.bank
, rank_ref
.rank
, act_tick
,
948 ranks
[rank_ref
.rank
]->numBanksActive
);
950 rank_ref
.cmdList
.push_back(Command(MemCommand::ACT
, bank_ref
.bank
,
953 DPRINTF(DRAMPower
, "%llu,ACT,%d,%d\n", divCeil(act_tick
, tCK
) -
954 timeStampOffset
, bank_ref
.bank
, rank_ref
.rank
);
956 // The next access has to respect tRAS for this bank
957 bank_ref
.preAllowedAt
= act_tick
+ tRAS
;
959 // Respect the row-to-column command delay
960 bank_ref
.colAllowedAt
= std::max(act_tick
+ tRCD
, bank_ref
.colAllowedAt
);
962 // start by enforcing tRRD
963 for (int i
= 0; i
< banksPerRank
; i
++) {
964 // next activate to any bank in this rank must not happen
966 if (bankGroupArch
&& (bank_ref
.bankgr
== rank_ref
.banks
[i
].bankgr
)) {
967 // bank group architecture requires longer delays between
968 // ACT commands within the same bank group. Use tRRD_L
970 rank_ref
.banks
[i
].actAllowedAt
= std::max(act_tick
+ tRRD_L
,
971 rank_ref
.banks
[i
].actAllowedAt
);
973 // use shorter tRRD value when either
974 // 1) bank group architecture is not supportted
975 // 2) bank is in a different bank group
976 rank_ref
.banks
[i
].actAllowedAt
= std::max(act_tick
+ tRRD
,
977 rank_ref
.banks
[i
].actAllowedAt
);
981 // next, we deal with tXAW, if the activation limit is disabled
982 // then we directly schedule an activate power event
983 if (!rank_ref
.actTicks
.empty()) {
985 if (rank_ref
.actTicks
.back() &&
986 (act_tick
- rank_ref
.actTicks
.back()) < tXAW
) {
987 panic("Got %d activates in window %d (%llu - %llu) which "
988 "is smaller than %llu\n", activationLimit
, act_tick
-
989 rank_ref
.actTicks
.back(), act_tick
,
990 rank_ref
.actTicks
.back(), tXAW
);
993 // shift the times used for the book keeping, the last element
994 // (highest index) is the oldest one and hence the lowest value
995 rank_ref
.actTicks
.pop_back();
997 // record an new activation (in the future)
998 rank_ref
.actTicks
.push_front(act_tick
);
1000 // cannot activate more than X times in time window tXAW, push the
1001 // next one (the X + 1'st activate) to be tXAW away from the
1002 // oldest in our window of X
1003 if (rank_ref
.actTicks
.back() &&
1004 (act_tick
- rank_ref
.actTicks
.back()) < tXAW
) {
1005 DPRINTF(DRAM
, "Enforcing tXAW with X = %d, next activate "
1006 "no earlier than %llu\n", activationLimit
,
1007 rank_ref
.actTicks
.back() + tXAW
);
1008 for (int j
= 0; j
< banksPerRank
; j
++)
1009 // next activate must not happen before end of window
1010 rank_ref
.banks
[j
].actAllowedAt
=
1011 std::max(rank_ref
.actTicks
.back() + tXAW
,
1012 rank_ref
.banks
[j
].actAllowedAt
);
1016 // at the point when this activate takes place, make sure we
1017 // transition to the active power state
1018 if (!rank_ref
.activateEvent
.scheduled())
1019 schedule(rank_ref
.activateEvent
, act_tick
);
1020 else if (rank_ref
.activateEvent
.when() > act_tick
)
1021 // move it sooner in time
1022 reschedule(rank_ref
.activateEvent
, act_tick
);
1026 DRAMCtrl::prechargeBank(Rank
& rank_ref
, Bank
& bank
, Tick pre_at
, bool trace
)
1028 // make sure the bank has an open row
1029 assert(bank
.openRow
!= Bank::NO_ROW
);
1031 // sample the bytes per activate here since we are closing
1033 bytesPerActivate
.sample(bank
.bytesAccessed
);
1035 bank
.openRow
= Bank::NO_ROW
;
1037 // no precharge allowed before this one
1038 bank
.preAllowedAt
= pre_at
;
1040 Tick pre_done_at
= pre_at
+ tRP
;
1042 bank
.actAllowedAt
= std::max(bank
.actAllowedAt
, pre_done_at
);
1044 assert(rank_ref
.numBanksActive
!= 0);
1045 --rank_ref
.numBanksActive
;
1047 DPRINTF(DRAM
, "Precharging bank %d, rank %d at tick %lld, now got "
1048 "%d active\n", bank
.bank
, rank_ref
.rank
, pre_at
,
1049 rank_ref
.numBanksActive
);
1053 rank_ref
.cmdList
.push_back(Command(MemCommand::PRE
, bank
.bank
,
1055 DPRINTF(DRAMPower
, "%llu,PRE,%d,%d\n", divCeil(pre_at
, tCK
) -
1056 timeStampOffset
, bank
.bank
, rank_ref
.rank
);
1058 // if we look at the current number of active banks we might be
1059 // tempted to think the DRAM is now idle, however this can be
1060 // undone by an activate that is scheduled to happen before we
1061 // would have reached the idle state, so schedule an event and
1062 // rather check once we actually make it to the point in time when
1063 // the (last) precharge takes place
1064 if (!rank_ref
.prechargeEvent
.scheduled()) {
1065 schedule(rank_ref
.prechargeEvent
, pre_done_at
);
1066 // New event, increment count
1067 ++rank_ref
.outstandingEvents
;
1068 } else if (rank_ref
.prechargeEvent
.when() < pre_done_at
) {
1069 reschedule(rank_ref
.prechargeEvent
, pre_done_at
);
1074 DRAMCtrl::doDRAMAccess(DRAMPacket
* dram_pkt
)
1076 DPRINTF(DRAM
, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1077 dram_pkt
->addr
, dram_pkt
->rank
, dram_pkt
->bank
, dram_pkt
->row
);
1080 Rank
& rank
= dram_pkt
->rankRef
;
1082 // are we in or transitioning to a low-power state and have not scheduled
1083 // a power-up event?
1084 // if so, wake up from power down to issue RD/WR burst
1085 if (rank
.inLowPowerState
) {
1086 assert(rank
.pwrState
!= PWR_SREF
);
1087 rank
.scheduleWakeUpEvent(tXP
);
1091 Bank
& bank
= dram_pkt
->bankRef
;
1093 // for the state we need to track if it is a row hit or not
1094 bool row_hit
= true;
1096 // respect any constraints on the command (e.g. tRCD or tCCD)
1097 Tick cmd_at
= std::max(bank
.colAllowedAt
, curTick());
1099 // Determine the access latency and update the bank state
1100 if (bank
.openRow
== dram_pkt
->row
) {
1105 // If there is a page open, precharge it.
1106 if (bank
.openRow
!= Bank::NO_ROW
) {
1107 prechargeBank(rank
, bank
, std::max(bank
.preAllowedAt
, curTick()));
1110 // next we need to account for the delay in activating the
1112 Tick act_tick
= std::max(bank
.actAllowedAt
, curTick());
1114 // Record the activation and deal with all the global timing
1115 // constraints caused be a new activation (tRRD and tXAW)
1116 activateBank(rank
, bank
, act_tick
, dram_pkt
->row
);
1118 // issue the command as early as possible
1119 cmd_at
= bank
.colAllowedAt
;
1122 // we need to wait until the bus is available before we can issue
1124 cmd_at
= std::max(cmd_at
, busBusyUntil
- tCL
);
1126 // update the packet ready time
1127 dram_pkt
->readyTime
= cmd_at
+ tCL
+ tBURST
;
1129 // only one burst can use the bus at any one point in time
1130 assert(dram_pkt
->readyTime
- busBusyUntil
>= tBURST
);
1132 // update the time for the next read/write burst for each
1133 // bank (add a max with tCCD/tCCD_L here)
1135 for (int j
= 0; j
< ranksPerChannel
; j
++) {
1136 for (int i
= 0; i
< banksPerRank
; i
++) {
1137 // next burst to same bank group in this rank must not happen
1138 // before tCCD_L. Different bank group timing requirement is
1139 // tBURST; Add tCS for different ranks
1140 if (dram_pkt
->rank
== j
) {
1141 if (bankGroupArch
&&
1142 (bank
.bankgr
== ranks
[j
]->banks
[i
].bankgr
)) {
1143 // bank group architecture requires longer delays between
1144 // RD/WR burst commands to the same bank group.
1145 // Use tCCD_L in this case
1148 // use tBURST (equivalent to tCCD_S), the shorter
1149 // cas-to-cas delay value, when either:
1150 // 1) bank group architecture is not supportted
1151 // 2) bank is in a different bank group
1155 // different rank is by default in a different bank group
1156 // use tBURST (equivalent to tCCD_S), which is the shorter
1157 // cas-to-cas delay in this case
1158 // Add tCS to account for rank-to-rank bus delay requirements
1159 cmd_dly
= tBURST
+ tCS
;
1161 ranks
[j
]->banks
[i
].colAllowedAt
= std::max(cmd_at
+ cmd_dly
,
1162 ranks
[j
]->banks
[i
].colAllowedAt
);
1166 // Save rank of current access
1167 activeRank
= dram_pkt
->rank
;
1169 // If this is a write, we also need to respect the write recovery
1170 // time before a precharge, in the case of a read, respect the
1171 // read to precharge constraint
1172 bank
.preAllowedAt
= std::max(bank
.preAllowedAt
,
1173 dram_pkt
->isRead
? cmd_at
+ tRTP
:
1174 dram_pkt
->readyTime
+ tWR
);
1176 // increment the bytes accessed and the accesses per row
1177 bank
.bytesAccessed
+= burstSize
;
1180 // if we reached the max, then issue with an auto-precharge
1181 bool auto_precharge
= pageMgmt
== Enums::close
||
1182 bank
.rowAccesses
== maxAccessesPerRow
;
1184 // if we did not hit the limit, we might still want to
1186 if (!auto_precharge
&&
1187 (pageMgmt
== Enums::open_adaptive
||
1188 pageMgmt
== Enums::close_adaptive
)) {
1189 // a twist on the open and close page policies:
1190 // 1) open_adaptive page policy does not blindly keep the
1191 // page open, but close it if there are no row hits, and there
1192 // are bank conflicts in the queue
1193 // 2) close_adaptive page policy does not blindly close the
1194 // page, but closes it only if there are no row hits in the queue.
1195 // In this case, only force an auto precharge when there
1196 // are no same page hits in the queue
1197 bool got_more_hits
= false;
1198 bool got_bank_conflict
= false;
1200 // either look at the read queue or write queue
1201 const deque
<DRAMPacket
*>& queue
= dram_pkt
->isRead
? readQueue
:
1203 auto p
= queue
.begin();
1204 // make sure we are not considering the packet that we are
1205 // currently dealing with (which is the head of the queue)
1208 // keep on looking until we find a hit or reach the end of the queue
1209 // 1) if a hit is found, then both open and close adaptive policies keep
1211 // 2) if no hit is found, got_bank_conflict is set to true if a bank
1212 // conflict request is waiting in the queue
1213 while (!got_more_hits
&& p
!= queue
.end()) {
1214 bool same_rank_bank
= (dram_pkt
->rank
== (*p
)->rank
) &&
1215 (dram_pkt
->bank
== (*p
)->bank
);
1216 bool same_row
= dram_pkt
->row
== (*p
)->row
;
1217 got_more_hits
|= same_rank_bank
&& same_row
;
1218 got_bank_conflict
|= same_rank_bank
&& !same_row
;
1222 // auto pre-charge when either
1223 // 1) open_adaptive policy, we have not got any more hits, and
1224 // have a bank conflict
1225 // 2) close_adaptive policy and we have not got any more hits
1226 auto_precharge
= !got_more_hits
&&
1227 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
);
1230 // DRAMPower trace command to be written
1231 std::string mem_cmd
= dram_pkt
->isRead
? "RD" : "WR";
1233 // MemCommand required for DRAMPower library
1234 MemCommand::cmds command
= (mem_cmd
== "RD") ? MemCommand::RD
:
1238 busBusyUntil
= dram_pkt
->readyTime
;
1240 DPRINTF(DRAM
, "Access to %lld, ready at %lld bus busy until %lld.\n",
1241 dram_pkt
->addr
, dram_pkt
->readyTime
, busBusyUntil
);
1243 dram_pkt
->rankRef
.cmdList
.push_back(Command(command
, dram_pkt
->bank
,
1246 DPRINTF(DRAMPower
, "%llu,%s,%d,%d\n", divCeil(cmd_at
, tCK
) -
1247 timeStampOffset
, mem_cmd
, dram_pkt
->bank
, dram_pkt
->rank
);
1249 // if this access should use auto-precharge, then we are
1250 // closing the row after the read/write burst
1251 if (auto_precharge
) {
1252 // if auto-precharge push a PRE command at the correct tick to the
1253 // list used by DRAMPower library to calculate power
1254 prechargeBank(rank
, bank
, std::max(curTick(), bank
.preAllowedAt
));
1256 DPRINTF(DRAM
, "Auto-precharged bank: %d\n", dram_pkt
->bankId
);
1259 // Update the minimum timing between the requests, this is a
1260 // conservative estimate of when we have to schedule the next
1261 // request to not introduce any unecessary bubbles. In most cases
1262 // we will wake up sooner than we have to.
1263 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1265 // Update the stats and schedule the next request
1266 if (dram_pkt
->isRead
) {
1270 bytesReadDRAM
+= burstSize
;
1271 perBankRdBursts
[dram_pkt
->bankId
]++;
1273 // Update latency stats
1274 totMemAccLat
+= dram_pkt
->readyTime
- dram_pkt
->entryTime
;
1275 totBusLat
+= tBURST
;
1276 totQLat
+= cmd_at
- dram_pkt
->entryTime
;
1281 bytesWritten
+= burstSize
;
1282 perBankWrBursts
[dram_pkt
->bankId
]++;
1287 DRAMCtrl::processNextReqEvent()
1290 for (auto r
: ranks
) {
1291 if (!r
->isAvailable()) {
1292 if (r
->pwrState
!= PWR_SREF
) {
1293 // rank is busy refreshing
1294 DPRINTF(DRAMState
, "Rank %d is not available\n", r
->rank
);
1297 // let the rank know that if it was waiting to drain, it
1298 // is now done and ready to proceed
1299 r
->checkDrainDone();
1302 // check if we were in self-refresh and haven't started
1303 // to transition out
1304 if ((r
->pwrState
== PWR_SREF
) && r
->inLowPowerState
) {
1305 DPRINTF(DRAMState
, "Rank %d is in self-refresh\n", r
->rank
);
1306 // if we have commands queued to this rank and we don't have
1307 // a minimum number of active commands enqueued,
1308 // exit self-refresh
1309 if (r
->forceSelfRefreshExit()) {
1310 DPRINTF(DRAMState
, "rank %d was in self refresh and"
1311 " should wake up\n", r
->rank
);
1312 //wake up from self-refresh
1313 r
->scheduleWakeUpEvent(tXS
);
1314 // things are brought back into action once a refresh is
1315 // performed after self-refresh
1316 // continue with selection for other ranks
1322 if (busyRanks
== ranksPerChannel
) {
1323 // if all ranks are refreshing wait for them to finish
1324 // and stall this state machine without taking any further
1325 // action, and do not schedule a new nextReqEvent
1329 // pre-emptively set to false. Overwrite if in transitioning to
1331 bool switched_cmd_type
= false;
1332 if (busState
!= busStateNext
) {
1333 if (busState
== READ
) {
1334 DPRINTF(DRAM
, "Switching to writes after %d reads with %d reads "
1335 "waiting\n", readsThisTime
, readQueue
.size());
1337 // sample and reset the read-related stats as we are now
1338 // transitioning to writes, and all reads are done
1339 rdPerTurnAround
.sample(readsThisTime
);
1342 // now proceed to do the actual writes
1343 switched_cmd_type
= true;
1345 DPRINTF(DRAM
, "Switching to reads after %d writes with %d writes "
1346 "waiting\n", writesThisTime
, writeQueue
.size());
1348 wrPerTurnAround
.sample(writesThisTime
);
1351 switched_cmd_type
= true;
1353 // update busState to match next state until next transition
1354 busState
= busStateNext
;
1357 // when we get here it is either a read or a write
1358 if (busState
== READ
) {
1360 // track if we should switch or not
1361 bool switch_to_writes
= false;
1363 if (readQueue
.empty()) {
1364 // In the case there is no read request to go next,
1365 // trigger writes if we have passed the low threshold (or
1366 // if we are draining)
1367 if (!writeQueue
.empty() &&
1368 (drainState() == DrainState::Draining
||
1369 writeQueue
.size() > writeLowThreshold
)) {
1371 switch_to_writes
= true;
1373 // check if we are drained
1374 // not done draining until in PWR_IDLE state
1375 // ensuring all banks are closed and
1376 // have exited low power states
1377 if (drainState() == DrainState::Draining
&&
1378 respQueue
.empty() && allRanksDrained()) {
1380 DPRINTF(Drain
, "DRAM controller done draining\n");
1384 // nothing to do, not even any point in scheduling an
1385 // event for the next request
1389 // bool to check if there is a read to a free rank
1390 bool found_read
= false;
1392 // Figure out which read request goes next, and move it to the
1393 // front of the read queue
1394 // If we are changing command type, incorporate the minimum
1395 // bus turnaround delay which will be tCS (different rank) case
1396 found_read
= chooseNext(readQueue
,
1397 switched_cmd_type
? tCS
: 0);
1399 // if no read to an available rank is found then return
1400 // at this point. There could be writes to the available ranks
1401 // which are above the required threshold. However, to
1402 // avoid adding more complexity to the code, return and wait
1403 // for a refresh event to kick things into action again.
1407 DRAMPacket
* dram_pkt
= readQueue
.front();
1408 assert(dram_pkt
->rankRef
.isAvailable());
1410 // here we get a bit creative and shift the bus busy time not
1411 // just the tWTR, but also a CAS latency to capture the fact
1412 // that we are allowed to prepare a new bank, but not issue a
1413 // read command until after tWTR, in essence we capture a
1414 // bubble on the data bus that is tWTR + tCL
1415 if (switched_cmd_type
&& dram_pkt
->rank
== activeRank
) {
1416 busBusyUntil
+= tWTR
+ tCL
;
1419 doDRAMAccess(dram_pkt
);
1421 // At this point we're done dealing with the request
1422 readQueue
.pop_front();
1424 // Every respQueue which will generate an event, increment count
1425 ++dram_pkt
->rankRef
.outstandingEvents
;
1428 assert(dram_pkt
->size
<= burstSize
);
1429 assert(dram_pkt
->readyTime
>= curTick());
1431 // Insert into response queue. It will be sent back to the
1432 // requestor at its readyTime
1433 if (respQueue
.empty()) {
1434 assert(!respondEvent
.scheduled());
1435 schedule(respondEvent
, dram_pkt
->readyTime
);
1437 assert(respQueue
.back()->readyTime
<= dram_pkt
->readyTime
);
1438 assert(respondEvent
.scheduled());
1441 respQueue
.push_back(dram_pkt
);
1443 // we have so many writes that we have to transition
1444 if (writeQueue
.size() > writeHighThreshold
) {
1445 switch_to_writes
= true;
1449 // switching to writes, either because the read queue is empty
1450 // and the writes have passed the low threshold (or we are
1451 // draining), or because the writes hit the hight threshold
1452 if (switch_to_writes
) {
1453 // transition to writing
1454 busStateNext
= WRITE
;
1457 // bool to check if write to free rank is found
1458 bool found_write
= false;
1460 // If we are changing command type, incorporate the minimum
1461 // bus turnaround delay
1462 found_write
= chooseNext(writeQueue
,
1463 switched_cmd_type
? std::min(tRTW
, tCS
) : 0);
1465 // if no writes to an available rank are found then return.
1466 // There could be reads to the available ranks. However, to avoid
1467 // adding more complexity to the code, return at this point and wait
1468 // for a refresh event to kick things into action again.
1472 DRAMPacket
* dram_pkt
= writeQueue
.front();
1473 assert(dram_pkt
->rankRef
.isAvailable());
1475 assert(dram_pkt
->size
<= burstSize
);
1477 // add a bubble to the data bus, as defined by the
1478 // tRTW when access is to the same rank as previous burst
1479 // Different rank timing is handled with tCS, which is
1480 // applied to colAllowedAt
1481 if (switched_cmd_type
&& dram_pkt
->rank
== activeRank
) {
1482 busBusyUntil
+= tRTW
;
1485 doDRAMAccess(dram_pkt
);
1487 writeQueue
.pop_front();
1489 // removed write from queue, decrement count
1490 --dram_pkt
->rankRef
.writeEntries
;
1492 // Schedule write done event to decrement event count
1493 // after the readyTime has been reached
1494 // Only schedule latest write event to minimize events
1495 // required; only need to ensure that final event scheduled covers
1496 // the time that writes are outstanding and bus is active
1497 // to holdoff power-down entry events
1498 if (!dram_pkt
->rankRef
.writeDoneEvent
.scheduled()) {
1499 schedule(dram_pkt
->rankRef
.writeDoneEvent
, dram_pkt
->readyTime
);
1500 // New event, increment count
1501 ++dram_pkt
->rankRef
.outstandingEvents
;
1503 } else if (dram_pkt
->rankRef
.writeDoneEvent
.when() <
1504 dram_pkt
-> readyTime
) {
1505 reschedule(dram_pkt
->rankRef
.writeDoneEvent
, dram_pkt
->readyTime
);
1508 isInWriteQueue
.erase(burstAlign(dram_pkt
->addr
));
1511 // If we emptied the write queue, or got sufficiently below the
1512 // threshold (using the minWritesPerSwitch as the hysteresis) and
1513 // are not draining, or we have reads waiting and have done enough
1514 // writes, then switch to reads.
1515 if (writeQueue
.empty() ||
1516 (writeQueue
.size() + minWritesPerSwitch
< writeLowThreshold
&&
1517 drainState() != DrainState::Draining
) ||
1518 (!readQueue
.empty() && writesThisTime
>= minWritesPerSwitch
)) {
1519 // turn the bus back around for reads again
1520 busStateNext
= READ
;
1522 // note that the we switch back to reads also in the idle
1523 // case, which eventually will check for any draining and
1524 // also pause any further scheduling if there is really
1528 // It is possible that a refresh to another rank kicks things back into
1529 // action before reaching this point.
1530 if (!nextReqEvent
.scheduled())
1531 schedule(nextReqEvent
, std::max(nextReqTime
, curTick()));
1533 // If there is space available and we have writes waiting then let
1534 // them retry. This is done here to ensure that the retry does not
1535 // cause a nextReqEvent to be scheduled before we do so as part of
1536 // the next request processing
1537 if (retryWrReq
&& writeQueue
.size() < writeBufferSize
) {
1539 port
.sendRetryReq();
1543 pair
<uint64_t, bool>
1544 DRAMCtrl::minBankPrep(const deque
<DRAMPacket
*>& queue
,
1545 Tick min_col_at
) const
1547 uint64_t bank_mask
= 0;
1548 Tick min_act_at
= MaxTick
;
1550 // latest Tick for which ACT can occur without incurring additoinal
1551 // delay on the data bus
1552 const Tick hidden_act_max
= std::max(min_col_at
- tRCD
, curTick());
1554 // Flag condition when burst can issue back-to-back with previous burst
1555 bool found_seamless_bank
= false;
1557 // Flag condition when bank can be opened without incurring additional
1558 // delay on the data bus
1559 bool hidden_bank_prep
= false;
1561 // determine if we have queued transactions targetting the
1563 vector
<bool> got_waiting(ranksPerChannel
* banksPerRank
, false);
1564 for (const auto& p
: queue
) {
1565 if (p
->rankRef
.isAvailable())
1566 got_waiting
[p
->bankId
] = true;
1569 // Find command with optimal bank timing
1570 // Will prioritize commands that can issue seamlessly.
1571 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1572 for (int j
= 0; j
< banksPerRank
; j
++) {
1573 uint16_t bank_id
= i
* banksPerRank
+ j
;
1575 // if we have waiting requests for the bank, and it is
1576 // amongst the first available, update the mask
1577 if (got_waiting
[bank_id
]) {
1578 // make sure this rank is not currently refreshing.
1579 assert(ranks
[i
]->isAvailable());
1580 // simplistic approximation of when the bank can issue
1581 // an activate, ignoring any rank-to-rank switching
1582 // cost in this calculation
1583 Tick act_at
= ranks
[i
]->banks
[j
].openRow
== Bank::NO_ROW
?
1584 std::max(ranks
[i
]->banks
[j
].actAllowedAt
, curTick()) :
1585 std::max(ranks
[i
]->banks
[j
].preAllowedAt
, curTick()) + tRP
;
1587 // When is the earliest the R/W burst can issue?
1588 Tick col_at
= std::max(ranks
[i
]->banks
[j
].colAllowedAt
,
1591 // bank can issue burst back-to-back (seamlessly) with
1593 bool new_seamless_bank
= col_at
<= min_col_at
;
1595 // if we found a new seamless bank or we have no
1596 // seamless banks, and got a bank with an earlier
1597 // activate time, it should be added to the bit mask
1598 if (new_seamless_bank
||
1599 (!found_seamless_bank
&& act_at
<= min_act_at
)) {
1600 // if we did not have a seamless bank before, and
1601 // we do now, reset the bank mask, also reset it
1602 // if we have not yet found a seamless bank and
1603 // the activate time is smaller than what we have
1605 if (!found_seamless_bank
&&
1606 (new_seamless_bank
|| act_at
< min_act_at
)) {
1610 found_seamless_bank
|= new_seamless_bank
;
1612 // ACT can occur 'behind the scenes'
1613 hidden_bank_prep
= act_at
<= hidden_act_max
;
1615 // set the bit corresponding to the available bank
1616 replaceBits(bank_mask
, bank_id
, bank_id
, 1);
1617 min_act_at
= act_at
;
1623 return make_pair(bank_mask
, hidden_bank_prep
);
1626 DRAMCtrl::Rank::Rank(DRAMCtrl
& _memory
, const DRAMCtrlParams
* _p
)
1627 : EventManager(&_memory
), memory(_memory
),
1628 pwrStateTrans(PWR_IDLE
), pwrStatePostRefresh(PWR_IDLE
),
1629 pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE
),
1630 refreshState(REF_IDLE
), inLowPowerState(false), rank(0),
1631 readEntries(0), writeEntries(0), outstandingEvents(0),
1632 wakeUpAllowedAt(0), power(_p
, false), numBanksActive(0),
1633 writeDoneEvent(*this), activateEvent(*this), prechargeEvent(*this),
1634 refreshEvent(*this), powerEvent(*this), wakeUpEvent(*this)
1638 DRAMCtrl::Rank::startup(Tick ref_tick
)
1640 assert(ref_tick
> curTick());
1642 pwrStateTick
= curTick();
1644 // kick off the refresh, and give ourselves enough time to
1646 schedule(refreshEvent
, ref_tick
);
1650 DRAMCtrl::Rank::suspend()
1652 deschedule(refreshEvent
);
1657 // don't automatically transition back to LP state after next REF
1658 pwrStatePostRefresh
= PWR_IDLE
;
1662 DRAMCtrl::Rank::lowPowerEntryReady() const
1664 bool no_queued_cmds
= ((memory
.busStateNext
== READ
) && (readEntries
== 0))
1665 || ((memory
.busStateNext
== WRITE
) &&
1666 (writeEntries
== 0));
1668 if (refreshState
== REF_RUN
) {
1669 // have not decremented outstandingEvents for refresh command
1670 // still check if there are no commands queued to force PD
1671 // entry after refresh completes
1672 return no_queued_cmds
;
1674 // ensure no commands in Q and no commands scheduled
1675 return (no_queued_cmds
&& (outstandingEvents
== 0));
1680 DRAMCtrl::Rank::checkDrainDone()
1682 // if this rank was waiting to drain it is now able to proceed to
1684 if (refreshState
== REF_DRAIN
) {
1685 DPRINTF(DRAM
, "Refresh drain done, now precharging\n");
1687 refreshState
= REF_PD_EXIT
;
1689 // hand control back to the refresh event loop
1690 schedule(refreshEvent
, curTick());
1695 DRAMCtrl::Rank::flushCmdList()
1697 // at the moment sort the list of commands and update the counters
1698 // for DRAMPower libray when doing a refresh
1699 sort(cmdList
.begin(), cmdList
.end(), DRAMCtrl::sortTime
);
1701 auto next_iter
= cmdList
.begin();
1702 // push to commands to DRAMPower
1703 for ( ; next_iter
!= cmdList
.end() ; ++next_iter
) {
1704 Command cmd
= *next_iter
;
1705 if (cmd
.timeStamp
<= curTick()) {
1706 // Move all commands at or before curTick to DRAMPower
1707 power
.powerlib
.doCommand(cmd
.type
, cmd
.bank
,
1708 divCeil(cmd
.timeStamp
, memory
.tCK
) -
1709 memory
.timeStampOffset
);
1711 // done - found all commands at or before curTick()
1712 // next_iter references the 1st command after curTick
1716 // reset cmdList to only contain commands after curTick
1717 // if there are no commands after curTick, updated cmdList will be empty
1718 // in this case, next_iter is cmdList.end()
1719 cmdList
.assign(next_iter
, cmdList
.end());
1723 DRAMCtrl::Rank::processActivateEvent()
1725 // we should transition to the active state as soon as any bank is active
1726 if (pwrState
!= PWR_ACT
)
1727 // note that at this point numBanksActive could be back at
1728 // zero again due to a precharge scheduled in the future
1729 schedulePowerEvent(PWR_ACT
, curTick());
1733 DRAMCtrl::Rank::processPrechargeEvent()
1735 // counter should at least indicate one outstanding request
1736 // for this precharge
1737 assert(outstandingEvents
> 0);
1738 // precharge complete, decrement count
1739 --outstandingEvents
;
1741 // if we reached zero, then special conditions apply as we track
1742 // if all banks are precharged for the power models
1743 if (numBanksActive
== 0) {
1744 // no reads to this rank in the Q and no pending
1745 // RD/WR or refresh commands
1746 if (lowPowerEntryReady()) {
1747 // should still be in ACT state since bank still open
1748 assert(pwrState
== PWR_ACT
);
1750 // All banks closed - switch to precharge power down state.
1751 DPRINTF(DRAMState
, "Rank %d sleep at tick %d\n",
1753 powerDownSleep(PWR_PRE_PDN
, curTick());
1755 // we should transition to the idle state when the last bank
1757 schedulePowerEvent(PWR_IDLE
, curTick());
1763 DRAMCtrl::Rank::processWriteDoneEvent()
1765 // counter should at least indicate one outstanding request
1767 assert(outstandingEvents
> 0);
1768 // Write transfer on bus has completed
1769 // decrement per rank counter
1770 --outstandingEvents
;
1774 DRAMCtrl::Rank::processRefreshEvent()
1776 // when first preparing the refresh, remember when it was due
1777 if ((refreshState
== REF_IDLE
) || (refreshState
== REF_SREF_EXIT
)) {
1778 // remember when the refresh is due
1779 refreshDueAt
= curTick();
1782 refreshState
= REF_DRAIN
;
1784 // make nonzero while refresh is pending to ensure
1785 // power down and self-refresh are not entered
1786 ++outstandingEvents
;
1788 DPRINTF(DRAM
, "Refresh due\n");
1791 // let any scheduled read or write to the same rank go ahead,
1792 // after which it will
1793 // hand control back to this event loop
1794 if (refreshState
== REF_DRAIN
) {
1795 // if a request is at the moment being handled and this request is
1796 // accessing the current rank then wait for it to finish
1797 if ((rank
== memory
.activeRank
)
1798 && (memory
.nextReqEvent
.scheduled())) {
1799 // hand control over to the request loop until it is
1801 DPRINTF(DRAM
, "Refresh awaiting draining\n");
1805 refreshState
= REF_PD_EXIT
;
1809 // at this point, ensure that rank is not in a power-down state
1810 if (refreshState
== REF_PD_EXIT
) {
1811 // if rank was sleeping and we have't started exit process,
1812 // wake-up for refresh
1813 if (inLowPowerState
) {
1814 DPRINTF(DRAM
, "Wake Up for refresh\n");
1815 // save state and return after refresh completes
1816 scheduleWakeUpEvent(memory
.tXP
);
1819 refreshState
= REF_PRE
;
1823 // at this point, ensure that all banks are precharged
1824 if (refreshState
== REF_PRE
) {
1825 // precharge any active bank
1826 if (numBanksActive
!= 0) {
1827 // at the moment, we use a precharge all even if there is
1828 // only a single bank open
1829 DPRINTF(DRAM
, "Precharging all\n");
1831 // first determine when we can precharge
1832 Tick pre_at
= curTick();
1834 for (auto &b
: banks
) {
1835 // respect both causality and any existing bank
1836 // constraints, some banks could already have a
1837 // (auto) precharge scheduled
1838 pre_at
= std::max(b
.preAllowedAt
, pre_at
);
1841 // make sure all banks per rank are precharged, and for those that
1842 // already are, update their availability
1843 Tick act_allowed_at
= pre_at
+ memory
.tRP
;
1845 for (auto &b
: banks
) {
1846 if (b
.openRow
!= Bank::NO_ROW
) {
1847 memory
.prechargeBank(*this, b
, pre_at
, false);
1849 b
.actAllowedAt
= std::max(b
.actAllowedAt
, act_allowed_at
);
1850 b
.preAllowedAt
= std::max(b
.preAllowedAt
, pre_at
);
1854 // precharge all banks in rank
1855 cmdList
.push_back(Command(MemCommand::PREA
, 0, pre_at
));
1857 DPRINTF(DRAMPower
, "%llu,PREA,0,%d\n",
1858 divCeil(pre_at
, memory
.tCK
) -
1859 memory
.timeStampOffset
, rank
);
1860 } else if ((pwrState
== PWR_IDLE
) && (outstandingEvents
== 1)) {
1861 // Banks are closed, have transitioned to IDLE state, and
1862 // no outstanding ACT,RD/WR,Auto-PRE sequence scheduled
1863 DPRINTF(DRAM
, "All banks already precharged, starting refresh\n");
1865 // go ahead and kick the power state machine into gear since
1866 // we are already idle
1867 schedulePowerEvent(PWR_REF
, curTick());
1869 // banks state is closed but haven't transitioned pwrState to IDLE
1870 // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled
1871 // should have outstanding precharge event in this case
1872 assert(prechargeEvent
.scheduled());
1873 // will start refresh when pwrState transitions to IDLE
1876 assert(numBanksActive
== 0);
1878 // wait for all banks to be precharged, at which point the
1879 // power state machine will transition to the idle state, and
1880 // automatically move to a refresh, at that point it will also
1881 // call this method to get the refresh event loop going again
1885 // last but not least we perform the actual refresh
1886 if (refreshState
== REF_START
) {
1887 // should never get here with any banks active
1888 assert(numBanksActive
== 0);
1889 assert(pwrState
== PWR_REF
);
1891 Tick ref_done_at
= curTick() + memory
.tRFC
;
1893 for (auto &b
: banks
) {
1894 b
.actAllowedAt
= ref_done_at
;
1897 // at the moment this affects all ranks
1898 cmdList
.push_back(Command(MemCommand::REF
, 0, curTick()));
1903 DPRINTF(DRAMPower
, "%llu,REF,0,%d\n", divCeil(curTick(), memory
.tCK
) -
1904 memory
.timeStampOffset
, rank
);
1906 // Update for next refresh
1907 refreshDueAt
+= memory
.tREFI
;
1909 // make sure we did not wait so long that we cannot make up
1911 if (refreshDueAt
< ref_done_at
) {
1912 fatal("Refresh was delayed so long we cannot catch up\n");
1915 // Run the refresh and schedule event to transition power states
1916 // when refresh completes
1917 refreshState
= REF_RUN
;
1918 schedule(refreshEvent
, ref_done_at
);
1922 if (refreshState
== REF_RUN
) {
1923 // should never get here with any banks active
1924 assert(numBanksActive
== 0);
1925 assert(pwrState
== PWR_REF
);
1927 assert(!powerEvent
.scheduled());
1929 if ((memory
.drainState() == DrainState::Draining
) ||
1930 (memory
.drainState() == DrainState::Drained
)) {
1931 // if draining, do not re-enter low-power mode.
1932 // simply go to IDLE and wait
1933 schedulePowerEvent(PWR_IDLE
, curTick());
1935 // At the moment, we sleep when the refresh ends and wait to be
1936 // woken up again if previously in a low-power state.
1937 if (pwrStatePostRefresh
!= PWR_IDLE
) {
1938 // power State should be power Refresh
1939 assert(pwrState
== PWR_REF
);
1940 DPRINTF(DRAMState
, "Rank %d sleeping after refresh and was in "
1941 "power state %d before refreshing\n", rank
,
1942 pwrStatePostRefresh
);
1943 powerDownSleep(pwrState
, curTick());
1945 // Force PRE power-down if there are no outstanding commands
1946 // in Q after refresh.
1947 } else if (lowPowerEntryReady()) {
1948 DPRINTF(DRAMState
, "Rank %d sleeping after refresh but was NOT"
1949 " in a low power state before refreshing\n", rank
);
1950 powerDownSleep(PWR_PRE_PDN
, curTick());
1953 // move to the idle power state once the refresh is done, this
1954 // will also move the refresh state machine to the refresh
1956 schedulePowerEvent(PWR_IDLE
, curTick());
1960 // if transitioning to self refresh do not schedule a new refresh;
1961 // when waking from self refresh, a refresh is scheduled again.
1962 if (pwrStateTrans
!= PWR_SREF
) {
1963 // compensate for the delay in actually performing the refresh
1964 // when scheduling the next one
1965 schedule(refreshEvent
, refreshDueAt
- memory
.tRP
);
1967 DPRINTF(DRAMState
, "Refresh done at %llu and next refresh"
1968 " at %llu\n", curTick(), refreshDueAt
);
1974 DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state
, Tick tick
)
1976 // respect causality
1977 assert(tick
>= curTick());
1979 if (!powerEvent
.scheduled()) {
1980 DPRINTF(DRAMState
, "Scheduling power event at %llu to state %d\n",
1983 // insert the new transition
1984 pwrStateTrans
= pwr_state
;
1986 schedule(powerEvent
, tick
);
1988 panic("Scheduled power event at %llu to state %d, "
1989 "with scheduled event at %llu to %d\n", tick
, pwr_state
,
1990 powerEvent
.when(), pwrStateTrans
);
1995 DRAMCtrl::Rank::powerDownSleep(PowerState pwr_state
, Tick tick
)
1997 // if low power state is active low, schedule to active low power state.
1998 // in reality tCKE is needed to enter active low power. This is neglected
1999 // here and could be added in the future.
2000 if (pwr_state
== PWR_ACT_PDN
) {
2001 schedulePowerEvent(pwr_state
, tick
);
2002 // push command to DRAMPower
2003 cmdList
.push_back(Command(MemCommand::PDN_F_ACT
, 0, tick
));
2004 DPRINTF(DRAMPower
, "%llu,PDN_F_ACT,0,%d\n", divCeil(tick
,
2005 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2006 } else if (pwr_state
== PWR_PRE_PDN
) {
2007 // if low power state is precharge low, schedule to precharge low
2008 // power state. In reality tCKE is needed to enter active low power.
2009 // This is neglected here.
2010 schedulePowerEvent(pwr_state
, tick
);
2011 //push Command to DRAMPower
2012 cmdList
.push_back(Command(MemCommand::PDN_F_PRE
, 0, tick
));
2013 DPRINTF(DRAMPower
, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick
,
2014 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2015 } else if (pwr_state
== PWR_REF
) {
2016 // if a refresh just occured
2017 // transition to PRE_PDN now that all banks are closed
2018 // do not transition to SREF if commands are in Q; stay in PRE_PDN
2019 if (pwrStatePostRefresh
== PWR_ACT_PDN
|| !lowPowerEntryReady()) {
2020 // prechage power down requires tCKE to enter. For simplicity
2021 // this is not considered.
2022 schedulePowerEvent(PWR_PRE_PDN
, tick
);
2023 //push Command to DRAMPower
2024 cmdList
.push_back(Command(MemCommand::PDN_F_PRE
, 0, tick
));
2025 DPRINTF(DRAMPower
, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick
,
2026 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2028 // last low power State was power precharge
2029 assert(pwrStatePostRefresh
== PWR_PRE_PDN
);
2030 // self refresh requires time tCKESR to enter. For simplicity,
2031 // this is not considered.
2032 schedulePowerEvent(PWR_SREF
, tick
);
2033 // push Command to DRAMPower
2034 cmdList
.push_back(Command(MemCommand::SREN
, 0, tick
));
2035 DPRINTF(DRAMPower
, "%llu,SREN,0,%d\n", divCeil(tick
,
2036 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2039 // Ensure that we don't power-down and back up in same tick
2040 // Once we commit to PD entry, do it and wait for at least 1tCK
2041 // This could be replaced with tCKE if/when that is added to the model
2042 wakeUpAllowedAt
= tick
+ memory
.tCK
;
2044 // Transitioning to a low power state, set flag
2045 inLowPowerState
= true;
2049 DRAMCtrl::Rank::scheduleWakeUpEvent(Tick exit_delay
)
2051 Tick wake_up_tick
= std::max(curTick(), wakeUpAllowedAt
);
2053 DPRINTF(DRAMState
, "Scheduling wake-up for rank %d at tick %d\n",
2054 rank
, wake_up_tick
);
2056 // if waking for refresh, hold previous state
2057 // else reset state back to IDLE
2058 if (refreshState
== REF_PD_EXIT
) {
2059 pwrStatePostRefresh
= pwrState
;
2061 // don't automatically transition back to LP state after next REF
2062 pwrStatePostRefresh
= PWR_IDLE
;
2065 // schedule wake-up with event to ensure entry has completed before
2066 // we try to wake-up
2067 schedule(wakeUpEvent
, wake_up_tick
);
2069 for (auto &b
: banks
) {
2070 // respect both causality and any existing bank
2071 // constraints, some banks could already have a
2072 // (auto) precharge scheduled
2073 b
.colAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.colAllowedAt
);
2074 b
.preAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.preAllowedAt
);
2075 b
.actAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.actAllowedAt
);
2077 // Transitioning out of low power state, clear flag
2078 inLowPowerState
= false;
2080 // push to DRAMPower
2081 // use pwrStateTrans for cases where we have a power event scheduled
2082 // to enter low power that has not yet been processed
2083 if (pwrStateTrans
== PWR_ACT_PDN
) {
2084 cmdList
.push_back(Command(MemCommand::PUP_ACT
, 0, wake_up_tick
));
2085 DPRINTF(DRAMPower
, "%llu,PUP_ACT,0,%d\n", divCeil(wake_up_tick
,
2086 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2088 } else if (pwrStateTrans
== PWR_PRE_PDN
) {
2089 cmdList
.push_back(Command(MemCommand::PUP_PRE
, 0, wake_up_tick
));
2090 DPRINTF(DRAMPower
, "%llu,PUP_PRE,0,%d\n", divCeil(wake_up_tick
,
2091 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2092 } else if (pwrStateTrans
== PWR_SREF
) {
2093 cmdList
.push_back(Command(MemCommand::SREX
, 0, wake_up_tick
));
2094 DPRINTF(DRAMPower
, "%llu,SREX,0,%d\n", divCeil(wake_up_tick
,
2095 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2100 DRAMCtrl::Rank::processWakeUpEvent()
2102 // Should be in a power-down or self-refresh state
2103 assert((pwrState
== PWR_ACT_PDN
) || (pwrState
== PWR_PRE_PDN
) ||
2104 (pwrState
== PWR_SREF
));
2106 // Check current state to determine transition state
2107 if (pwrState
== PWR_ACT_PDN
) {
2108 // banks still open, transition to PWR_ACT
2109 schedulePowerEvent(PWR_ACT
, curTick());
2111 // transitioning from a precharge power-down or self-refresh state
2112 // banks are closed - transition to PWR_IDLE
2113 schedulePowerEvent(PWR_IDLE
, curTick());
2118 DRAMCtrl::Rank::processPowerEvent()
2120 assert(curTick() >= pwrStateTick
);
2121 // remember where we were, and for how long
2122 Tick duration
= curTick() - pwrStateTick
;
2123 PowerState prev_state
= pwrState
;
2125 // update the accounting
2126 pwrStateTime
[prev_state
] += duration
;
2128 // track to total idle time
2129 if ((prev_state
== PWR_PRE_PDN
) || (prev_state
== PWR_ACT_PDN
) ||
2130 (prev_state
== PWR_SREF
)) {
2131 totalIdleTime
+= duration
;
2134 pwrState
= pwrStateTrans
;
2135 pwrStateTick
= curTick();
2137 // if rank was refreshing, make sure to start scheduling requests again
2138 if (prev_state
== PWR_REF
) {
2139 // bus IDLED prior to REF
2140 // counter should be one for refresh command only
2141 assert(outstandingEvents
== 1);
2142 // REF complete, decrement count
2143 --outstandingEvents
;
2145 DPRINTF(DRAMState
, "Was refreshing for %llu ticks\n", duration
);
2146 // if sleeping after refresh
2147 if (pwrState
!= PWR_IDLE
) {
2148 assert((pwrState
== PWR_PRE_PDN
) || (pwrState
== PWR_SREF
));
2149 DPRINTF(DRAMState
, "Switching to power down state after refreshing"
2150 " rank %d at %llu tick\n", rank
, curTick());
2152 if (pwrState
!= PWR_SREF
) {
2153 // rank is not available in SREF
2154 // don't transition to IDLE in this case
2155 refreshState
= REF_IDLE
;
2157 // a request event could be already scheduled by the state
2158 // machine of the other rank
2159 if (!memory
.nextReqEvent
.scheduled()) {
2160 DPRINTF(DRAM
, "Scheduling next request after refreshing rank %d\n",
2162 schedule(memory
.nextReqEvent
, curTick());
2164 } else if (pwrState
== PWR_ACT
) {
2165 if (refreshState
== REF_PD_EXIT
) {
2166 // kick the refresh event loop into action again
2167 assert(prev_state
== PWR_ACT_PDN
);
2169 // go back to REF event and close banks
2170 refreshState
= REF_PRE
;
2171 schedule(refreshEvent
, curTick());
2173 } else if (pwrState
== PWR_IDLE
) {
2174 DPRINTF(DRAMState
, "All banks precharged\n");
2175 if (prev_state
== PWR_SREF
) {
2176 // set refresh state to REF_SREF_EXIT, ensuring isAvailable
2177 // continues to return false during tXS after SREF exit
2178 // Schedule a refresh which kicks things back into action
2180 refreshState
= REF_SREF_EXIT
;
2181 schedule(refreshEvent
, curTick() + memory
.tXS
);
2183 // if we have a pending refresh, and are now moving to
2184 // the idle state, directly transition to a refresh
2185 if ((refreshState
== REF_PRE
) || (refreshState
== REF_PD_EXIT
)) {
2186 // ensure refresh is restarted only after final PRE command.
2187 // do not restart refresh if controller is in an intermediate
2188 // state, after PRE_PDN exit, when banks are IDLE but an
2189 // ACT is scheduled.
2190 if (!activateEvent
.scheduled()) {
2191 // there should be nothing waiting at this point
2192 assert(!powerEvent
.scheduled());
2193 // update the state in zero time and proceed below
2196 // must have PRE scheduled to transition back to IDLE
2197 // and re-kick off refresh
2198 assert(prechargeEvent
.scheduled());
2204 // we transition to the refresh state, let the refresh state
2205 // machine know of this state update and let it deal with the
2206 // scheduling of the next power state transition as well as the
2207 // following refresh
2208 if (pwrState
== PWR_REF
) {
2209 assert(refreshState
== REF_PRE
|| refreshState
== REF_PD_EXIT
);
2210 DPRINTF(DRAMState
, "Refreshing\n");
2212 // kick the refresh event loop into action again, and that
2213 // in turn will schedule a transition to the idle power
2214 // state once the refresh is done
2215 if (refreshState
== REF_PD_EXIT
) {
2216 // Wait for PD exit timing to complete before issuing REF
2217 schedule(refreshEvent
, curTick() + memory
.tXP
);
2219 schedule(refreshEvent
, curTick());
2221 // Banks transitioned to IDLE, start REF
2222 refreshState
= REF_START
;
2227 DRAMCtrl::Rank::updatePowerStats()
2229 // All commands up to refresh have completed
2230 // flush cmdList to DRAMPower
2233 // update the counters for DRAMPower, passing false to
2234 // indicate that this is not the last command in the
2235 // list. DRAMPower requires this information for the
2236 // correct calculation of the background energy at the end
2237 // of the simulation. Ideally we would want to call this
2238 // function with true once at the end of the
2239 // simulation. However, the discarded energy is extremly
2240 // small and does not effect the final results.
2241 power
.powerlib
.updateCounters(false);
2243 // call the energy function
2244 power
.powerlib
.calcEnergy();
2246 // Get the energy and power from DRAMPower
2247 Data::MemoryPowerModel::Energy energy
=
2248 power
.powerlib
.getEnergy();
2249 Data::MemoryPowerModel::Power rank_power
=
2250 power
.powerlib
.getPower();
2252 actEnergy
= energy
.act_energy
* memory
.devicesPerRank
;
2253 preEnergy
= energy
.pre_energy
* memory
.devicesPerRank
;
2254 readEnergy
= energy
.read_energy
* memory
.devicesPerRank
;
2255 writeEnergy
= energy
.write_energy
* memory
.devicesPerRank
;
2256 refreshEnergy
= energy
.ref_energy
* memory
.devicesPerRank
;
2257 actBackEnergy
= energy
.act_stdby_energy
* memory
.devicesPerRank
;
2258 preBackEnergy
= energy
.pre_stdby_energy
* memory
.devicesPerRank
;
2259 actPowerDownEnergy
= energy
.f_act_pd_energy
* memory
.devicesPerRank
;
2260 prePowerDownEnergy
= energy
.f_pre_pd_energy
* memory
.devicesPerRank
;
2261 selfRefreshEnergy
= energy
.sref_energy
* memory
.devicesPerRank
;
2262 totalEnergy
= energy
.total_energy
* memory
.devicesPerRank
;
2263 averagePower
= rank_power
.average_power
* memory
.devicesPerRank
;
2267 DRAMCtrl::Rank::computeStats()
2269 DPRINTF(DRAM
,"Computing final stats\n");
2271 // Force DRAM power to update counters based on time spent in
2272 // current state up to curTick()
2273 cmdList
.push_back(Command(MemCommand::NOP
, 0, curTick()));
2278 // final update of power state times
2279 pwrStateTime
[pwrState
] += (curTick() - pwrStateTick
);
2280 pwrStateTick
= curTick();
2285 DRAMCtrl::Rank::regStats()
2287 using namespace Stats
;
2291 .name(name() + ".memoryStateTime")
2292 .desc("Time in different power states");
2293 pwrStateTime
.subname(0, "IDLE");
2294 pwrStateTime
.subname(1, "REF");
2295 pwrStateTime
.subname(2, "SREF");
2296 pwrStateTime
.subname(3, "PRE_PDN");
2297 pwrStateTime
.subname(4, "ACT");
2298 pwrStateTime
.subname(5, "ACT_PDN");
2301 .name(name() + ".actEnergy")
2302 .desc("Energy for activate commands per rank (pJ)");
2305 .name(name() + ".preEnergy")
2306 .desc("Energy for precharge commands per rank (pJ)");
2309 .name(name() + ".readEnergy")
2310 .desc("Energy for read commands per rank (pJ)");
2313 .name(name() + ".writeEnergy")
2314 .desc("Energy for write commands per rank (pJ)");
2317 .name(name() + ".refreshEnergy")
2318 .desc("Energy for refresh commands per rank (pJ)");
2321 .name(name() + ".actBackEnergy")
2322 .desc("Energy for active background per rank (pJ)");
2325 .name(name() + ".preBackEnergy")
2326 .desc("Energy for precharge background per rank (pJ)");
2329 .name(name() + ".actPowerDownEnergy")
2330 .desc("Energy for active power-down per rank (pJ)");
2333 .name(name() + ".prePowerDownEnergy")
2334 .desc("Energy for precharge power-down per rank (pJ)");
2337 .name(name() + ".selfRefreshEnergy")
2338 .desc("Energy for self refresh per rank (pJ)");
2341 .name(name() + ".totalEnergy")
2342 .desc("Total energy per rank (pJ)");
2345 .name(name() + ".averagePower")
2346 .desc("Core power per rank (mW)");
2349 .name(name() + ".totalIdleTime")
2350 .desc("Total Idle time Per DRAM Rank");
2352 registerDumpCallback(new RankDumpCallback(this));
2355 DRAMCtrl::regStats()
2357 using namespace Stats
;
2359 AbstractMemory::regStats();
2361 for (auto r
: ranks
) {
2366 .name(name() + ".readReqs")
2367 .desc("Number of read requests accepted");
2370 .name(name() + ".writeReqs")
2371 .desc("Number of write requests accepted");
2374 .name(name() + ".readBursts")
2375 .desc("Number of DRAM read bursts, "
2376 "including those serviced by the write queue");
2379 .name(name() + ".writeBursts")
2380 .desc("Number of DRAM write bursts, "
2381 "including those merged in the write queue");
2384 .name(name() + ".servicedByWrQ")
2385 .desc("Number of DRAM read bursts serviced by the write queue");
2388 .name(name() + ".mergedWrBursts")
2389 .desc("Number of DRAM write bursts merged with an existing one");
2392 .name(name() + ".neitherReadNorWriteReqs")
2393 .desc("Number of requests that are neither read nor write");
2396 .init(banksPerRank
* ranksPerChannel
)
2397 .name(name() + ".perBankRdBursts")
2398 .desc("Per bank write bursts");
2401 .init(banksPerRank
* ranksPerChannel
)
2402 .name(name() + ".perBankWrBursts")
2403 .desc("Per bank write bursts");
2406 .name(name() + ".avgRdQLen")
2407 .desc("Average read queue length when enqueuing")
2411 .name(name() + ".avgWrQLen")
2412 .desc("Average write queue length when enqueuing")
2416 .name(name() + ".totQLat")
2417 .desc("Total ticks spent queuing");
2420 .name(name() + ".totBusLat")
2421 .desc("Total ticks spent in databus transfers");
2424 .name(name() + ".totMemAccLat")
2425 .desc("Total ticks spent from burst creation until serviced "
2429 .name(name() + ".avgQLat")
2430 .desc("Average queueing delay per DRAM burst")
2433 avgQLat
= totQLat
/ (readBursts
- servicedByWrQ
);
2436 .name(name() + ".avgBusLat")
2437 .desc("Average bus latency per DRAM burst")
2440 avgBusLat
= totBusLat
/ (readBursts
- servicedByWrQ
);
2443 .name(name() + ".avgMemAccLat")
2444 .desc("Average memory access latency per DRAM burst")
2447 avgMemAccLat
= totMemAccLat
/ (readBursts
- servicedByWrQ
);
2450 .name(name() + ".numRdRetry")
2451 .desc("Number of times read queue was full causing retry");
2454 .name(name() + ".numWrRetry")
2455 .desc("Number of times write queue was full causing retry");
2458 .name(name() + ".readRowHits")
2459 .desc("Number of row buffer hits during reads");
2462 .name(name() + ".writeRowHits")
2463 .desc("Number of row buffer hits during writes");
2466 .name(name() + ".readRowHitRate")
2467 .desc("Row buffer hit rate for reads")
2470 readRowHitRate
= (readRowHits
/ (readBursts
- servicedByWrQ
)) * 100;
2473 .name(name() + ".writeRowHitRate")
2474 .desc("Row buffer hit rate for writes")
2477 writeRowHitRate
= (writeRowHits
/ (writeBursts
- mergedWrBursts
)) * 100;
2480 .init(ceilLog2(burstSize
) + 1)
2481 .name(name() + ".readPktSize")
2482 .desc("Read request sizes (log2)");
2485 .init(ceilLog2(burstSize
) + 1)
2486 .name(name() + ".writePktSize")
2487 .desc("Write request sizes (log2)");
2490 .init(readBufferSize
)
2491 .name(name() + ".rdQLenPdf")
2492 .desc("What read queue length does an incoming req see");
2495 .init(writeBufferSize
)
2496 .name(name() + ".wrQLenPdf")
2497 .desc("What write queue length does an incoming req see");
2500 .init(maxAccessesPerRow
)
2501 .name(name() + ".bytesPerActivate")
2502 .desc("Bytes accessed per row activation")
2506 .init(readBufferSize
)
2507 .name(name() + ".rdPerTurnAround")
2508 .desc("Reads before turning the bus around for writes")
2512 .init(writeBufferSize
)
2513 .name(name() + ".wrPerTurnAround")
2514 .desc("Writes before turning the bus around for reads")
2518 .name(name() + ".bytesReadDRAM")
2519 .desc("Total number of bytes read from DRAM");
2522 .name(name() + ".bytesReadWrQ")
2523 .desc("Total number of bytes read from write queue");
2526 .name(name() + ".bytesWritten")
2527 .desc("Total number of bytes written to DRAM");
2530 .name(name() + ".bytesReadSys")
2531 .desc("Total read bytes from the system interface side");
2534 .name(name() + ".bytesWrittenSys")
2535 .desc("Total written bytes from the system interface side");
2538 .name(name() + ".avgRdBW")
2539 .desc("Average DRAM read bandwidth in MiByte/s")
2542 avgRdBW
= (bytesReadDRAM
/ 1000000) / simSeconds
;
2545 .name(name() + ".avgWrBW")
2546 .desc("Average achieved write bandwidth in MiByte/s")
2549 avgWrBW
= (bytesWritten
/ 1000000) / simSeconds
;
2552 .name(name() + ".avgRdBWSys")
2553 .desc("Average system read bandwidth in MiByte/s")
2556 avgRdBWSys
= (bytesReadSys
/ 1000000) / simSeconds
;
2559 .name(name() + ".avgWrBWSys")
2560 .desc("Average system write bandwidth in MiByte/s")
2563 avgWrBWSys
= (bytesWrittenSys
/ 1000000) / simSeconds
;
2566 .name(name() + ".peakBW")
2567 .desc("Theoretical peak bandwidth in MiByte/s")
2570 peakBW
= (SimClock::Frequency
/ tBURST
) * burstSize
/ 1000000;
2573 .name(name() + ".busUtil")
2574 .desc("Data bus utilization in percentage")
2576 busUtil
= (avgRdBW
+ avgWrBW
) / peakBW
* 100;
2579 .name(name() + ".totGap")
2580 .desc("Total gap between requests");
2583 .name(name() + ".avgGap")
2584 .desc("Average gap between requests")
2587 avgGap
= totGap
/ (readReqs
+ writeReqs
);
2589 // Stats for DRAM Power calculation based on Micron datasheet
2591 .name(name() + ".busUtilRead")
2592 .desc("Data bus utilization in percentage for reads")
2595 busUtilRead
= avgRdBW
/ peakBW
* 100;
2598 .name(name() + ".busUtilWrite")
2599 .desc("Data bus utilization in percentage for writes")
2602 busUtilWrite
= avgWrBW
/ peakBW
* 100;
2605 .name(name() + ".pageHitRate")
2606 .desc("Row buffer hit rate, read and write combined")
2609 pageHitRate
= (writeRowHits
+ readRowHits
) /
2610 (writeBursts
- mergedWrBursts
+ readBursts
- servicedByWrQ
) * 100;
2614 DRAMCtrl::recvFunctional(PacketPtr pkt
)
2616 // rely on the abstract memory
2617 functionalAccess(pkt
);
2621 DRAMCtrl::getSlavePort(const string
&if_name
, PortID idx
)
2623 if (if_name
!= "port") {
2624 return MemObject::getSlavePort(if_name
, idx
);
2633 // if there is anything in any of our internal queues, keep track
2635 if (!(writeQueue
.empty() && readQueue
.empty() && respQueue
.empty() &&
2636 allRanksDrained())) {
2638 DPRINTF(Drain
, "DRAM controller not drained, write: %d, read: %d,"
2639 " resp: %d\n", writeQueue
.size(), readQueue
.size(),
2642 // the only queue that is not drained automatically over time
2643 // is the write queue, thus kick things into action if needed
2644 if (!writeQueue
.empty() && !nextReqEvent
.scheduled()) {
2645 schedule(nextReqEvent
, curTick());
2648 // also need to kick off events to exit self-refresh
2649 for (auto r
: ranks
) {
2650 // force self-refresh exit, which in turn will issue auto-refresh
2651 if (r
->pwrState
== PWR_SREF
) {
2652 DPRINTF(DRAM
,"Rank%d: Forcing self-refresh wakeup in drain\n",
2654 r
->scheduleWakeUpEvent(tXS
);
2658 return DrainState::Draining
;
2660 return DrainState::Drained
;
2665 DRAMCtrl::allRanksDrained() const
2667 // true until proven false
2668 bool all_ranks_drained
= true;
2669 for (auto r
: ranks
) {
2670 // then verify that the power state is IDLE
2671 // ensuring all banks are closed and rank is not in a low power state
2672 all_ranks_drained
= r
->inPwrIdleState() && all_ranks_drained
;
2674 return all_ranks_drained
;
2678 DRAMCtrl::drainResume()
2680 if (!isTimingMode
&& system()->isTimingMode()) {
2681 // if we switched to timing mode, kick things into action,
2682 // and behave as if we restored from a checkpoint
2684 } else if (isTimingMode
&& !system()->isTimingMode()) {
2685 // if we switch from timing mode, stop the refresh events to
2686 // not cause issues with KVM
2687 for (auto r
: ranks
) {
2693 isTimingMode
= system()->isTimingMode();
2696 DRAMCtrl::MemoryPort::MemoryPort(const std::string
& name
, DRAMCtrl
& _memory
)
2697 : QueuedSlavePort(name
, &_memory
, queue
), queue(_memory
, *this),
2702 DRAMCtrl::MemoryPort::getAddrRanges() const
2704 AddrRangeList ranges
;
2705 ranges
.push_back(memory
.getAddrRange());
2710 DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt
)
2712 pkt
->pushLabel(memory
.name());
2714 if (!queue
.checkFunctional(pkt
)) {
2715 // Default implementation of SimpleTimingPort::recvFunctional()
2716 // calls recvAtomic() and throws away the latency; we can save a
2717 // little here by just not calculating the latency.
2718 memory
.recvFunctional(pkt
);
2725 DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt
)
2727 return memory
.recvAtomic(pkt
);
2731 DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt
)
2733 // pass it to the memory controller
2734 return memory
.recvTimingReq(pkt
);
2738 DRAMCtrlParams::create()
2740 return new DRAMCtrl(this);