2 * Copyright (c) 2010-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
45 #include "base/bitfield.hh"
46 #include "base/trace.hh"
47 #include "debug/DRAM.hh"
48 #include "debug/Drain.hh"
49 #include "mem/dram_ctrl.hh"
50 #include "sim/system.hh"
54 DRAMCtrl::DRAMCtrl(const DRAMCtrlParams
* p
) :
56 port(name() + ".port", *this),
57 retryRdReq(false), retryWrReq(false),
58 rowHitFlag(false), busState(READ
),
60 refreshEvent(this), nextReqEvent(this), drainManager(NULL
),
61 deviceBusWidth(p
->device_bus_width
), burstLength(p
->burst_length
),
62 deviceRowBufferSize(p
->device_rowbuffer_size
),
63 devicesPerRank(p
->devices_per_rank
),
64 burstSize((devicesPerRank
* burstLength
* deviceBusWidth
) / 8),
65 rowBufferSize(devicesPerRank
* deviceRowBufferSize
),
66 columnsPerRowBuffer(rowBufferSize
/ burstSize
),
67 ranksPerChannel(p
->ranks_per_channel
),
68 banksPerRank(p
->banks_per_rank
), channels(p
->channels
), rowsPerBank(0),
69 readBufferSize(p
->read_buffer_size
),
70 writeBufferSize(p
->write_buffer_size
),
71 writeHighThreshold(writeBufferSize
* p
->write_high_thresh_perc
/ 100.0),
72 writeLowThreshold(writeBufferSize
* p
->write_low_thresh_perc
/ 100.0),
73 minWritesPerSwitch(p
->min_writes_per_switch
),
74 writesThisTime(0), readsThisTime(0),
75 tWTR(p
->tWTR
), tRTW(p
->tRTW
), tBURST(p
->tBURST
),
76 tRCD(p
->tRCD
), tCL(p
->tCL
), tRP(p
->tRP
), tRAS(p
->tRAS
),
77 tRFC(p
->tRFC
), tREFI(p
->tREFI
), tRRD(p
->tRRD
),
78 tXAW(p
->tXAW
), activationLimit(p
->activation_limit
),
79 memSchedPolicy(p
->mem_sched_policy
), addrMapping(p
->addr_mapping
),
80 pageMgmt(p
->page_policy
),
81 maxAccessesPerRow(p
->max_accesses_per_row
),
82 frontendLatency(p
->static_frontend_latency
),
83 backendLatency(p
->static_backend_latency
),
84 busBusyUntil(0), prevArrival(0),
85 nextReqTime(0), startTickPrechargeAll(0), numBanksActive(0)
87 // create the bank states based on the dimensions of the ranks and
89 banks
.resize(ranksPerChannel
);
90 actTicks
.resize(ranksPerChannel
);
91 for (size_t c
= 0; c
< ranksPerChannel
; ++c
) {
92 banks
[c
].resize(banksPerRank
);
93 actTicks
[c
].resize(activationLimit
, 0);
96 // perform a basic check of the write thresholds
97 if (p
->write_low_thresh_perc
>= p
->write_high_thresh_perc
)
98 fatal("Write buffer low threshold %d must be smaller than the "
99 "high threshold %d\n", p
->write_low_thresh_perc
,
100 p
->write_high_thresh_perc
);
102 // determine the rows per bank by looking at the total capacity
103 uint64_t capacity
= ULL(1) << ceilLog2(AbstractMemory::size());
105 DPRINTF(DRAM
, "Memory capacity %lld (%lld) bytes\n", capacity
,
106 AbstractMemory::size());
108 DPRINTF(DRAM
, "Row buffer size %d bytes with %d columns per row buffer\n",
109 rowBufferSize
, columnsPerRowBuffer
);
111 rowsPerBank
= capacity
/ (rowBufferSize
* banksPerRank
* ranksPerChannel
);
113 if (range
.interleaved()) {
114 if (channels
!= range
.stripes())
115 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
116 name(), range
.stripes(), channels
);
118 if (addrMapping
== Enums::RoRaBaChCo
) {
119 if (rowBufferSize
!= range
.granularity()) {
120 fatal("Interleaving of %s doesn't match RoRaBaChCo "
121 "address map\n", name());
123 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
124 if (system()->cacheLineSize() != range
.granularity()) {
125 fatal("Interleaving of %s doesn't match RoRaBaCoCh "
126 "address map\n", name());
128 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
129 if (system()->cacheLineSize() != range
.granularity())
130 fatal("Interleaving of %s doesn't match RoCoRaBaCh "
131 "address map\n", name());
139 if (!port
.isConnected()) {
140 fatal("DRAMCtrl %s is unconnected!\n", name());
142 port
.sendRangeChange();
149 // update the start tick for the precharge accounting to the
151 startTickPrechargeAll
= curTick();
153 // shift the bus busy time sufficiently far ahead that we never
154 // have to worry about negative values when computing the time for
155 // the next request, this will add an insignificant bubble at the
156 // start of simulation
157 busBusyUntil
= curTick() + tRP
+ tRCD
+ tCL
;
159 // print the configuration of the controller
162 // kick off the refresh
163 schedule(refreshEvent
, curTick() + tREFI
);
167 DRAMCtrl::recvAtomic(PacketPtr pkt
)
169 DPRINTF(DRAM
, "recvAtomic: %s 0x%x\n", pkt
->cmdString(), pkt
->getAddr());
171 // do the actual memory access and turn the packet into a response
175 if (!pkt
->memInhibitAsserted() && pkt
->hasData()) {
176 // this value is not supposed to be accurate, just enough to
177 // keep things going, mimic a closed page
178 latency
= tRP
+ tRCD
+ tCL
;
184 DRAMCtrl::readQueueFull(unsigned int neededEntries
) const
186 DPRINTF(DRAM
, "Read queue limit %d, current size %d, entries needed %d\n",
187 readBufferSize
, readQueue
.size() + respQueue
.size(),
191 (readQueue
.size() + respQueue
.size() + neededEntries
) > readBufferSize
;
195 DRAMCtrl::writeQueueFull(unsigned int neededEntries
) const
197 DPRINTF(DRAM
, "Write queue limit %d, current size %d, entries needed %d\n",
198 writeBufferSize
, writeQueue
.size(), neededEntries
);
199 return (writeQueue
.size() + neededEntries
) > writeBufferSize
;
202 DRAMCtrl::DRAMPacket
*
203 DRAMCtrl::decodeAddr(PacketPtr pkt
, Addr dramPktAddr
, unsigned size
,
206 // decode the address based on the address mapping scheme, with
207 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
208 // channel, respectively
213 // truncate the address to the access granularity
214 Addr addr
= dramPktAddr
/ burstSize
;
216 // we have removed the lowest order address bits that denote the
217 // position within the column
218 if (addrMapping
== Enums::RoRaBaChCo
) {
219 // the lowest order bits denote the column to ensure that
220 // sequential cache lines occupy the same row
221 addr
= addr
/ columnsPerRowBuffer
;
223 // take out the channel part of the address
224 addr
= addr
/ channels
;
226 // after the channel bits, get the bank bits to interleave
228 bank
= addr
% banksPerRank
;
229 addr
= addr
/ banksPerRank
;
231 // after the bank, we get the rank bits which thus interleaves
233 rank
= addr
% ranksPerChannel
;
234 addr
= addr
/ ranksPerChannel
;
236 // lastly, get the row bits
237 row
= addr
% rowsPerBank
;
238 addr
= addr
/ rowsPerBank
;
239 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
240 // take out the channel part of the address
241 addr
= addr
/ channels
;
244 addr
= addr
/ columnsPerRowBuffer
;
246 // after the column bits, we get the bank bits to interleave
248 bank
= addr
% banksPerRank
;
249 addr
= addr
/ banksPerRank
;
251 // after the bank, we get the rank bits which thus interleaves
253 rank
= addr
% ranksPerChannel
;
254 addr
= addr
/ ranksPerChannel
;
256 // lastly, get the row bits
257 row
= addr
% rowsPerBank
;
258 addr
= addr
/ rowsPerBank
;
259 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
260 // optimise for closed page mode and utilise maximum
261 // parallelism of the DRAM (at the cost of power)
263 // take out the channel part of the address, not that this has
264 // to match with how accesses are interleaved between the
265 // controllers in the address mapping
266 addr
= addr
/ channels
;
268 // start with the bank bits, as this provides the maximum
269 // opportunity for parallelism between requests
270 bank
= addr
% banksPerRank
;
271 addr
= addr
/ banksPerRank
;
273 // next get the rank bits
274 rank
= addr
% ranksPerChannel
;
275 addr
= addr
/ ranksPerChannel
;
277 // next the column bits which we do not need to keep track of
278 // and simply skip past
279 addr
= addr
/ columnsPerRowBuffer
;
281 // lastly, get the row bits
282 row
= addr
% rowsPerBank
;
283 addr
= addr
/ rowsPerBank
;
285 panic("Unknown address mapping policy chosen!");
287 assert(rank
< ranksPerChannel
);
288 assert(bank
< banksPerRank
);
289 assert(row
< rowsPerBank
);
291 DPRINTF(DRAM
, "Address: %lld Rank %d Bank %d Row %d\n",
292 dramPktAddr
, rank
, bank
, row
);
294 // create the corresponding DRAM packet with the entry time and
295 // ready time set to the current tick, the latter will be updated
297 uint16_t bank_id
= banksPerRank
* rank
+ bank
;
298 return new DRAMPacket(pkt
, isRead
, rank
, bank
, row
, bank_id
, dramPktAddr
,
299 size
, banks
[rank
][bank
]);
303 DRAMCtrl::addToReadQueue(PacketPtr pkt
, unsigned int pktCount
)
305 // only add to the read queue here. whenever the request is
306 // eventually done, set the readyTime, and call schedule()
307 assert(!pkt
->isWrite());
309 assert(pktCount
!= 0);
311 // if the request size is larger than burst size, the pkt is split into
312 // multiple DRAM packets
313 // Note if the pkt starting address is not aligened to burst size, the
314 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
315 // are aligned to burst size boundaries. This is to ensure we accurately
316 // check read packets against packets in write queue.
317 Addr addr
= pkt
->getAddr();
318 unsigned pktsServicedByWrQ
= 0;
319 BurstHelper
* burst_helper
= NULL
;
320 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
321 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
322 pkt
->getAddr() + pkt
->getSize()) - addr
;
323 readPktSize
[ceilLog2(size
)]++;
326 // First check write buffer to see if the data is already at
328 bool foundInWrQ
= false;
329 for (auto i
= writeQueue
.begin(); i
!= writeQueue
.end(); ++i
) {
330 // check if the read is subsumed in the write entry we are
332 if ((*i
)->addr
<= addr
&&
333 (addr
+ size
) <= ((*i
)->addr
+ (*i
)->size
)) {
337 DPRINTF(DRAM
, "Read to addr %lld with size %d serviced by "
338 "write queue\n", addr
, size
);
339 bytesReadWrQ
+= burstSize
;
344 // If not found in the write q, make a DRAM packet and
345 // push it onto the read queue
348 // Make the burst helper for split packets
349 if (pktCount
> 1 && burst_helper
== NULL
) {
350 DPRINTF(DRAM
, "Read to addr %lld translates to %d "
351 "dram requests\n", pkt
->getAddr(), pktCount
);
352 burst_helper
= new BurstHelper(pktCount
);
355 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, true);
356 dram_pkt
->burstHelper
= burst_helper
;
358 assert(!readQueueFull(1));
359 rdQLenPdf
[readQueue
.size() + respQueue
.size()]++;
361 DPRINTF(DRAM
, "Adding to read queue\n");
363 readQueue
.push_back(dram_pkt
);
366 avgRdQLen
= readQueue
.size() + respQueue
.size();
369 // Starting address of next dram pkt (aligend to burstSize boundary)
370 addr
= (addr
| (burstSize
- 1)) + 1;
373 // If all packets are serviced by write queue, we send the repsonse back
374 if (pktsServicedByWrQ
== pktCount
) {
375 accessAndRespond(pkt
, frontendLatency
);
379 // Update how many split packets are serviced by write queue
380 if (burst_helper
!= NULL
)
381 burst_helper
->burstsServiced
= pktsServicedByWrQ
;
383 // If we are not already scheduled to get a request out of the
385 if (!nextReqEvent
.scheduled()) {
386 DPRINTF(DRAM
, "Request scheduled immediately\n");
387 schedule(nextReqEvent
, curTick());
392 DRAMCtrl::addToWriteQueue(PacketPtr pkt
, unsigned int pktCount
)
394 // only add to the write queue here. whenever the request is
395 // eventually done, set the readyTime, and call schedule()
396 assert(pkt
->isWrite());
398 // if the request size is larger than burst size, the pkt is split into
399 // multiple DRAM packets
400 Addr addr
= pkt
->getAddr();
401 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
402 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
403 pkt
->getAddr() + pkt
->getSize()) - addr
;
404 writePktSize
[ceilLog2(size
)]++;
407 // see if we can merge with an existing item in the write
408 // queue and keep track of whether we have merged or not so we
409 // can stop at that point and also avoid enqueueing a new
412 auto w
= writeQueue
.begin();
414 while(!merged
&& w
!= writeQueue
.end()) {
415 // either of the two could be first, if they are the same
416 // it does not matter which way we go
417 if ((*w
)->addr
>= addr
) {
418 // the existing one starts after the new one, figure
419 // out where the new one ends with respect to the
421 if ((addr
+ size
) >= ((*w
)->addr
+ (*w
)->size
)) {
422 // check if the existing one is completely
423 // subsumed in the new one
424 DPRINTF(DRAM
, "Merging write covering existing burst\n");
426 // update both the address and the size
429 } else if ((addr
+ size
) >= (*w
)->addr
&&
430 ((*w
)->addr
+ (*w
)->size
- addr
) <= burstSize
) {
431 // the new one is just before or partially
432 // overlapping with the existing one, and together
433 // they fit within a burst
434 DPRINTF(DRAM
, "Merging write before existing burst\n");
436 // the existing queue item needs to be adjusted with
437 // respect to both address and size
438 (*w
)->size
= (*w
)->addr
+ (*w
)->size
- addr
;
442 // the new one starts after the current one, figure
443 // out where the existing one ends with respect to the
445 if (((*w
)->addr
+ (*w
)->size
) >= (addr
+ size
)) {
446 // check if the new one is completely subsumed in the
448 DPRINTF(DRAM
, "Merging write into existing burst\n");
450 // no adjustments necessary
451 } else if (((*w
)->addr
+ (*w
)->size
) >= addr
&&
452 (addr
+ size
- (*w
)->addr
) <= burstSize
) {
453 // the existing one is just before or partially
454 // overlapping with the new one, and together
455 // they fit within a burst
456 DPRINTF(DRAM
, "Merging write after existing burst\n");
458 // the address is right, and only the size has
460 (*w
)->size
= addr
+ size
- (*w
)->addr
;
466 // if the item was not merged we need to create a new write
469 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, false);
471 assert(writeQueue
.size() < writeBufferSize
);
472 wrQLenPdf
[writeQueue
.size()]++;
474 DPRINTF(DRAM
, "Adding to write queue\n");
476 writeQueue
.push_back(dram_pkt
);
479 avgWrQLen
= writeQueue
.size();
481 // keep track of the fact that this burst effectively
482 // disappeared as it was merged with an existing one
486 // Starting address of next dram pkt (aligend to burstSize boundary)
487 addr
= (addr
| (burstSize
- 1)) + 1;
490 // we do not wait for the writes to be send to the actual memory,
491 // but instead take responsibility for the consistency here and
492 // snoop the write queue for any upcoming reads
493 // @todo, if a pkt size is larger than burst size, we might need a
494 // different front end latency
495 accessAndRespond(pkt
, frontendLatency
);
497 // If we are not already scheduled to get a request out of the
499 if (!nextReqEvent
.scheduled()) {
500 DPRINTF(DRAM
, "Request scheduled immediately\n");
501 schedule(nextReqEvent
, curTick());
506 DRAMCtrl::printParams() const
508 // Sanity check print of important parameters
510 "Memory controller %s physical organization\n" \
511 "Number of devices per rank %d\n" \
512 "Device bus width (in bits) %d\n" \
513 "DRAM data bus burst (bytes) %d\n" \
514 "Row buffer size (bytes) %d\n" \
515 "Columns per row buffer %d\n" \
516 "Rows per bank %d\n" \
517 "Banks per rank %d\n" \
518 "Ranks per channel %d\n" \
519 "Total mem capacity (bytes) %u\n",
520 name(), devicesPerRank
, deviceBusWidth
, burstSize
, rowBufferSize
,
521 columnsPerRowBuffer
, rowsPerBank
, banksPerRank
, ranksPerChannel
,
522 rowBufferSize
* rowsPerBank
* banksPerRank
* ranksPerChannel
);
524 string scheduler
= memSchedPolicy
== Enums::fcfs
? "FCFS" : "FR-FCFS";
525 string address_mapping
= addrMapping
== Enums::RoRaBaChCo
? "RoRaBaChCo" :
526 (addrMapping
== Enums::RoRaBaCoCh
? "RoRaBaCoCh" : "RoCoRaBaCh");
527 string page_policy
= pageMgmt
== Enums::open
? "OPEN" :
528 (pageMgmt
== Enums::open_adaptive
? "OPEN (adaptive)" :
529 (pageMgmt
== Enums::close_adaptive
? "CLOSE (adaptive)" : "CLOSE"));
532 "Memory controller %s characteristics\n" \
533 "Read buffer size %d\n" \
534 "Write buffer size %d\n" \
535 "Write high thresh %d\n" \
536 "Write low thresh %d\n" \
538 "Address mapping %s\n" \
540 name(), readBufferSize
, writeBufferSize
, writeHighThreshold
,
541 writeLowThreshold
, scheduler
, address_mapping
, page_policy
);
543 DPRINTF(DRAM
, "Memory controller %s timing specs\n" \
547 "tBURST %d ticks\n" \
552 "tXAW (%d) %d ticks\n",
553 name(), tRCD
, tCL
, tRP
, tBURST
, tRFC
, tREFI
, tWTR
,
554 tRTW
, activationLimit
, tXAW
);
558 DRAMCtrl::printQs() const {
559 DPRINTF(DRAM
, "===READ QUEUE===\n\n");
560 for (auto i
= readQueue
.begin() ; i
!= readQueue
.end() ; ++i
) {
561 DPRINTF(DRAM
, "Read %lu\n", (*i
)->addr
);
563 DPRINTF(DRAM
, "\n===RESP QUEUE===\n\n");
564 for (auto i
= respQueue
.begin() ; i
!= respQueue
.end() ; ++i
) {
565 DPRINTF(DRAM
, "Response %lu\n", (*i
)->addr
);
567 DPRINTF(DRAM
, "\n===WRITE QUEUE===\n\n");
568 for (auto i
= writeQueue
.begin() ; i
!= writeQueue
.end() ; ++i
) {
569 DPRINTF(DRAM
, "Write %lu\n", (*i
)->addr
);
574 DRAMCtrl::recvTimingReq(PacketPtr pkt
)
576 /// @todo temporary hack to deal with memory corruption issues until
577 /// 4-phase transactions are complete
578 for (int x
= 0; x
< pendingDelete
.size(); x
++)
579 delete pendingDelete
[x
];
580 pendingDelete
.clear();
582 // This is where we enter from the outside world
583 DPRINTF(DRAM
, "recvTimingReq: request %s addr %lld size %d\n",
584 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
586 // simply drop inhibited packets for now
587 if (pkt
->memInhibitAsserted()) {
588 DPRINTF(DRAM
, "Inhibited packet -- Dropping it now\n");
589 pendingDelete
.push_back(pkt
);
593 // Calc avg gap between requests
594 if (prevArrival
!= 0) {
595 totGap
+= curTick() - prevArrival
;
597 prevArrival
= curTick();
600 // Find out how many dram packets a pkt translates to
601 // If the burst size is equal or larger than the pkt size, then a pkt
602 // translates to only one dram packet. Otherwise, a pkt translates to
603 // multiple dram packets
604 unsigned size
= pkt
->getSize();
605 unsigned offset
= pkt
->getAddr() & (burstSize
- 1);
606 unsigned int dram_pkt_count
= divCeil(offset
+ size
, burstSize
);
608 // check local buffers and do not accept if full
611 if (readQueueFull(dram_pkt_count
)) {
612 DPRINTF(DRAM
, "Read queue full, not accepting\n");
613 // remember that we have to retry this port
618 addToReadQueue(pkt
, dram_pkt_count
);
620 bytesReadSys
+= size
;
622 } else if (pkt
->isWrite()) {
624 if (writeQueueFull(dram_pkt_count
)) {
625 DPRINTF(DRAM
, "Write queue full, not accepting\n");
626 // remember that we have to retry this port
631 addToWriteQueue(pkt
, dram_pkt_count
);
633 bytesWrittenSys
+= size
;
636 DPRINTF(DRAM
,"Neither read nor write, ignore timing\n");
637 neitherReadNorWrite
++;
638 accessAndRespond(pkt
, 1);
645 DRAMCtrl::processRespondEvent()
648 "processRespondEvent(): Some req has reached its readyTime\n");
650 DRAMPacket
* dram_pkt
= respQueue
.front();
652 if (dram_pkt
->burstHelper
) {
653 // it is a split packet
654 dram_pkt
->burstHelper
->burstsServiced
++;
655 if (dram_pkt
->burstHelper
->burstsServiced
==
656 dram_pkt
->burstHelper
->burstCount
) {
657 // we have now serviced all children packets of a system packet
658 // so we can now respond to the requester
659 // @todo we probably want to have a different front end and back
660 // end latency for split packets
661 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
662 delete dram_pkt
->burstHelper
;
663 dram_pkt
->burstHelper
= NULL
;
666 // it is not a split packet
667 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
670 delete respQueue
.front();
671 respQueue
.pop_front();
673 if (!respQueue
.empty()) {
674 assert(respQueue
.front()->readyTime
>= curTick());
675 assert(!respondEvent
.scheduled());
676 schedule(respondEvent
, respQueue
.front()->readyTime
);
678 // if there is nothing left in any queue, signal a drain
679 if (writeQueue
.empty() && readQueue
.empty() &&
681 drainManager
->signalDrainDone();
686 // We have made a location in the queue available at this point,
687 // so if there is a read that was forced to wait, retry now
695 DRAMCtrl::chooseNext(std::deque
<DRAMPacket
*>& queue
)
697 // This method does the arbitration between requests. The chosen
698 // packet is simply moved to the head of the queue. The other
699 // methods know that this is the place to look. For example, with
700 // FCFS, this method does nothing
701 assert(!queue
.empty());
703 if (queue
.size() == 1) {
704 DPRINTF(DRAM
, "Single request, nothing to do\n");
708 if (memSchedPolicy
== Enums::fcfs
) {
709 // Do nothing, since the correct request is already head
710 } else if (memSchedPolicy
== Enums::frfcfs
) {
713 panic("No scheduling policy chosen\n");
717 DRAMCtrl::reorderQueue(std::deque
<DRAMPacket
*>& queue
)
719 // Only determine this when needed
720 uint64_t earliest_banks
= 0;
722 // Search for row hits first, if no row hit is found then schedule the
723 // packet to one of the earliest banks available
724 bool found_earliest_pkt
= false;
725 auto selected_pkt_it
= queue
.begin();
727 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
728 DRAMPacket
* dram_pkt
= *i
;
729 const Bank
& bank
= dram_pkt
->bankRef
;
730 // Check if it is a row hit
731 if (bank
.openRow
== dram_pkt
->row
) {
732 DPRINTF(DRAM
, "Row buffer hit\n");
735 } else if (!found_earliest_pkt
) {
736 // No row hit, go for first ready
737 if (earliest_banks
== 0)
738 earliest_banks
= minBankFreeAt(queue
);
740 // Bank is ready or is the first available bank
741 if (bank
.freeAt
<= curTick() ||
742 bits(earliest_banks
, dram_pkt
->bankId
, dram_pkt
->bankId
)) {
743 // Remember the packet to be scheduled to one of the earliest
746 found_earliest_pkt
= true;
751 DRAMPacket
* selected_pkt
= *selected_pkt_it
;
752 queue
.erase(selected_pkt_it
);
753 queue
.push_front(selected_pkt
);
757 DRAMCtrl::accessAndRespond(PacketPtr pkt
, Tick static_latency
)
759 DPRINTF(DRAM
, "Responding to Address %lld.. ",pkt
->getAddr());
761 bool needsResponse
= pkt
->needsResponse();
762 // do the actual memory access which also turns the packet into a
766 // turn packet around to go back to requester if response expected
768 // access already turned the packet into a response
769 assert(pkt
->isResponse());
771 // @todo someone should pay for this
772 pkt
->busFirstWordDelay
= pkt
->busLastWordDelay
= 0;
774 // queue the packet in the response queue to be sent out after
775 // the static latency has passed
776 port
.schedTimingResp(pkt
, curTick() + static_latency
);
778 // @todo the packet is going to be deleted, and the DRAMPacket
779 // is still having a pointer to it
780 pendingDelete
.push_back(pkt
);
783 DPRINTF(DRAM
, "Done\n");
789 DRAMCtrl::estimateLatency(DRAMPacket
* dram_pkt
, Tick inTime
)
791 // If a request reaches a bank at tick 'inTime', how much time
792 // *after* that does it take to finish the request, depending
793 // on bank status and page open policy. Note that this method
794 // considers only the time taken for the actual read or write
795 // to complete, NOT any additional time thereafter for tRAS or
800 Tick potentialActTick
;
802 const Bank
& bank
= dram_pkt
->bankRef
;
803 // open-page policy or close_adaptive policy
804 if (pageMgmt
== Enums::open
|| pageMgmt
== Enums::open_adaptive
||
805 pageMgmt
== Enums::close_adaptive
) {
806 if (bank
.openRow
== dram_pkt
->row
) {
807 // When we have a row-buffer hit,
808 // we don't care about tRAS having expired or not,
809 // but do care about bank being free for access
812 // When a series of requests arrive to the same row,
813 // DDR systems are capable of streaming data continuously
814 // at maximum bandwidth (subject to tCCD). Here, we approximate
815 // this condition, and assume that if whenever a bank is already
816 // busy and a new request comes in, it can be completed with no
817 // penalty beyond waiting for the existing read to complete.
818 if (bank
.freeAt
> inTime
) {
819 accLat
+= bank
.freeAt
- inTime
;
828 // Row-buffer miss, need to close existing row
829 // once tRAS has expired, then open the new one,
830 // then add cas latency.
831 Tick freeTime
= std::max(bank
.tRASDoneAt
, bank
.freeAt
);
833 if (freeTime
> inTime
)
834 accLat
+= freeTime
- inTime
;
836 // If the there is no open row (open adaptive), then there
837 // is no precharge delay, otherwise go with tRP
838 Tick precharge_delay
= bank
.openRow
== -1 ? 0 : tRP
;
840 //The bank is free, and you may be able to activate
841 potentialActTick
= inTime
+ accLat
+ precharge_delay
;
842 if (potentialActTick
< bank
.actAllowedAt
)
843 accLat
+= bank
.actAllowedAt
- potentialActTick
;
845 accLat
+= precharge_delay
+ tRCD
+ tCL
;
846 bankLat
+= precharge_delay
+ tRCD
+ tCL
;
848 } else if (pageMgmt
== Enums::close
) {
849 // With a close page policy, no notion of
851 if (bank
.freeAt
> inTime
)
852 accLat
+= bank
.freeAt
- inTime
;
854 //The bank is free, and you may be able to activate
855 potentialActTick
= inTime
+ accLat
;
856 if (potentialActTick
< bank
.actAllowedAt
)
857 accLat
+= bank
.actAllowedAt
- potentialActTick
;
859 // page already closed, simply open the row, and
861 accLat
+= tRCD
+ tCL
;
862 bankLat
+= tRCD
+ tCL
;
864 panic("No page management policy chosen\n");
866 DPRINTF(DRAM
, "Returning < %lld, %lld > from estimateLatency()\n",
869 return make_pair(bankLat
, accLat
);
873 DRAMCtrl::recordActivate(Tick act_tick
, uint8_t rank
, uint8_t bank
)
875 assert(0 <= rank
&& rank
< ranksPerChannel
);
876 assert(actTicks
[rank
].size() == activationLimit
);
878 DPRINTF(DRAM
, "Activate at tick %d\n", act_tick
);
880 // Tracking accesses after all banks are precharged.
881 // startTickPrechargeAll: is the tick when all the banks were again
882 // precharged. The difference between act_tick and startTickPrechargeAll
883 // gives the time for which DRAM doesn't get any accesses after refreshing
884 // or after a page is closed in closed-page or open-adaptive-page policy.
885 if ((numBanksActive
== 0) && (act_tick
> startTickPrechargeAll
)) {
886 prechargeAllTime
+= act_tick
- startTickPrechargeAll
;
889 // No need to update number of active banks for closed-page policy as only 1
890 // bank will be activated at any given point, which will be instatntly
892 if (pageMgmt
== Enums::open
|| pageMgmt
== Enums::open_adaptive
||
893 pageMgmt
== Enums::close_adaptive
)
896 // start by enforcing tRRD
897 for(int i
= 0; i
< banksPerRank
; i
++) {
898 // next activate must not happen before tRRD
899 banks
[rank
][i
].actAllowedAt
= act_tick
+ tRRD
;
901 // tRC should be added to activation tick of the bank currently accessed,
902 // where tRC = tRAS + tRP, this is just for a check as actAllowedAt for same
903 // bank is already captured by bank.freeAt and bank.tRASDoneAt
904 banks
[rank
][bank
].actAllowedAt
= act_tick
+ tRAS
+ tRP
;
906 // next, we deal with tXAW, if the activation limit is disabled
908 if (actTicks
[rank
].empty())
912 if (actTicks
[rank
].back() && (act_tick
- actTicks
[rank
].back()) < tXAW
) {
913 // @todo For now, stick with a warning
914 warn("Got %d activates in window %d (%d - %d) which is smaller "
915 "than %d\n", activationLimit
, act_tick
- actTicks
[rank
].back(),
916 act_tick
, actTicks
[rank
].back(), tXAW
);
919 // shift the times used for the book keeping, the last element
920 // (highest index) is the oldest one and hence the lowest value
921 actTicks
[rank
].pop_back();
923 // record an new activation (in the future)
924 actTicks
[rank
].push_front(act_tick
);
926 // cannot activate more than X times in time window tXAW, push the
927 // next one (the X + 1'st activate) to be tXAW away from the
928 // oldest in our window of X
929 if (actTicks
[rank
].back() && (act_tick
- actTicks
[rank
].back()) < tXAW
) {
930 DPRINTF(DRAM
, "Enforcing tXAW with X = %d, next activate no earlier "
931 "than %d\n", activationLimit
, actTicks
[rank
].back() + tXAW
);
932 for(int j
= 0; j
< banksPerRank
; j
++)
933 // next activate must not happen before end of window
934 banks
[rank
][j
].actAllowedAt
= actTicks
[rank
].back() + tXAW
;
939 DRAMCtrl::doDRAMAccess(DRAMPacket
* dram_pkt
)
942 DPRINTF(DRAM
, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
943 dram_pkt
->addr
, dram_pkt
->rank
, dram_pkt
->bank
, dram_pkt
->row
);
945 // estimate the bank and access latency
946 pair
<Tick
, Tick
> lat
= estimateLatency(dram_pkt
, curTick());
947 Tick bankLat
= lat
.first
;
948 Tick accessLat
= lat
.second
;
951 // This request was woken up at this time based on a prior call
952 // to estimateLatency(). However, between then and now, both the
953 // accessLatency and/or busBusyUntil may have changed. We need
954 // to correct for that.
956 Tick addDelay
= (curTick() + accessLat
< busBusyUntil
) ?
957 busBusyUntil
- (curTick() + accessLat
) : 0;
959 Bank
& bank
= dram_pkt
->bankRef
;
962 if (pageMgmt
== Enums::open
|| pageMgmt
== Enums::open_adaptive
||
963 pageMgmt
== Enums::close_adaptive
) {
964 bank
.freeAt
= curTick() + addDelay
+ accessLat
;
966 // If you activated a new row do to this access, the next access
967 // will have to respect tRAS for this bank.
969 // any waiting for banks account for in freeAt
970 actTick
= bank
.freeAt
- tCL
- tRCD
;
971 bank
.tRASDoneAt
= actTick
+ tRAS
;
972 recordActivate(actTick
, dram_pkt
->rank
, dram_pkt
->bank
);
974 // if we closed an open row as a result of this access,
975 // then sample the number of bytes accessed before
977 if (bank
.openRow
!= -1)
978 bytesPerActivate
.sample(bank
.bytesAccessed
);
980 // update the open row
981 bank
.openRow
= dram_pkt
->row
;
983 // start counting anew, this covers both the case when we
984 // auto-precharged, and when this access is forced to
986 bank
.bytesAccessed
= 0;
987 bank
.rowAccesses
= 0;
990 // increment the bytes accessed and the accesses per row
991 bank
.bytesAccessed
+= burstSize
;
994 // if we reached the max, then issue with an auto-precharge
995 bool auto_precharge
= bank
.rowAccesses
== maxAccessesPerRow
;
997 // if we did not hit the limit, we might still want to
999 if (!auto_precharge
&&
1000 (pageMgmt
== Enums::open_adaptive
||
1001 pageMgmt
== Enums::close_adaptive
)) {
1002 // a twist on the open and close page policies:
1003 // 1) open_adaptive page policy does not blindly keep the
1004 // page open, but close it if there are no row hits, and there
1005 // are bank conflicts in the queue
1006 // 2) close_adaptive page policy does not blindly close the
1007 // page, but closes it only if there are no row hits in the queue.
1008 // In this case, only force an auto precharge when there
1009 // are no same page hits in the queue
1010 bool got_more_hits
= false;
1011 bool got_bank_conflict
= false;
1013 // either look at the read queue or write queue
1014 const deque
<DRAMPacket
*>& queue
= dram_pkt
->isRead
? readQueue
:
1016 auto p
= queue
.begin();
1017 // make sure we are not considering the packet that we are
1018 // currently dealing with (which is the head of the queue)
1021 // keep on looking until we have found required condition or
1023 while (!(got_more_hits
&&
1024 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
)) &&
1026 bool same_rank_bank
= (dram_pkt
->rank
== (*p
)->rank
) &&
1027 (dram_pkt
->bank
== (*p
)->bank
);
1028 bool same_row
= dram_pkt
->row
== (*p
)->row
;
1029 got_more_hits
|= same_rank_bank
&& same_row
;
1030 got_bank_conflict
|= same_rank_bank
&& !same_row
;
1034 // auto pre-charge when either
1035 // 1) open_adaptive policy, we have not got any more hits, and
1036 // have a bank conflict
1037 // 2) close_adaptive policy and we have not got any more hits
1038 auto_precharge
= !got_more_hits
&&
1039 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
);
1042 // if this access should use auto-precharge, then we are
1044 if (auto_precharge
) {
1046 bank
.freeAt
= std::max(bank
.freeAt
, bank
.tRASDoneAt
) + tRP
;
1048 if (numBanksActive
== 0) {
1049 startTickPrechargeAll
= std::max(startTickPrechargeAll
,
1051 DPRINTF(DRAM
, "All banks precharged at tick: %ld\n",
1052 startTickPrechargeAll
);
1055 // sample the bytes per activate here since we are closing
1057 bytesPerActivate
.sample(bank
.bytesAccessed
);
1059 DPRINTF(DRAM
, "Auto-precharged bank: %d\n", dram_pkt
->bankId
);
1062 DPRINTF(DRAM
, "doDRAMAccess::bank.freeAt is %lld\n", bank
.freeAt
);
1063 } else if (pageMgmt
== Enums::close
) {
1064 actTick
= curTick() + addDelay
+ accessLat
- tRCD
- tCL
;
1065 recordActivate(actTick
, dram_pkt
->rank
, dram_pkt
->bank
);
1067 // If the DRAM has a very quick tRAS, bank can be made free
1068 // after consecutive tCL,tRCD,tRP times. In general, however,
1069 // an additional wait is required to respect tRAS.
1070 bank
.freeAt
= std::max(actTick
+ tRAS
+ tRP
,
1071 actTick
+ tRCD
+ tCL
+ tRP
);
1072 DPRINTF(DRAM
, "doDRAMAccess::bank.freeAt is %lld\n", bank
.freeAt
);
1073 bytesPerActivate
.sample(burstSize
);
1074 startTickPrechargeAll
= std::max(startTickPrechargeAll
, bank
.freeAt
);
1076 panic("No page management policy chosen\n");
1078 // Update request parameters
1079 dram_pkt
->readyTime
= curTick() + addDelay
+ accessLat
+ tBURST
;
1082 DPRINTF(DRAM
, "Req %lld: curtick is %lld accessLat is %d " \
1083 "readytime is %lld busbusyuntil is %lld. " \
1084 "Scheduling at readyTime\n", dram_pkt
->addr
,
1085 curTick(), accessLat
, dram_pkt
->readyTime
, busBusyUntil
);
1087 // Make sure requests are not overlapping on the databus
1088 assert(dram_pkt
->readyTime
- busBusyUntil
>= tBURST
);
1091 busBusyUntil
= dram_pkt
->readyTime
;
1093 DPRINTF(DRAM
,"Access time is %lld\n",
1094 dram_pkt
->readyTime
- dram_pkt
->entryTime
);
1096 // Update the minimum timing between the requests, this is a
1097 // conservative estimate of when we have to schedule the next
1098 // request to not introduce any unecessary bubbles. In most cases
1099 // we will wake up sooner than we have to.
1100 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1102 // Update the stats and schedule the next request
1103 if (dram_pkt
->isRead
) {
1107 bytesReadDRAM
+= burstSize
;
1108 perBankRdBursts
[dram_pkt
->bankId
]++;
1110 // Update latency stats
1111 totMemAccLat
+= dram_pkt
->readyTime
- dram_pkt
->entryTime
;
1112 totBankLat
+= bankLat
;
1113 totBusLat
+= tBURST
;
1114 totQLat
+= dram_pkt
->readyTime
- dram_pkt
->entryTime
- bankLat
-
1120 bytesWritten
+= burstSize
;
1121 perBankWrBursts
[dram_pkt
->bankId
]++;
1126 DRAMCtrl::moveToRespQ()
1128 // Remove from read queue
1129 DRAMPacket
* dram_pkt
= readQueue
.front();
1130 readQueue
.pop_front();
1133 assert(dram_pkt
->size
<= burstSize
);
1135 // Insert into response queue sorted by readyTime
1136 // It will be sent back to the requestor at its
1138 if (respQueue
.empty()) {
1139 respQueue
.push_front(dram_pkt
);
1140 assert(!respondEvent
.scheduled());
1141 assert(dram_pkt
->readyTime
>= curTick());
1142 schedule(respondEvent
, dram_pkt
->readyTime
);
1145 auto i
= respQueue
.begin();
1146 while (!done
&& i
!= respQueue
.end()) {
1147 if ((*i
)->readyTime
> dram_pkt
->readyTime
) {
1148 respQueue
.insert(i
, dram_pkt
);
1155 respQueue
.push_back(dram_pkt
);
1157 assert(respondEvent
.scheduled());
1159 if (respQueue
.front()->readyTime
< respondEvent
.when()) {
1160 assert(respQueue
.front()->readyTime
>= curTick());
1161 reschedule(respondEvent
, respQueue
.front()->readyTime
);
1167 DRAMCtrl::processNextReqEvent()
1169 if (busState
== READ_TO_WRITE
) {
1170 DPRINTF(DRAM
, "Switching to writes after %d reads with %d reads "
1171 "waiting\n", readsThisTime
, readQueue
.size());
1173 // sample and reset the read-related stats as we are now
1174 // transitioning to writes, and all reads are done
1175 rdPerTurnAround
.sample(readsThisTime
);
1178 // now proceed to do the actual writes
1180 } else if (busState
== WRITE_TO_READ
) {
1181 DPRINTF(DRAM
, "Switching to reads after %d writes with %d writes "
1182 "waiting\n", writesThisTime
, writeQueue
.size());
1184 wrPerTurnAround
.sample(writesThisTime
);
1190 // when we get here it is either a read or a write
1191 if (busState
== READ
) {
1193 // track if we should switch or not
1194 bool switch_to_writes
= false;
1196 if (readQueue
.empty()) {
1197 // In the case there is no read request to go next,
1198 // trigger writes if we have passed the low threshold (or
1199 // if we are draining)
1200 if (!writeQueue
.empty() &&
1201 (drainManager
|| writeQueue
.size() > writeLowThreshold
)) {
1203 switch_to_writes
= true;
1205 // check if we are drained
1206 if (respQueue
.empty () && drainManager
) {
1207 drainManager
->signalDrainDone();
1208 drainManager
= NULL
;
1211 // nothing to do, not even any point in scheduling an
1212 // event for the next request
1216 // Figure out which read request goes next, and move it to the
1217 // front of the read queue
1218 chooseNext(readQueue
);
1220 doDRAMAccess(readQueue
.front());
1222 // At this point we're done dealing with the request
1223 // It will be moved to a separate response queue with a
1224 // correct readyTime, and eventually be sent back at that
1228 // we have so many writes that we have to transition
1229 if (writeQueue
.size() > writeHighThreshold
) {
1230 switch_to_writes
= true;
1234 // switching to writes, either because the read queue is empty
1235 // and the writes have passed the low threshold (or we are
1236 // draining), or because the writes hit the hight threshold
1237 if (switch_to_writes
) {
1238 // transition to writing
1239 busState
= READ_TO_WRITE
;
1241 // add a bubble to the data bus, as defined by the
1243 busBusyUntil
+= tRTW
;
1245 // update the minimum timing between the requests,
1246 // this shifts us back in time far enough to do any
1248 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1251 chooseNext(writeQueue
);
1252 DRAMPacket
* dram_pkt
= writeQueue
.front();
1254 assert(dram_pkt
->size
<= burstSize
);
1255 doDRAMAccess(dram_pkt
);
1257 writeQueue
.pop_front();
1260 // If we emptied the write queue, or got sufficiently below the
1261 // threshold (using the minWritesPerSwitch as the hysteresis) and
1262 // are not draining, or we have reads waiting and have done enough
1263 // writes, then switch to reads.
1264 if (writeQueue
.empty() ||
1265 (writeQueue
.size() + minWritesPerSwitch
< writeLowThreshold
&&
1267 (!readQueue
.empty() && writesThisTime
>= minWritesPerSwitch
)) {
1268 // turn the bus back around for reads again
1269 busState
= WRITE_TO_READ
;
1271 // note that the we switch back to reads also in the idle
1272 // case, which eventually will check for any draining and
1273 // also pause any further scheduling if there is really
1276 // here we get a bit creative and shift the bus busy time not
1277 // just the tWTR, but also a CAS latency to capture the fact
1278 // that we are allowed to prepare a new bank, but not issue a
1279 // read command until after tWTR, in essence we capture a
1280 // bubble on the data bus that is tWTR + tCL
1281 busBusyUntil
+= tWTR
+ tCL
;
1283 // update the minimum timing between the requests, this shifts
1284 // us back in time far enough to do any bank preparation
1285 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1289 schedule(nextReqEvent
, std::max(nextReqTime
, curTick()));
1291 // If there is space available and we have writes waiting then let
1292 // them retry. This is done here to ensure that the retry does not
1293 // cause a nextReqEvent to be scheduled before we do so as part of
1294 // the next request processing
1295 if (retryWrReq
&& writeQueue
.size() < writeBufferSize
) {
1302 DRAMCtrl::maxBankFreeAt() const
1306 for(int i
= 0; i
< ranksPerChannel
; i
++)
1307 for(int j
= 0; j
< banksPerRank
; j
++)
1308 banksFree
= std::max(banks
[i
][j
].freeAt
, banksFree
);
1314 DRAMCtrl::minBankFreeAt(const deque
<DRAMPacket
*>& queue
) const
1316 uint64_t bank_mask
= 0;
1317 Tick freeAt
= MaxTick
;
1319 // detemrine if we have queued transactions targetting the
1321 vector
<bool> got_waiting(ranksPerChannel
* banksPerRank
, false);
1322 for (auto p
= queue
.begin(); p
!= queue
.end(); ++p
) {
1323 got_waiting
[(*p
)->bankId
] = true;
1326 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1327 for (int j
= 0; j
< banksPerRank
; j
++) {
1328 // if we have waiting requests for the bank, and it is
1329 // amongst the first available, update the mask
1330 if (got_waiting
[i
* banksPerRank
+ j
] &&
1331 banks
[i
][j
].freeAt
<= freeAt
) {
1332 // reset bank mask if new minimum is found
1333 if (banks
[i
][j
].freeAt
< freeAt
)
1335 // set the bit corresponding to the available bank
1336 uint8_t bit_index
= i
* ranksPerChannel
+ j
;
1337 replaceBits(bank_mask
, bit_index
, bit_index
, 1);
1338 freeAt
= banks
[i
][j
].freeAt
;
1346 DRAMCtrl::processRefreshEvent()
1348 DPRINTF(DRAM
, "Refreshing at tick %ld\n", curTick());
1350 Tick banksFree
= std::max(curTick(), maxBankFreeAt()) + tRFC
;
1352 for(int i
= 0; i
< ranksPerChannel
; i
++)
1353 for(int j
= 0; j
< banksPerRank
; j
++) {
1354 banks
[i
][j
].freeAt
= banksFree
;
1355 banks
[i
][j
].openRow
= -1;
1358 // updating startTickPrechargeAll, isprechargeAll
1360 startTickPrechargeAll
= banksFree
;
1362 schedule(refreshEvent
, curTick() + tREFI
);
1366 DRAMCtrl::regStats()
1368 using namespace Stats
;
1370 AbstractMemory::regStats();
1373 .name(name() + ".readReqs")
1374 .desc("Number of read requests accepted");
1377 .name(name() + ".writeReqs")
1378 .desc("Number of write requests accepted");
1381 .name(name() + ".readBursts")
1382 .desc("Number of DRAM read bursts, "
1383 "including those serviced by the write queue");
1386 .name(name() + ".writeBursts")
1387 .desc("Number of DRAM write bursts, "
1388 "including those merged in the write queue");
1391 .name(name() + ".servicedByWrQ")
1392 .desc("Number of DRAM read bursts serviced by the write queue");
1395 .name(name() + ".mergedWrBursts")
1396 .desc("Number of DRAM write bursts merged with an existing one");
1399 .name(name() + ".neitherReadNorWriteReqs")
1400 .desc("Number of requests that are neither read nor write");
1403 .init(banksPerRank
* ranksPerChannel
)
1404 .name(name() + ".perBankRdBursts")
1405 .desc("Per bank write bursts");
1408 .init(banksPerRank
* ranksPerChannel
)
1409 .name(name() + ".perBankWrBursts")
1410 .desc("Per bank write bursts");
1413 .name(name() + ".avgRdQLen")
1414 .desc("Average read queue length when enqueuing")
1418 .name(name() + ".avgWrQLen")
1419 .desc("Average write queue length when enqueuing")
1423 .name(name() + ".totQLat")
1424 .desc("Total ticks spent queuing");
1427 .name(name() + ".totBankLat")
1428 .desc("Total ticks spent accessing banks");
1431 .name(name() + ".totBusLat")
1432 .desc("Total ticks spent in databus transfers");
1435 .name(name() + ".totMemAccLat")
1436 .desc("Total ticks spent from burst creation until serviced "
1440 .name(name() + ".avgQLat")
1441 .desc("Average queueing delay per DRAM burst")
1444 avgQLat
= totQLat
/ (readBursts
- servicedByWrQ
);
1447 .name(name() + ".avgBankLat")
1448 .desc("Average bank access latency per DRAM burst")
1451 avgBankLat
= totBankLat
/ (readBursts
- servicedByWrQ
);
1454 .name(name() + ".avgBusLat")
1455 .desc("Average bus latency per DRAM burst")
1458 avgBusLat
= totBusLat
/ (readBursts
- servicedByWrQ
);
1461 .name(name() + ".avgMemAccLat")
1462 .desc("Average memory access latency per DRAM burst")
1465 avgMemAccLat
= totMemAccLat
/ (readBursts
- servicedByWrQ
);
1468 .name(name() + ".numRdRetry")
1469 .desc("Number of times read queue was full causing retry");
1472 .name(name() + ".numWrRetry")
1473 .desc("Number of times write queue was full causing retry");
1476 .name(name() + ".readRowHits")
1477 .desc("Number of row buffer hits during reads");
1480 .name(name() + ".writeRowHits")
1481 .desc("Number of row buffer hits during writes");
1484 .name(name() + ".readRowHitRate")
1485 .desc("Row buffer hit rate for reads")
1488 readRowHitRate
= (readRowHits
/ (readBursts
- servicedByWrQ
)) * 100;
1491 .name(name() + ".writeRowHitRate")
1492 .desc("Row buffer hit rate for writes")
1495 writeRowHitRate
= (writeRowHits
/ (writeBursts
- mergedWrBursts
)) * 100;
1498 .init(ceilLog2(burstSize
) + 1)
1499 .name(name() + ".readPktSize")
1500 .desc("Read request sizes (log2)");
1503 .init(ceilLog2(burstSize
) + 1)
1504 .name(name() + ".writePktSize")
1505 .desc("Write request sizes (log2)");
1508 .init(readBufferSize
)
1509 .name(name() + ".rdQLenPdf")
1510 .desc("What read queue length does an incoming req see");
1513 .init(writeBufferSize
)
1514 .name(name() + ".wrQLenPdf")
1515 .desc("What write queue length does an incoming req see");
1518 .init(maxAccessesPerRow
)
1519 .name(name() + ".bytesPerActivate")
1520 .desc("Bytes accessed per row activation")
1524 .init(readBufferSize
)
1525 .name(name() + ".rdPerTurnAround")
1526 .desc("Reads before turning the bus around for writes")
1530 .init(writeBufferSize
)
1531 .name(name() + ".wrPerTurnAround")
1532 .desc("Writes before turning the bus around for reads")
1536 .name(name() + ".bytesReadDRAM")
1537 .desc("Total number of bytes read from DRAM");
1540 .name(name() + ".bytesReadWrQ")
1541 .desc("Total number of bytes read from write queue");
1544 .name(name() + ".bytesWritten")
1545 .desc("Total number of bytes written to DRAM");
1548 .name(name() + ".bytesReadSys")
1549 .desc("Total read bytes from the system interface side");
1552 .name(name() + ".bytesWrittenSys")
1553 .desc("Total written bytes from the system interface side");
1556 .name(name() + ".avgRdBW")
1557 .desc("Average DRAM read bandwidth in MiByte/s")
1560 avgRdBW
= (bytesReadDRAM
/ 1000000) / simSeconds
;
1563 .name(name() + ".avgWrBW")
1564 .desc("Average achieved write bandwidth in MiByte/s")
1567 avgWrBW
= (bytesWritten
/ 1000000) / simSeconds
;
1570 .name(name() + ".avgRdBWSys")
1571 .desc("Average system read bandwidth in MiByte/s")
1574 avgRdBWSys
= (bytesReadSys
/ 1000000) / simSeconds
;
1577 .name(name() + ".avgWrBWSys")
1578 .desc("Average system write bandwidth in MiByte/s")
1581 avgWrBWSys
= (bytesWrittenSys
/ 1000000) / simSeconds
;
1584 .name(name() + ".peakBW")
1585 .desc("Theoretical peak bandwidth in MiByte/s")
1588 peakBW
= (SimClock::Frequency
/ tBURST
) * burstSize
/ 1000000;
1591 .name(name() + ".busUtil")
1592 .desc("Data bus utilization in percentage")
1595 busUtil
= (avgRdBW
+ avgWrBW
) / peakBW
* 100;
1598 .name(name() + ".totGap")
1599 .desc("Total gap between requests");
1602 .name(name() + ".avgGap")
1603 .desc("Average gap between requests")
1606 avgGap
= totGap
/ (readReqs
+ writeReqs
);
1608 // Stats for DRAM Power calculation based on Micron datasheet
1610 .name(name() + ".busUtilRead")
1611 .desc("Data bus utilization in percentage for reads")
1614 busUtilRead
= avgRdBW
/ peakBW
* 100;
1617 .name(name() + ".busUtilWrite")
1618 .desc("Data bus utilization in percentage for writes")
1621 busUtilWrite
= avgWrBW
/ peakBW
* 100;
1624 .name(name() + ".pageHitRate")
1625 .desc("Row buffer hit rate, read and write combined")
1628 pageHitRate
= (writeRowHits
+ readRowHits
) /
1629 (writeBursts
- mergedWrBursts
+ readBursts
- servicedByWrQ
) * 100;
1632 .name(name() + ".prechargeAllPercent")
1633 .desc("Percentage of time for which DRAM has all the banks in "
1637 prechargeAllPercent
= prechargeAllTime
/ simTicks
* 100;
1641 DRAMCtrl::recvFunctional(PacketPtr pkt
)
1643 // rely on the abstract memory
1644 functionalAccess(pkt
);
1648 DRAMCtrl::getSlavePort(const string
&if_name
, PortID idx
)
1650 if (if_name
!= "port") {
1651 return MemObject::getSlavePort(if_name
, idx
);
1658 DRAMCtrl::drain(DrainManager
*dm
)
1660 unsigned int count
= port
.drain(dm
);
1662 // if there is anything in any of our internal queues, keep track
1664 if (!(writeQueue
.empty() && readQueue
.empty() &&
1665 respQueue
.empty())) {
1666 DPRINTF(Drain
, "DRAM controller not drained, write: %d, read: %d,"
1667 " resp: %d\n", writeQueue
.size(), readQueue
.size(),
1672 // the only part that is not drained automatically over time
1673 // is the write queue, thus kick things into action if needed
1674 if (!writeQueue
.empty() && !nextReqEvent
.scheduled()) {
1675 schedule(nextReqEvent
, curTick());
1680 setDrainState(Drainable::Draining
);
1682 setDrainState(Drainable::Drained
);
1686 DRAMCtrl::MemoryPort::MemoryPort(const std::string
& name
, DRAMCtrl
& _memory
)
1687 : QueuedSlavePort(name
, &_memory
, queue
), queue(_memory
, *this),
1692 DRAMCtrl::MemoryPort::getAddrRanges() const
1694 AddrRangeList ranges
;
1695 ranges
.push_back(memory
.getAddrRange());
1700 DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt
)
1702 pkt
->pushLabel(memory
.name());
1704 if (!queue
.checkFunctional(pkt
)) {
1705 // Default implementation of SimpleTimingPort::recvFunctional()
1706 // calls recvAtomic() and throws away the latency; we can save a
1707 // little here by just not calculating the latency.
1708 memory
.recvFunctional(pkt
);
1715 DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt
)
1717 return memory
.recvAtomic(pkt
);
1721 DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt
)
1723 // pass it to the memory controller
1724 return memory
.recvTimingReq(pkt
);
1728 DRAMCtrlParams::create()
1730 return new DRAMCtrl(this);