2 * Copyright (c) 2010-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
45 #include "base/bitfield.hh"
46 #include "base/trace.hh"
47 #include "debug/DRAM.hh"
48 #include "debug/DRAMState.hh"
49 #include "debug/Drain.hh"
50 #include "mem/dram_ctrl.hh"
51 #include "sim/system.hh"
55 DRAMCtrl::DRAMCtrl(const DRAMCtrlParams
* p
) :
57 port(name() + ".port", *this),
58 retryRdReq(false), retryWrReq(false),
60 nextReqEvent(this), respondEvent(this), activateEvent(this),
61 prechargeEvent(this), refreshEvent(this), powerEvent(this),
63 deviceBusWidth(p
->device_bus_width
), burstLength(p
->burst_length
),
64 deviceRowBufferSize(p
->device_rowbuffer_size
),
65 devicesPerRank(p
->devices_per_rank
),
66 burstSize((devicesPerRank
* burstLength
* deviceBusWidth
) / 8),
67 rowBufferSize(devicesPerRank
* deviceRowBufferSize
),
68 columnsPerRowBuffer(rowBufferSize
/ burstSize
),
69 ranksPerChannel(p
->ranks_per_channel
),
70 banksPerRank(p
->banks_per_rank
), channels(p
->channels
), rowsPerBank(0),
71 readBufferSize(p
->read_buffer_size
),
72 writeBufferSize(p
->write_buffer_size
),
73 writeHighThreshold(writeBufferSize
* p
->write_high_thresh_perc
/ 100.0),
74 writeLowThreshold(writeBufferSize
* p
->write_low_thresh_perc
/ 100.0),
75 minWritesPerSwitch(p
->min_writes_per_switch
),
76 writesThisTime(0), readsThisTime(0),
77 tWTR(p
->tWTR
), tRTW(p
->tRTW
), tBURST(p
->tBURST
),
78 tRCD(p
->tRCD
), tCL(p
->tCL
), tRP(p
->tRP
), tRAS(p
->tRAS
), tWR(p
->tWR
),
79 tRFC(p
->tRFC
), tREFI(p
->tREFI
), tRRD(p
->tRRD
),
80 tXAW(p
->tXAW
), activationLimit(p
->activation_limit
),
81 memSchedPolicy(p
->mem_sched_policy
), addrMapping(p
->addr_mapping
),
82 pageMgmt(p
->page_policy
),
83 maxAccessesPerRow(p
->max_accesses_per_row
),
84 frontendLatency(p
->static_frontend_latency
),
85 backendLatency(p
->static_backend_latency
),
86 busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE
),
87 pwrStateTrans(PWR_IDLE
), pwrState(PWR_IDLE
), prevArrival(0),
88 nextReqTime(0), pwrStateTick(0), numBanksActive(0)
90 // create the bank states based on the dimensions of the ranks and
92 banks
.resize(ranksPerChannel
);
93 actTicks
.resize(ranksPerChannel
);
94 for (size_t c
= 0; c
< ranksPerChannel
; ++c
) {
95 banks
[c
].resize(banksPerRank
);
96 actTicks
[c
].resize(activationLimit
, 0);
99 // perform a basic check of the write thresholds
100 if (p
->write_low_thresh_perc
>= p
->write_high_thresh_perc
)
101 fatal("Write buffer low threshold %d must be smaller than the "
102 "high threshold %d\n", p
->write_low_thresh_perc
,
103 p
->write_high_thresh_perc
);
105 // determine the rows per bank by looking at the total capacity
106 uint64_t capacity
= ULL(1) << ceilLog2(AbstractMemory::size());
108 DPRINTF(DRAM
, "Memory capacity %lld (%lld) bytes\n", capacity
,
109 AbstractMemory::size());
111 DPRINTF(DRAM
, "Row buffer size %d bytes with %d columns per row buffer\n",
112 rowBufferSize
, columnsPerRowBuffer
);
114 rowsPerBank
= capacity
/ (rowBufferSize
* banksPerRank
* ranksPerChannel
);
116 if (range
.interleaved()) {
117 if (channels
!= range
.stripes())
118 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
119 name(), range
.stripes(), channels
);
121 if (addrMapping
== Enums::RoRaBaChCo
) {
122 if (rowBufferSize
!= range
.granularity()) {
123 fatal("Interleaving of %s doesn't match RoRaBaChCo "
124 "address map\n", name());
126 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
127 if (system()->cacheLineSize() != range
.granularity()) {
128 fatal("Interleaving of %s doesn't match RoRaBaCoCh "
129 "address map\n", name());
131 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
132 if (system()->cacheLineSize() != range
.granularity())
133 fatal("Interleaving of %s doesn't match RoCoRaBaCh "
134 "address map\n", name());
138 // some basic sanity checks
139 if (tREFI
<= tRP
|| tREFI
<= tRFC
) {
140 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
148 if (!port
.isConnected()) {
149 fatal("DRAMCtrl %s is unconnected!\n", name());
151 port
.sendRangeChange();
158 // update the start tick for the precharge accounting to the
160 pwrStateTick
= curTick();
162 // shift the bus busy time sufficiently far ahead that we never
163 // have to worry about negative values when computing the time for
164 // the next request, this will add an insignificant bubble at the
165 // start of simulation
166 busBusyUntil
= curTick() + tRP
+ tRCD
+ tCL
;
168 // print the configuration of the controller
171 // kick off the refresh, and give ourselves enough time to
173 schedule(refreshEvent
, curTick() + tREFI
- tRP
);
177 DRAMCtrl::recvAtomic(PacketPtr pkt
)
179 DPRINTF(DRAM
, "recvAtomic: %s 0x%x\n", pkt
->cmdString(), pkt
->getAddr());
181 // do the actual memory access and turn the packet into a response
185 if (!pkt
->memInhibitAsserted() && pkt
->hasData()) {
186 // this value is not supposed to be accurate, just enough to
187 // keep things going, mimic a closed page
188 latency
= tRP
+ tRCD
+ tCL
;
194 DRAMCtrl::readQueueFull(unsigned int neededEntries
) const
196 DPRINTF(DRAM
, "Read queue limit %d, current size %d, entries needed %d\n",
197 readBufferSize
, readQueue
.size() + respQueue
.size(),
201 (readQueue
.size() + respQueue
.size() + neededEntries
) > readBufferSize
;
205 DRAMCtrl::writeQueueFull(unsigned int neededEntries
) const
207 DPRINTF(DRAM
, "Write queue limit %d, current size %d, entries needed %d\n",
208 writeBufferSize
, writeQueue
.size(), neededEntries
);
209 return (writeQueue
.size() + neededEntries
) > writeBufferSize
;
212 DRAMCtrl::DRAMPacket
*
213 DRAMCtrl::decodeAddr(PacketPtr pkt
, Addr dramPktAddr
, unsigned size
,
216 // decode the address based on the address mapping scheme, with
217 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
218 // channel, respectively
223 // truncate the address to the access granularity
224 Addr addr
= dramPktAddr
/ burstSize
;
226 // we have removed the lowest order address bits that denote the
227 // position within the column
228 if (addrMapping
== Enums::RoRaBaChCo
) {
229 // the lowest order bits denote the column to ensure that
230 // sequential cache lines occupy the same row
231 addr
= addr
/ columnsPerRowBuffer
;
233 // take out the channel part of the address
234 addr
= addr
/ channels
;
236 // after the channel bits, get the bank bits to interleave
238 bank
= addr
% banksPerRank
;
239 addr
= addr
/ banksPerRank
;
241 // after the bank, we get the rank bits which thus interleaves
243 rank
= addr
% ranksPerChannel
;
244 addr
= addr
/ ranksPerChannel
;
246 // lastly, get the row bits
247 row
= addr
% rowsPerBank
;
248 addr
= addr
/ rowsPerBank
;
249 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
250 // take out the channel part of the address
251 addr
= addr
/ channels
;
254 addr
= addr
/ columnsPerRowBuffer
;
256 // after the column bits, we get the bank bits to interleave
258 bank
= addr
% banksPerRank
;
259 addr
= addr
/ banksPerRank
;
261 // after the bank, we get the rank bits which thus interleaves
263 rank
= addr
% ranksPerChannel
;
264 addr
= addr
/ ranksPerChannel
;
266 // lastly, get the row bits
267 row
= addr
% rowsPerBank
;
268 addr
= addr
/ rowsPerBank
;
269 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
270 // optimise for closed page mode and utilise maximum
271 // parallelism of the DRAM (at the cost of power)
273 // take out the channel part of the address, not that this has
274 // to match with how accesses are interleaved between the
275 // controllers in the address mapping
276 addr
= addr
/ channels
;
278 // start with the bank bits, as this provides the maximum
279 // opportunity for parallelism between requests
280 bank
= addr
% banksPerRank
;
281 addr
= addr
/ banksPerRank
;
283 // next get the rank bits
284 rank
= addr
% ranksPerChannel
;
285 addr
= addr
/ ranksPerChannel
;
287 // next the column bits which we do not need to keep track of
288 // and simply skip past
289 addr
= addr
/ columnsPerRowBuffer
;
291 // lastly, get the row bits
292 row
= addr
% rowsPerBank
;
293 addr
= addr
/ rowsPerBank
;
295 panic("Unknown address mapping policy chosen!");
297 assert(rank
< ranksPerChannel
);
298 assert(bank
< banksPerRank
);
299 assert(row
< rowsPerBank
);
301 DPRINTF(DRAM
, "Address: %lld Rank %d Bank %d Row %d\n",
302 dramPktAddr
, rank
, bank
, row
);
304 // create the corresponding DRAM packet with the entry time and
305 // ready time set to the current tick, the latter will be updated
307 uint16_t bank_id
= banksPerRank
* rank
+ bank
;
308 return new DRAMPacket(pkt
, isRead
, rank
, bank
, row
, bank_id
, dramPktAddr
,
309 size
, banks
[rank
][bank
]);
313 DRAMCtrl::addToReadQueue(PacketPtr pkt
, unsigned int pktCount
)
315 // only add to the read queue here. whenever the request is
316 // eventually done, set the readyTime, and call schedule()
317 assert(!pkt
->isWrite());
319 assert(pktCount
!= 0);
321 // if the request size is larger than burst size, the pkt is split into
322 // multiple DRAM packets
323 // Note if the pkt starting address is not aligened to burst size, the
324 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
325 // are aligned to burst size boundaries. This is to ensure we accurately
326 // check read packets against packets in write queue.
327 Addr addr
= pkt
->getAddr();
328 unsigned pktsServicedByWrQ
= 0;
329 BurstHelper
* burst_helper
= NULL
;
330 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
331 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
332 pkt
->getAddr() + pkt
->getSize()) - addr
;
333 readPktSize
[ceilLog2(size
)]++;
336 // First check write buffer to see if the data is already at
338 bool foundInWrQ
= false;
339 for (auto i
= writeQueue
.begin(); i
!= writeQueue
.end(); ++i
) {
340 // check if the read is subsumed in the write entry we are
342 if ((*i
)->addr
<= addr
&&
343 (addr
+ size
) <= ((*i
)->addr
+ (*i
)->size
)) {
347 DPRINTF(DRAM
, "Read to addr %lld with size %d serviced by "
348 "write queue\n", addr
, size
);
349 bytesReadWrQ
+= burstSize
;
354 // If not found in the write q, make a DRAM packet and
355 // push it onto the read queue
358 // Make the burst helper for split packets
359 if (pktCount
> 1 && burst_helper
== NULL
) {
360 DPRINTF(DRAM
, "Read to addr %lld translates to %d "
361 "dram requests\n", pkt
->getAddr(), pktCount
);
362 burst_helper
= new BurstHelper(pktCount
);
365 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, true);
366 dram_pkt
->burstHelper
= burst_helper
;
368 assert(!readQueueFull(1));
369 rdQLenPdf
[readQueue
.size() + respQueue
.size()]++;
371 DPRINTF(DRAM
, "Adding to read queue\n");
373 readQueue
.push_back(dram_pkt
);
376 avgRdQLen
= readQueue
.size() + respQueue
.size();
379 // Starting address of next dram pkt (aligend to burstSize boundary)
380 addr
= (addr
| (burstSize
- 1)) + 1;
383 // If all packets are serviced by write queue, we send the repsonse back
384 if (pktsServicedByWrQ
== pktCount
) {
385 accessAndRespond(pkt
, frontendLatency
);
389 // Update how many split packets are serviced by write queue
390 if (burst_helper
!= NULL
)
391 burst_helper
->burstsServiced
= pktsServicedByWrQ
;
393 // If we are not already scheduled to get a request out of the
395 if (!nextReqEvent
.scheduled()) {
396 DPRINTF(DRAM
, "Request scheduled immediately\n");
397 schedule(nextReqEvent
, curTick());
402 DRAMCtrl::addToWriteQueue(PacketPtr pkt
, unsigned int pktCount
)
404 // only add to the write queue here. whenever the request is
405 // eventually done, set the readyTime, and call schedule()
406 assert(pkt
->isWrite());
408 // if the request size is larger than burst size, the pkt is split into
409 // multiple DRAM packets
410 Addr addr
= pkt
->getAddr();
411 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
412 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
413 pkt
->getAddr() + pkt
->getSize()) - addr
;
414 writePktSize
[ceilLog2(size
)]++;
417 // see if we can merge with an existing item in the write
418 // queue and keep track of whether we have merged or not so we
419 // can stop at that point and also avoid enqueueing a new
422 auto w
= writeQueue
.begin();
424 while(!merged
&& w
!= writeQueue
.end()) {
425 // either of the two could be first, if they are the same
426 // it does not matter which way we go
427 if ((*w
)->addr
>= addr
) {
428 // the existing one starts after the new one, figure
429 // out where the new one ends with respect to the
431 if ((addr
+ size
) >= ((*w
)->addr
+ (*w
)->size
)) {
432 // check if the existing one is completely
433 // subsumed in the new one
434 DPRINTF(DRAM
, "Merging write covering existing burst\n");
436 // update both the address and the size
439 } else if ((addr
+ size
) >= (*w
)->addr
&&
440 ((*w
)->addr
+ (*w
)->size
- addr
) <= burstSize
) {
441 // the new one is just before or partially
442 // overlapping with the existing one, and together
443 // they fit within a burst
444 DPRINTF(DRAM
, "Merging write before existing burst\n");
446 // the existing queue item needs to be adjusted with
447 // respect to both address and size
448 (*w
)->size
= (*w
)->addr
+ (*w
)->size
- addr
;
452 // the new one starts after the current one, figure
453 // out where the existing one ends with respect to the
455 if (((*w
)->addr
+ (*w
)->size
) >= (addr
+ size
)) {
456 // check if the new one is completely subsumed in the
458 DPRINTF(DRAM
, "Merging write into existing burst\n");
460 // no adjustments necessary
461 } else if (((*w
)->addr
+ (*w
)->size
) >= addr
&&
462 (addr
+ size
- (*w
)->addr
) <= burstSize
) {
463 // the existing one is just before or partially
464 // overlapping with the new one, and together
465 // they fit within a burst
466 DPRINTF(DRAM
, "Merging write after existing burst\n");
468 // the address is right, and only the size has
470 (*w
)->size
= addr
+ size
- (*w
)->addr
;
476 // if the item was not merged we need to create a new write
479 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, false);
481 assert(writeQueue
.size() < writeBufferSize
);
482 wrQLenPdf
[writeQueue
.size()]++;
484 DPRINTF(DRAM
, "Adding to write queue\n");
486 writeQueue
.push_back(dram_pkt
);
489 avgWrQLen
= writeQueue
.size();
491 // keep track of the fact that this burst effectively
492 // disappeared as it was merged with an existing one
496 // Starting address of next dram pkt (aligend to burstSize boundary)
497 addr
= (addr
| (burstSize
- 1)) + 1;
500 // we do not wait for the writes to be send to the actual memory,
501 // but instead take responsibility for the consistency here and
502 // snoop the write queue for any upcoming reads
503 // @todo, if a pkt size is larger than burst size, we might need a
504 // different front end latency
505 accessAndRespond(pkt
, frontendLatency
);
507 // If we are not already scheduled to get a request out of the
509 if (!nextReqEvent
.scheduled()) {
510 DPRINTF(DRAM
, "Request scheduled immediately\n");
511 schedule(nextReqEvent
, curTick());
516 DRAMCtrl::printParams() const
518 // Sanity check print of important parameters
520 "Memory controller %s physical organization\n" \
521 "Number of devices per rank %d\n" \
522 "Device bus width (in bits) %d\n" \
523 "DRAM data bus burst (bytes) %d\n" \
524 "Row buffer size (bytes) %d\n" \
525 "Columns per row buffer %d\n" \
526 "Rows per bank %d\n" \
527 "Banks per rank %d\n" \
528 "Ranks per channel %d\n" \
529 "Total mem capacity (bytes) %u\n",
530 name(), devicesPerRank
, deviceBusWidth
, burstSize
, rowBufferSize
,
531 columnsPerRowBuffer
, rowsPerBank
, banksPerRank
, ranksPerChannel
,
532 rowBufferSize
* rowsPerBank
* banksPerRank
* ranksPerChannel
);
534 string scheduler
= memSchedPolicy
== Enums::fcfs
? "FCFS" : "FR-FCFS";
535 string address_mapping
= addrMapping
== Enums::RoRaBaChCo
? "RoRaBaChCo" :
536 (addrMapping
== Enums::RoRaBaCoCh
? "RoRaBaCoCh" : "RoCoRaBaCh");
537 string page_policy
= pageMgmt
== Enums::open
? "OPEN" :
538 (pageMgmt
== Enums::open_adaptive
? "OPEN (adaptive)" :
539 (pageMgmt
== Enums::close_adaptive
? "CLOSE (adaptive)" : "CLOSE"));
542 "Memory controller %s characteristics\n" \
543 "Read buffer size %d\n" \
544 "Write buffer size %d\n" \
545 "Write high thresh %d\n" \
546 "Write low thresh %d\n" \
548 "Address mapping %s\n" \
550 name(), readBufferSize
, writeBufferSize
, writeHighThreshold
,
551 writeLowThreshold
, scheduler
, address_mapping
, page_policy
);
553 DPRINTF(DRAM
, "Memory controller %s timing specs\n" \
557 "tBURST %d ticks\n" \
563 "tXAW (%d) %d ticks\n",
564 name(), tRCD
, tCL
, tRP
, tBURST
, tRFC
, tREFI
, tWTR
,
565 tRTW
, tWR
, activationLimit
, tXAW
);
569 DRAMCtrl::printQs() const {
570 DPRINTF(DRAM
, "===READ QUEUE===\n\n");
571 for (auto i
= readQueue
.begin() ; i
!= readQueue
.end() ; ++i
) {
572 DPRINTF(DRAM
, "Read %lu\n", (*i
)->addr
);
574 DPRINTF(DRAM
, "\n===RESP QUEUE===\n\n");
575 for (auto i
= respQueue
.begin() ; i
!= respQueue
.end() ; ++i
) {
576 DPRINTF(DRAM
, "Response %lu\n", (*i
)->addr
);
578 DPRINTF(DRAM
, "\n===WRITE QUEUE===\n\n");
579 for (auto i
= writeQueue
.begin() ; i
!= writeQueue
.end() ; ++i
) {
580 DPRINTF(DRAM
, "Write %lu\n", (*i
)->addr
);
585 DRAMCtrl::recvTimingReq(PacketPtr pkt
)
587 /// @todo temporary hack to deal with memory corruption issues until
588 /// 4-phase transactions are complete
589 for (int x
= 0; x
< pendingDelete
.size(); x
++)
590 delete pendingDelete
[x
];
591 pendingDelete
.clear();
593 // This is where we enter from the outside world
594 DPRINTF(DRAM
, "recvTimingReq: request %s addr %lld size %d\n",
595 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
597 // simply drop inhibited packets for now
598 if (pkt
->memInhibitAsserted()) {
599 DPRINTF(DRAM
, "Inhibited packet -- Dropping it now\n");
600 pendingDelete
.push_back(pkt
);
604 // Calc avg gap between requests
605 if (prevArrival
!= 0) {
606 totGap
+= curTick() - prevArrival
;
608 prevArrival
= curTick();
611 // Find out how many dram packets a pkt translates to
612 // If the burst size is equal or larger than the pkt size, then a pkt
613 // translates to only one dram packet. Otherwise, a pkt translates to
614 // multiple dram packets
615 unsigned size
= pkt
->getSize();
616 unsigned offset
= pkt
->getAddr() & (burstSize
- 1);
617 unsigned int dram_pkt_count
= divCeil(offset
+ size
, burstSize
);
619 // check local buffers and do not accept if full
622 if (readQueueFull(dram_pkt_count
)) {
623 DPRINTF(DRAM
, "Read queue full, not accepting\n");
624 // remember that we have to retry this port
629 addToReadQueue(pkt
, dram_pkt_count
);
631 bytesReadSys
+= size
;
633 } else if (pkt
->isWrite()) {
635 if (writeQueueFull(dram_pkt_count
)) {
636 DPRINTF(DRAM
, "Write queue full, not accepting\n");
637 // remember that we have to retry this port
642 addToWriteQueue(pkt
, dram_pkt_count
);
644 bytesWrittenSys
+= size
;
647 DPRINTF(DRAM
,"Neither read nor write, ignore timing\n");
648 neitherReadNorWrite
++;
649 accessAndRespond(pkt
, 1);
656 DRAMCtrl::processRespondEvent()
659 "processRespondEvent(): Some req has reached its readyTime\n");
661 DRAMPacket
* dram_pkt
= respQueue
.front();
663 if (dram_pkt
->burstHelper
) {
664 // it is a split packet
665 dram_pkt
->burstHelper
->burstsServiced
++;
666 if (dram_pkt
->burstHelper
->burstsServiced
==
667 dram_pkt
->burstHelper
->burstCount
) {
668 // we have now serviced all children packets of a system packet
669 // so we can now respond to the requester
670 // @todo we probably want to have a different front end and back
671 // end latency for split packets
672 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
673 delete dram_pkt
->burstHelper
;
674 dram_pkt
->burstHelper
= NULL
;
677 // it is not a split packet
678 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
681 delete respQueue
.front();
682 respQueue
.pop_front();
684 if (!respQueue
.empty()) {
685 assert(respQueue
.front()->readyTime
>= curTick());
686 assert(!respondEvent
.scheduled());
687 schedule(respondEvent
, respQueue
.front()->readyTime
);
689 // if there is nothing left in any queue, signal a drain
690 if (writeQueue
.empty() && readQueue
.empty() &&
692 drainManager
->signalDrainDone();
697 // We have made a location in the queue available at this point,
698 // so if there is a read that was forced to wait, retry now
706 DRAMCtrl::chooseNext(std::deque
<DRAMPacket
*>& queue
)
708 // This method does the arbitration between requests. The chosen
709 // packet is simply moved to the head of the queue. The other
710 // methods know that this is the place to look. For example, with
711 // FCFS, this method does nothing
712 assert(!queue
.empty());
714 if (queue
.size() == 1) {
715 DPRINTF(DRAM
, "Single request, nothing to do\n");
719 if (memSchedPolicy
== Enums::fcfs
) {
720 // Do nothing, since the correct request is already head
721 } else if (memSchedPolicy
== Enums::frfcfs
) {
724 panic("No scheduling policy chosen\n");
728 DRAMCtrl::reorderQueue(std::deque
<DRAMPacket
*>& queue
)
730 // Only determine this when needed
731 uint64_t earliest_banks
= 0;
733 // Search for row hits first, if no row hit is found then schedule the
734 // packet to one of the earliest banks available
735 bool found_earliest_pkt
= false;
736 auto selected_pkt_it
= queue
.begin();
738 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
739 DRAMPacket
* dram_pkt
= *i
;
740 const Bank
& bank
= dram_pkt
->bankRef
;
741 // Check if it is a row hit
742 if (bank
.openRow
== dram_pkt
->row
) {
743 // FCFS within the hits
744 DPRINTF(DRAM
, "Row buffer hit\n");
747 } else if (!found_earliest_pkt
) {
748 // No row hit, go for first ready
749 if (earliest_banks
== 0)
750 earliest_banks
= minBankActAt(queue
);
752 // simplistic approximation of when the bank can issue an
753 // activate, this is calculated in minBankActAt and could
755 Tick act_at
= bank
.openRow
== Bank::NO_ROW
?
757 std::max(bank
.preAllowedAt
, curTick()) + tRP
;
759 // Bank is ready or is the first available bank
760 if (act_at
<= curTick() ||
761 bits(earliest_banks
, dram_pkt
->bankId
, dram_pkt
->bankId
)) {
762 // Remember the packet to be scheduled to one of the earliest
763 // banks available, FCFS amongst the earliest banks
765 found_earliest_pkt
= true;
770 DRAMPacket
* selected_pkt
= *selected_pkt_it
;
771 queue
.erase(selected_pkt_it
);
772 queue
.push_front(selected_pkt
);
776 DRAMCtrl::accessAndRespond(PacketPtr pkt
, Tick static_latency
)
778 DPRINTF(DRAM
, "Responding to Address %lld.. ",pkt
->getAddr());
780 bool needsResponse
= pkt
->needsResponse();
781 // do the actual memory access which also turns the packet into a
785 // turn packet around to go back to requester if response expected
787 // access already turned the packet into a response
788 assert(pkt
->isResponse());
790 // @todo someone should pay for this
791 pkt
->busFirstWordDelay
= pkt
->busLastWordDelay
= 0;
793 // queue the packet in the response queue to be sent out after
794 // the static latency has passed
795 port
.schedTimingResp(pkt
, curTick() + static_latency
);
797 // @todo the packet is going to be deleted, and the DRAMPacket
798 // is still having a pointer to it
799 pendingDelete
.push_back(pkt
);
802 DPRINTF(DRAM
, "Done\n");
808 DRAMCtrl::activateBank(Tick act_tick
, uint8_t rank
, uint8_t bank
,
809 uint16_t row
, Bank
& bank_ref
)
811 assert(0 <= rank
&& rank
< ranksPerChannel
);
812 assert(actTicks
[rank
].size() == activationLimit
);
814 DPRINTF(DRAM
, "Activate at tick %d\n", act_tick
);
816 // update the open row
817 assert(bank_ref
.openRow
== Bank::NO_ROW
);
818 bank_ref
.openRow
= row
;
820 // start counting anew, this covers both the case when we
821 // auto-precharged, and when this access is forced to
823 bank_ref
.bytesAccessed
= 0;
824 bank_ref
.rowAccesses
= 0;
827 assert(numBanksActive
<= banksPerRank
* ranksPerChannel
);
829 DPRINTF(DRAM
, "Activate bank at tick %lld, now got %d active\n",
830 act_tick
, numBanksActive
);
832 // The next access has to respect tRAS for this bank
833 bank_ref
.preAllowedAt
= act_tick
+ tRAS
;
835 // Respect the row-to-column command delay
836 bank_ref
.colAllowedAt
= act_tick
+ tRCD
;
838 // start by enforcing tRRD
839 for(int i
= 0; i
< banksPerRank
; i
++) {
840 // next activate to any bank in this rank must not happen
842 banks
[rank
][i
].actAllowedAt
= std::max(act_tick
+ tRRD
,
843 banks
[rank
][i
].actAllowedAt
);
846 // next, we deal with tXAW, if the activation limit is disabled
848 if (actTicks
[rank
].empty())
852 if (actTicks
[rank
].back() && (act_tick
- actTicks
[rank
].back()) < tXAW
) {
853 panic("Got %d activates in window %d (%llu - %llu) which is smaller "
854 "than %llu\n", activationLimit
, act_tick
- actTicks
[rank
].back(),
855 act_tick
, actTicks
[rank
].back(), tXAW
);
858 // shift the times used for the book keeping, the last element
859 // (highest index) is the oldest one and hence the lowest value
860 actTicks
[rank
].pop_back();
862 // record an new activation (in the future)
863 actTicks
[rank
].push_front(act_tick
);
865 // cannot activate more than X times in time window tXAW, push the
866 // next one (the X + 1'st activate) to be tXAW away from the
867 // oldest in our window of X
868 if (actTicks
[rank
].back() && (act_tick
- actTicks
[rank
].back()) < tXAW
) {
869 DPRINTF(DRAM
, "Enforcing tXAW with X = %d, next activate no earlier "
870 "than %llu\n", activationLimit
, actTicks
[rank
].back() + tXAW
);
871 for(int j
= 0; j
< banksPerRank
; j
++)
872 // next activate must not happen before end of window
873 banks
[rank
][j
].actAllowedAt
=
874 std::max(actTicks
[rank
].back() + tXAW
,
875 banks
[rank
][j
].actAllowedAt
);
878 // at the point when this activate takes place, make sure we
879 // transition to the active power state
880 if (!activateEvent
.scheduled())
881 schedule(activateEvent
, act_tick
);
882 else if (activateEvent
.when() > act_tick
)
883 // move it sooner in time
884 reschedule(activateEvent
, act_tick
);
888 DRAMCtrl::processActivateEvent()
890 // we should transition to the active state as soon as any bank is active
891 if (pwrState
!= PWR_ACT
)
892 // note that at this point numBanksActive could be back at
893 // zero again due to a precharge scheduled in the future
894 schedulePowerEvent(PWR_ACT
, curTick());
898 DRAMCtrl::prechargeBank(Bank
& bank
, Tick pre_at
)
900 // make sure the bank has an open row
901 assert(bank
.openRow
!= Bank::NO_ROW
);
903 // sample the bytes per activate here since we are closing
905 bytesPerActivate
.sample(bank
.bytesAccessed
);
907 bank
.openRow
= Bank::NO_ROW
;
909 Tick pre_done_at
= pre_at
+ tRP
;
911 bank
.actAllowedAt
= std::max(bank
.actAllowedAt
, pre_done_at
);
913 assert(numBanksActive
!= 0);
916 DPRINTF(DRAM
, "Precharging bank at tick %lld, now got %d active\n",
917 pre_at
, numBanksActive
);
919 // if we look at the current number of active banks we might be
920 // tempted to think the DRAM is now idle, however this can be
921 // undone by an activate that is scheduled to happen before we
922 // would have reached the idle state, so schedule an event and
923 // rather check once we actually make it to the point in time when
924 // the (last) precharge takes place
925 if (!prechargeEvent
.scheduled())
926 schedule(prechargeEvent
, pre_done_at
);
927 else if (prechargeEvent
.when() < pre_done_at
)
928 reschedule(prechargeEvent
, pre_done_at
);
932 DRAMCtrl::processPrechargeEvent()
934 // if we reached zero, then special conditions apply as we track
935 // if all banks are precharged for the power models
936 if (numBanksActive
== 0) {
937 // we should transition to the idle state when the last bank
939 schedulePowerEvent(PWR_IDLE
, curTick());
944 DRAMCtrl::doDRAMAccess(DRAMPacket
* dram_pkt
)
946 DPRINTF(DRAM
, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
947 dram_pkt
->addr
, dram_pkt
->rank
, dram_pkt
->bank
, dram_pkt
->row
);
950 Bank
& bank
= dram_pkt
->bankRef
;
952 // for the state we need to track if it is a row hit or not
955 // respect any constraints on the command (e.g. tRCD or tCCD)
956 Tick cmd_at
= std::max(bank
.colAllowedAt
, curTick());
958 // Determine the access latency and update the bank state
959 if (bank
.openRow
== dram_pkt
->row
) {
964 // If there is a page open, precharge it.
965 if (bank
.openRow
!= Bank::NO_ROW
) {
966 prechargeBank(bank
, std::max(bank
.preAllowedAt
, curTick()));
969 // next we need to account for the delay in activating the
971 Tick act_tick
= std::max(bank
.actAllowedAt
, curTick());
973 // Record the activation and deal with all the global timing
974 // constraints caused be a new activation (tRRD and tXAW)
975 activateBank(act_tick
, dram_pkt
->rank
, dram_pkt
->bank
,
976 dram_pkt
->row
, bank
);
978 // issue the command as early as possible
979 cmd_at
= bank
.colAllowedAt
;
982 // we need to wait until the bus is available before we can issue
984 cmd_at
= std::max(cmd_at
, busBusyUntil
- tCL
);
986 // update the packet ready time
987 dram_pkt
->readyTime
= cmd_at
+ tCL
+ tBURST
;
989 // only one burst can use the bus at any one point in time
990 assert(dram_pkt
->readyTime
- busBusyUntil
>= tBURST
);
992 // not strictly necessary, but update the time for the next
993 // read/write (add a max with tCCD here)
994 bank
.colAllowedAt
= cmd_at
+ tBURST
;
996 // If this is a write, we also need to respect the write
997 // recovery time before a precharge
998 if (!dram_pkt
->isRead
) {
999 bank
.preAllowedAt
= std::max(bank
.preAllowedAt
,
1000 dram_pkt
->readyTime
+ tWR
);
1003 // increment the bytes accessed and the accesses per row
1004 bank
.bytesAccessed
+= burstSize
;
1007 // if we reached the max, then issue with an auto-precharge
1008 bool auto_precharge
= pageMgmt
== Enums::close
||
1009 bank
.rowAccesses
== maxAccessesPerRow
;
1011 // if we did not hit the limit, we might still want to
1013 if (!auto_precharge
&&
1014 (pageMgmt
== Enums::open_adaptive
||
1015 pageMgmt
== Enums::close_adaptive
)) {
1016 // a twist on the open and close page policies:
1017 // 1) open_adaptive page policy does not blindly keep the
1018 // page open, but close it if there are no row hits, and there
1019 // are bank conflicts in the queue
1020 // 2) close_adaptive page policy does not blindly close the
1021 // page, but closes it only if there are no row hits in the queue.
1022 // In this case, only force an auto precharge when there
1023 // are no same page hits in the queue
1024 bool got_more_hits
= false;
1025 bool got_bank_conflict
= false;
1027 // either look at the read queue or write queue
1028 const deque
<DRAMPacket
*>& queue
= dram_pkt
->isRead
? readQueue
:
1030 auto p
= queue
.begin();
1031 // make sure we are not considering the packet that we are
1032 // currently dealing with (which is the head of the queue)
1035 // keep on looking until we have found required condition or
1037 while (!(got_more_hits
&&
1038 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
)) &&
1040 bool same_rank_bank
= (dram_pkt
->rank
== (*p
)->rank
) &&
1041 (dram_pkt
->bank
== (*p
)->bank
);
1042 bool same_row
= dram_pkt
->row
== (*p
)->row
;
1043 got_more_hits
|= same_rank_bank
&& same_row
;
1044 got_bank_conflict
|= same_rank_bank
&& !same_row
;
1048 // auto pre-charge when either
1049 // 1) open_adaptive policy, we have not got any more hits, and
1050 // have a bank conflict
1051 // 2) close_adaptive policy and we have not got any more hits
1052 auto_precharge
= !got_more_hits
&&
1053 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
);
1056 // if this access should use auto-precharge, then we are
1058 if (auto_precharge
) {
1059 prechargeBank(bank
, std::max(curTick(), bank
.preAllowedAt
));
1061 DPRINTF(DRAM
, "Auto-precharged bank: %d\n", dram_pkt
->bankId
);
1065 busBusyUntil
= dram_pkt
->readyTime
;
1067 DPRINTF(DRAM
, "Access to %lld, ready at %lld bus busy until %lld.\n",
1068 dram_pkt
->addr
, dram_pkt
->readyTime
, busBusyUntil
);
1070 // Update the minimum timing between the requests, this is a
1071 // conservative estimate of when we have to schedule the next
1072 // request to not introduce any unecessary bubbles. In most cases
1073 // we will wake up sooner than we have to.
1074 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1076 // Update the stats and schedule the next request
1077 if (dram_pkt
->isRead
) {
1081 bytesReadDRAM
+= burstSize
;
1082 perBankRdBursts
[dram_pkt
->bankId
]++;
1084 // Update latency stats
1085 totMemAccLat
+= dram_pkt
->readyTime
- dram_pkt
->entryTime
;
1086 totBusLat
+= tBURST
;
1087 totQLat
+= cmd_at
- dram_pkt
->entryTime
;
1092 bytesWritten
+= burstSize
;
1093 perBankWrBursts
[dram_pkt
->bankId
]++;
1098 DRAMCtrl::moveToRespQ()
1100 // Remove from read queue
1101 DRAMPacket
* dram_pkt
= readQueue
.front();
1102 readQueue
.pop_front();
1105 assert(dram_pkt
->size
<= burstSize
);
1107 // Insert into response queue sorted by readyTime
1108 // It will be sent back to the requestor at its
1110 if (respQueue
.empty()) {
1111 respQueue
.push_front(dram_pkt
);
1112 assert(!respondEvent
.scheduled());
1113 assert(dram_pkt
->readyTime
>= curTick());
1114 schedule(respondEvent
, dram_pkt
->readyTime
);
1117 auto i
= respQueue
.begin();
1118 while (!done
&& i
!= respQueue
.end()) {
1119 if ((*i
)->readyTime
> dram_pkt
->readyTime
) {
1120 respQueue
.insert(i
, dram_pkt
);
1127 respQueue
.push_back(dram_pkt
);
1129 assert(respondEvent
.scheduled());
1131 if (respQueue
.front()->readyTime
< respondEvent
.when()) {
1132 assert(respQueue
.front()->readyTime
>= curTick());
1133 reschedule(respondEvent
, respQueue
.front()->readyTime
);
1139 DRAMCtrl::processNextReqEvent()
1141 if (busState
== READ_TO_WRITE
) {
1142 DPRINTF(DRAM
, "Switching to writes after %d reads with %d reads "
1143 "waiting\n", readsThisTime
, readQueue
.size());
1145 // sample and reset the read-related stats as we are now
1146 // transitioning to writes, and all reads are done
1147 rdPerTurnAround
.sample(readsThisTime
);
1150 // now proceed to do the actual writes
1152 } else if (busState
== WRITE_TO_READ
) {
1153 DPRINTF(DRAM
, "Switching to reads after %d writes with %d writes "
1154 "waiting\n", writesThisTime
, writeQueue
.size());
1156 wrPerTurnAround
.sample(writesThisTime
);
1162 if (refreshState
!= REF_IDLE
) {
1163 // if a refresh waiting for this event loop to finish, then hand
1164 // over now, and do not schedule a new nextReqEvent
1165 if (refreshState
== REF_DRAIN
) {
1166 DPRINTF(DRAM
, "Refresh drain done, now precharging\n");
1168 refreshState
= REF_PRE
;
1170 // hand control back to the refresh event loop
1171 schedule(refreshEvent
, curTick());
1174 // let the refresh finish before issuing any further requests
1178 // when we get here it is either a read or a write
1179 if (busState
== READ
) {
1181 // track if we should switch or not
1182 bool switch_to_writes
= false;
1184 if (readQueue
.empty()) {
1185 // In the case there is no read request to go next,
1186 // trigger writes if we have passed the low threshold (or
1187 // if we are draining)
1188 if (!writeQueue
.empty() &&
1189 (drainManager
|| writeQueue
.size() > writeLowThreshold
)) {
1191 switch_to_writes
= true;
1193 // check if we are drained
1194 if (respQueue
.empty () && drainManager
) {
1195 drainManager
->signalDrainDone();
1196 drainManager
= NULL
;
1199 // nothing to do, not even any point in scheduling an
1200 // event for the next request
1204 // Figure out which read request goes next, and move it to the
1205 // front of the read queue
1206 chooseNext(readQueue
);
1208 doDRAMAccess(readQueue
.front());
1210 // At this point we're done dealing with the request
1211 // It will be moved to a separate response queue with a
1212 // correct readyTime, and eventually be sent back at that
1216 // we have so many writes that we have to transition
1217 if (writeQueue
.size() > writeHighThreshold
) {
1218 switch_to_writes
= true;
1222 // switching to writes, either because the read queue is empty
1223 // and the writes have passed the low threshold (or we are
1224 // draining), or because the writes hit the hight threshold
1225 if (switch_to_writes
) {
1226 // transition to writing
1227 busState
= READ_TO_WRITE
;
1229 // add a bubble to the data bus, as defined by the
1231 busBusyUntil
+= tRTW
;
1233 // update the minimum timing between the requests,
1234 // this shifts us back in time far enough to do any
1236 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1239 chooseNext(writeQueue
);
1240 DRAMPacket
* dram_pkt
= writeQueue
.front();
1242 assert(dram_pkt
->size
<= burstSize
);
1243 doDRAMAccess(dram_pkt
);
1245 writeQueue
.pop_front();
1248 // If we emptied the write queue, or got sufficiently below the
1249 // threshold (using the minWritesPerSwitch as the hysteresis) and
1250 // are not draining, or we have reads waiting and have done enough
1251 // writes, then switch to reads.
1252 if (writeQueue
.empty() ||
1253 (writeQueue
.size() + minWritesPerSwitch
< writeLowThreshold
&&
1255 (!readQueue
.empty() && writesThisTime
>= minWritesPerSwitch
)) {
1256 // turn the bus back around for reads again
1257 busState
= WRITE_TO_READ
;
1259 // note that the we switch back to reads also in the idle
1260 // case, which eventually will check for any draining and
1261 // also pause any further scheduling if there is really
1264 // here we get a bit creative and shift the bus busy time not
1265 // just the tWTR, but also a CAS latency to capture the fact
1266 // that we are allowed to prepare a new bank, but not issue a
1267 // read command until after tWTR, in essence we capture a
1268 // bubble on the data bus that is tWTR + tCL
1269 busBusyUntil
+= tWTR
+ tCL
;
1271 // update the minimum timing between the requests, this shifts
1272 // us back in time far enough to do any bank preparation
1273 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1277 schedule(nextReqEvent
, std::max(nextReqTime
, curTick()));
1279 // If there is space available and we have writes waiting then let
1280 // them retry. This is done here to ensure that the retry does not
1281 // cause a nextReqEvent to be scheduled before we do so as part of
1282 // the next request processing
1283 if (retryWrReq
&& writeQueue
.size() < writeBufferSize
) {
1290 DRAMCtrl::minBankActAt(const deque
<DRAMPacket
*>& queue
) const
1292 uint64_t bank_mask
= 0;
1293 Tick min_act_at
= MaxTick
;
1295 // deterimne if we have queued transactions targetting a
1297 vector
<bool> got_waiting(ranksPerChannel
* banksPerRank
, false);
1298 for (auto p
= queue
.begin(); p
!= queue
.end(); ++p
) {
1299 got_waiting
[(*p
)->bankId
] = true;
1302 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1303 for (int j
= 0; j
< banksPerRank
; j
++) {
1304 uint8_t bank_id
= i
* banksPerRank
+ j
;
1306 // if we have waiting requests for the bank, and it is
1307 // amongst the first available, update the mask
1308 if (got_waiting
[bank_id
]) {
1309 // simplistic approximation of when the bank can issue
1310 // an activate, ignoring any rank-to-rank switching
1312 Tick act_at
= banks
[i
][j
].openRow
== Bank::NO_ROW
?
1313 banks
[i
][j
].actAllowedAt
:
1314 std::max(banks
[i
][j
].preAllowedAt
, curTick()) + tRP
;
1316 if (act_at
<= min_act_at
) {
1317 // reset bank mask if new minimum is found
1318 if (act_at
< min_act_at
)
1320 // set the bit corresponding to the available bank
1321 replaceBits(bank_mask
, bank_id
, bank_id
, 1);
1322 min_act_at
= act_at
;
1332 DRAMCtrl::processRefreshEvent()
1334 // when first preparing the refresh, remember when it was due
1335 if (refreshState
== REF_IDLE
) {
1336 // remember when the refresh is due
1337 refreshDueAt
= curTick();
1340 refreshState
= REF_DRAIN
;
1342 DPRINTF(DRAM
, "Refresh due\n");
1345 // let any scheduled read or write go ahead, after which it will
1346 // hand control back to this event loop
1347 if (refreshState
== REF_DRAIN
) {
1348 if (nextReqEvent
.scheduled()) {
1349 // hand control over to the request loop until it is
1351 DPRINTF(DRAM
, "Refresh awaiting draining\n");
1355 refreshState
= REF_PRE
;
1359 // at this point, ensure that all banks are precharged
1360 if (refreshState
== REF_PRE
) {
1361 // precharge any active bank if we are not already in the idle
1363 if (pwrState
!= PWR_IDLE
) {
1364 DPRINTF(DRAM
, "Precharging all\n");
1365 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1366 for (int j
= 0; j
< banksPerRank
; j
++) {
1367 if (banks
[i
][j
].openRow
!= Bank::NO_ROW
) {
1368 // respect both causality and any existing bank
1370 Tick pre_at
= std::max(banks
[i
][j
].preAllowedAt
,
1373 prechargeBank(banks
[i
][j
], pre_at
);
1378 DPRINTF(DRAM
, "All banks already precharged, starting refresh\n");
1380 // go ahead and kick the power state machine into gear if
1381 // we are already idle
1382 schedulePowerEvent(PWR_REF
, curTick());
1385 refreshState
= REF_RUN
;
1386 assert(numBanksActive
== 0);
1388 // wait for all banks to be precharged, at which point the
1389 // power state machine will transition to the idle state, and
1390 // automatically move to a refresh, at that point it will also
1391 // call this method to get the refresh event loop going again
1395 // last but not least we perform the actual refresh
1396 if (refreshState
== REF_RUN
) {
1397 // should never get here with any banks active
1398 assert(numBanksActive
== 0);
1399 assert(pwrState
== PWR_REF
);
1401 Tick ref_done_at
= curTick() + tRFC
;
1403 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1404 for (int j
= 0; j
< banksPerRank
; j
++) {
1405 banks
[i
][j
].actAllowedAt
= ref_done_at
;
1409 // make sure we did not wait so long that we cannot make up
1411 if (refreshDueAt
+ tREFI
< ref_done_at
) {
1412 fatal("Refresh was delayed so long we cannot catch up\n");
1415 // compensate for the delay in actually performing the refresh
1416 // when scheduling the next one
1417 schedule(refreshEvent
, refreshDueAt
+ tREFI
- tRP
);
1419 assert(!powerEvent
.scheduled());
1421 // move to the idle power state once the refresh is done, this
1422 // will also move the refresh state machine to the refresh
1424 schedulePowerEvent(PWR_IDLE
, ref_done_at
);
1426 DPRINTF(DRAMState
, "Refresh done at %llu and next refresh at %llu\n",
1427 ref_done_at
, refreshDueAt
+ tREFI
);
1432 DRAMCtrl::schedulePowerEvent(PowerState pwr_state
, Tick tick
)
1434 // respect causality
1435 assert(tick
>= curTick());
1437 if (!powerEvent
.scheduled()) {
1438 DPRINTF(DRAMState
, "Scheduling power event at %llu to state %d\n",
1441 // insert the new transition
1442 pwrStateTrans
= pwr_state
;
1444 schedule(powerEvent
, tick
);
1446 panic("Scheduled power event at %llu to state %d, "
1447 "with scheduled event at %llu to %d\n", tick
, pwr_state
,
1448 powerEvent
.when(), pwrStateTrans
);
1453 DRAMCtrl::processPowerEvent()
1455 // remember where we were, and for how long
1456 Tick duration
= curTick() - pwrStateTick
;
1457 PowerState prev_state
= pwrState
;
1459 // update the accounting
1460 pwrStateTime
[prev_state
] += duration
;
1462 pwrState
= pwrStateTrans
;
1463 pwrStateTick
= curTick();
1465 if (pwrState
== PWR_IDLE
) {
1466 DPRINTF(DRAMState
, "All banks precharged\n");
1468 // if we were refreshing, make sure we start scheduling requests again
1469 if (prev_state
== PWR_REF
) {
1470 DPRINTF(DRAMState
, "Was refreshing for %llu ticks\n", duration
);
1471 assert(pwrState
== PWR_IDLE
);
1473 // kick things into action again
1474 refreshState
= REF_IDLE
;
1475 assert(!nextReqEvent
.scheduled());
1476 schedule(nextReqEvent
, curTick());
1478 assert(prev_state
== PWR_ACT
);
1480 // if we have a pending refresh, and are now moving to
1481 // the idle state, direclty transition to a refresh
1482 if (refreshState
== REF_RUN
) {
1483 // there should be nothing waiting at this point
1484 assert(!powerEvent
.scheduled());
1486 // update the state in zero time and proceed below
1492 // we transition to the refresh state, let the refresh state
1493 // machine know of this state update and let it deal with the
1494 // scheduling of the next power state transition as well as the
1495 // following refresh
1496 if (pwrState
== PWR_REF
) {
1497 DPRINTF(DRAMState
, "Refreshing\n");
1498 // kick the refresh event loop into action again, and that
1499 // in turn will schedule a transition to the idle power
1500 // state once the refresh is done
1501 assert(refreshState
== REF_RUN
);
1502 processRefreshEvent();
1507 DRAMCtrl::regStats()
1509 using namespace Stats
;
1511 AbstractMemory::regStats();
1514 .name(name() + ".readReqs")
1515 .desc("Number of read requests accepted");
1518 .name(name() + ".writeReqs")
1519 .desc("Number of write requests accepted");
1522 .name(name() + ".readBursts")
1523 .desc("Number of DRAM read bursts, "
1524 "including those serviced by the write queue");
1527 .name(name() + ".writeBursts")
1528 .desc("Number of DRAM write bursts, "
1529 "including those merged in the write queue");
1532 .name(name() + ".servicedByWrQ")
1533 .desc("Number of DRAM read bursts serviced by the write queue");
1536 .name(name() + ".mergedWrBursts")
1537 .desc("Number of DRAM write bursts merged with an existing one");
1540 .name(name() + ".neitherReadNorWriteReqs")
1541 .desc("Number of requests that are neither read nor write");
1544 .init(banksPerRank
* ranksPerChannel
)
1545 .name(name() + ".perBankRdBursts")
1546 .desc("Per bank write bursts");
1549 .init(banksPerRank
* ranksPerChannel
)
1550 .name(name() + ".perBankWrBursts")
1551 .desc("Per bank write bursts");
1554 .name(name() + ".avgRdQLen")
1555 .desc("Average read queue length when enqueuing")
1559 .name(name() + ".avgWrQLen")
1560 .desc("Average write queue length when enqueuing")
1564 .name(name() + ".totQLat")
1565 .desc("Total ticks spent queuing");
1568 .name(name() + ".totBusLat")
1569 .desc("Total ticks spent in databus transfers");
1572 .name(name() + ".totMemAccLat")
1573 .desc("Total ticks spent from burst creation until serviced "
1577 .name(name() + ".avgQLat")
1578 .desc("Average queueing delay per DRAM burst")
1581 avgQLat
= totQLat
/ (readBursts
- servicedByWrQ
);
1584 .name(name() + ".avgBusLat")
1585 .desc("Average bus latency per DRAM burst")
1588 avgBusLat
= totBusLat
/ (readBursts
- servicedByWrQ
);
1591 .name(name() + ".avgMemAccLat")
1592 .desc("Average memory access latency per DRAM burst")
1595 avgMemAccLat
= totMemAccLat
/ (readBursts
- servicedByWrQ
);
1598 .name(name() + ".numRdRetry")
1599 .desc("Number of times read queue was full causing retry");
1602 .name(name() + ".numWrRetry")
1603 .desc("Number of times write queue was full causing retry");
1606 .name(name() + ".readRowHits")
1607 .desc("Number of row buffer hits during reads");
1610 .name(name() + ".writeRowHits")
1611 .desc("Number of row buffer hits during writes");
1614 .name(name() + ".readRowHitRate")
1615 .desc("Row buffer hit rate for reads")
1618 readRowHitRate
= (readRowHits
/ (readBursts
- servicedByWrQ
)) * 100;
1621 .name(name() + ".writeRowHitRate")
1622 .desc("Row buffer hit rate for writes")
1625 writeRowHitRate
= (writeRowHits
/ (writeBursts
- mergedWrBursts
)) * 100;
1628 .init(ceilLog2(burstSize
) + 1)
1629 .name(name() + ".readPktSize")
1630 .desc("Read request sizes (log2)");
1633 .init(ceilLog2(burstSize
) + 1)
1634 .name(name() + ".writePktSize")
1635 .desc("Write request sizes (log2)");
1638 .init(readBufferSize
)
1639 .name(name() + ".rdQLenPdf")
1640 .desc("What read queue length does an incoming req see");
1643 .init(writeBufferSize
)
1644 .name(name() + ".wrQLenPdf")
1645 .desc("What write queue length does an incoming req see");
1648 .init(maxAccessesPerRow
)
1649 .name(name() + ".bytesPerActivate")
1650 .desc("Bytes accessed per row activation")
1654 .init(readBufferSize
)
1655 .name(name() + ".rdPerTurnAround")
1656 .desc("Reads before turning the bus around for writes")
1660 .init(writeBufferSize
)
1661 .name(name() + ".wrPerTurnAround")
1662 .desc("Writes before turning the bus around for reads")
1666 .name(name() + ".bytesReadDRAM")
1667 .desc("Total number of bytes read from DRAM");
1670 .name(name() + ".bytesReadWrQ")
1671 .desc("Total number of bytes read from write queue");
1674 .name(name() + ".bytesWritten")
1675 .desc("Total number of bytes written to DRAM");
1678 .name(name() + ".bytesReadSys")
1679 .desc("Total read bytes from the system interface side");
1682 .name(name() + ".bytesWrittenSys")
1683 .desc("Total written bytes from the system interface side");
1686 .name(name() + ".avgRdBW")
1687 .desc("Average DRAM read bandwidth in MiByte/s")
1690 avgRdBW
= (bytesReadDRAM
/ 1000000) / simSeconds
;
1693 .name(name() + ".avgWrBW")
1694 .desc("Average achieved write bandwidth in MiByte/s")
1697 avgWrBW
= (bytesWritten
/ 1000000) / simSeconds
;
1700 .name(name() + ".avgRdBWSys")
1701 .desc("Average system read bandwidth in MiByte/s")
1704 avgRdBWSys
= (bytesReadSys
/ 1000000) / simSeconds
;
1707 .name(name() + ".avgWrBWSys")
1708 .desc("Average system write bandwidth in MiByte/s")
1711 avgWrBWSys
= (bytesWrittenSys
/ 1000000) / simSeconds
;
1714 .name(name() + ".peakBW")
1715 .desc("Theoretical peak bandwidth in MiByte/s")
1718 peakBW
= (SimClock::Frequency
/ tBURST
) * burstSize
/ 1000000;
1721 .name(name() + ".busUtil")
1722 .desc("Data bus utilization in percentage")
1725 busUtil
= (avgRdBW
+ avgWrBW
) / peakBW
* 100;
1728 .name(name() + ".totGap")
1729 .desc("Total gap between requests");
1732 .name(name() + ".avgGap")
1733 .desc("Average gap between requests")
1736 avgGap
= totGap
/ (readReqs
+ writeReqs
);
1738 // Stats for DRAM Power calculation based on Micron datasheet
1740 .name(name() + ".busUtilRead")
1741 .desc("Data bus utilization in percentage for reads")
1744 busUtilRead
= avgRdBW
/ peakBW
* 100;
1747 .name(name() + ".busUtilWrite")
1748 .desc("Data bus utilization in percentage for writes")
1751 busUtilWrite
= avgWrBW
/ peakBW
* 100;
1754 .name(name() + ".pageHitRate")
1755 .desc("Row buffer hit rate, read and write combined")
1758 pageHitRate
= (writeRowHits
+ readRowHits
) /
1759 (writeBursts
- mergedWrBursts
+ readBursts
- servicedByWrQ
) * 100;
1763 .name(name() + ".memoryStateTime")
1764 .desc("Time in different power states");
1765 pwrStateTime
.subname(0, "IDLE");
1766 pwrStateTime
.subname(1, "REF");
1767 pwrStateTime
.subname(2, "PRE_PDN");
1768 pwrStateTime
.subname(3, "ACT");
1769 pwrStateTime
.subname(4, "ACT_PDN");
1773 DRAMCtrl::recvFunctional(PacketPtr pkt
)
1775 // rely on the abstract memory
1776 functionalAccess(pkt
);
1780 DRAMCtrl::getSlavePort(const string
&if_name
, PortID idx
)
1782 if (if_name
!= "port") {
1783 return MemObject::getSlavePort(if_name
, idx
);
1790 DRAMCtrl::drain(DrainManager
*dm
)
1792 unsigned int count
= port
.drain(dm
);
1794 // if there is anything in any of our internal queues, keep track
1796 if (!(writeQueue
.empty() && readQueue
.empty() &&
1797 respQueue
.empty())) {
1798 DPRINTF(Drain
, "DRAM controller not drained, write: %d, read: %d,"
1799 " resp: %d\n", writeQueue
.size(), readQueue
.size(),
1804 // the only part that is not drained automatically over time
1805 // is the write queue, thus kick things into action if needed
1806 if (!writeQueue
.empty() && !nextReqEvent
.scheduled()) {
1807 schedule(nextReqEvent
, curTick());
1812 setDrainState(Drainable::Draining
);
1814 setDrainState(Drainable::Drained
);
1818 DRAMCtrl::MemoryPort::MemoryPort(const std::string
& name
, DRAMCtrl
& _memory
)
1819 : QueuedSlavePort(name
, &_memory
, queue
), queue(_memory
, *this),
1824 DRAMCtrl::MemoryPort::getAddrRanges() const
1826 AddrRangeList ranges
;
1827 ranges
.push_back(memory
.getAddrRange());
1832 DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt
)
1834 pkt
->pushLabel(memory
.name());
1836 if (!queue
.checkFunctional(pkt
)) {
1837 // Default implementation of SimpleTimingPort::recvFunctional()
1838 // calls recvAtomic() and throws away the latency; we can save a
1839 // little here by just not calculating the latency.
1840 memory
.recvFunctional(pkt
);
1847 DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt
)
1849 return memory
.recvAtomic(pkt
);
1853 DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt
)
1855 // pass it to the memory controller
1856 return memory
.recvTimingReq(pkt
);
1860 DRAMCtrlParams::create()
1862 return new DRAMCtrl(this);