2 * Copyright (c) 2010-2016 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
47 #include "mem/dram_ctrl.hh"
49 #include "base/bitfield.hh"
50 #include "base/trace.hh"
51 #include "debug/DRAM.hh"
52 #include "debug/DRAMPower.hh"
53 #include "debug/DRAMState.hh"
54 #include "debug/Drain.hh"
55 #include "sim/system.hh"
60 DRAMCtrl::DRAMCtrl(const DRAMCtrlParams
* p
) :
62 port(name() + ".port", *this), isTimingMode(false),
63 retryRdReq(false), retryWrReq(false),
66 nextReqEvent(this), respondEvent(this),
67 deviceSize(p
->device_size
),
68 deviceBusWidth(p
->device_bus_width
), burstLength(p
->burst_length
),
69 deviceRowBufferSize(p
->device_rowbuffer_size
),
70 devicesPerRank(p
->devices_per_rank
),
71 burstSize((devicesPerRank
* burstLength
* deviceBusWidth
) / 8),
72 rowBufferSize(devicesPerRank
* deviceRowBufferSize
),
73 columnsPerRowBuffer(rowBufferSize
/ burstSize
),
74 columnsPerStripe(range
.interleaved() ? range
.granularity() / burstSize
: 1),
75 ranksPerChannel(p
->ranks_per_channel
),
76 bankGroupsPerRank(p
->bank_groups_per_rank
),
77 bankGroupArch(p
->bank_groups_per_rank
> 0),
78 banksPerRank(p
->banks_per_rank
), channels(p
->channels
), rowsPerBank(0),
79 readBufferSize(p
->read_buffer_size
),
80 writeBufferSize(p
->write_buffer_size
),
81 writeHighThreshold(writeBufferSize
* p
->write_high_thresh_perc
/ 100.0),
82 writeLowThreshold(writeBufferSize
* p
->write_low_thresh_perc
/ 100.0),
83 minWritesPerSwitch(p
->min_writes_per_switch
),
84 writesThisTime(0), readsThisTime(0),
85 tCK(p
->tCK
), tWTR(p
->tWTR
), tRTW(p
->tRTW
), tCS(p
->tCS
), tBURST(p
->tBURST
),
86 tCCD_L(p
->tCCD_L
), tRCD(p
->tRCD
), tCL(p
->tCL
), tRP(p
->tRP
), tRAS(p
->tRAS
),
87 tWR(p
->tWR
), tRTP(p
->tRTP
), tRFC(p
->tRFC
), tREFI(p
->tREFI
), tRRD(p
->tRRD
),
88 tRRD_L(p
->tRRD_L
), tXAW(p
->tXAW
), tXP(p
->tXP
), tXS(p
->tXS
),
89 activationLimit(p
->activation_limit
),
90 memSchedPolicy(p
->mem_sched_policy
), addrMapping(p
->addr_mapping
),
91 pageMgmt(p
->page_policy
),
92 maxAccessesPerRow(p
->max_accesses_per_row
),
93 frontendLatency(p
->static_frontend_latency
),
94 backendLatency(p
->static_backend_latency
),
95 busBusyUntil(0), prevArrival(0),
96 nextReqTime(0), activeRank(0), timeStampOffset(0)
98 // sanity check the ranks since we rely on bit slicing for the
100 fatal_if(!isPowerOf2(ranksPerChannel
), "DRAM rank count of %d is not "
101 "allowed, must be a power of two\n", ranksPerChannel
);
103 fatal_if(!isPowerOf2(burstSize
), "DRAM burst size %d is not allowed, "
104 "must be a power of two\n", burstSize
);
106 for (int i
= 0; i
< ranksPerChannel
; i
++) {
107 Rank
* rank
= new Rank(*this, p
);
108 ranks
.push_back(rank
);
110 rank
->actTicks
.resize(activationLimit
, 0);
111 rank
->banks
.resize(banksPerRank
);
114 for (int b
= 0; b
< banksPerRank
; b
++) {
115 rank
->banks
[b
].bank
= b
;
116 // GDDR addressing of banks to BG is linear.
117 // Here we assume that all DRAM generations address bank groups as
120 // Simply assign lower bits to bank group in order to
121 // rotate across bank groups as banks are incremented
122 // e.g. with 4 banks per bank group and 16 banks total:
123 // banks 0,4,8,12 are in bank group 0
124 // banks 1,5,9,13 are in bank group 1
125 // banks 2,6,10,14 are in bank group 2
126 // banks 3,7,11,15 are in bank group 3
127 rank
->banks
[b
].bankgr
= b
% bankGroupsPerRank
;
129 // No bank groups; simply assign to bank number
130 rank
->banks
[b
].bankgr
= b
;
135 // perform a basic check of the write thresholds
136 if (p
->write_low_thresh_perc
>= p
->write_high_thresh_perc
)
137 fatal("Write buffer low threshold %d must be smaller than the "
138 "high threshold %d\n", p
->write_low_thresh_perc
,
139 p
->write_high_thresh_perc
);
141 // determine the rows per bank by looking at the total capacity
142 uint64_t capacity
= ULL(1) << ceilLog2(AbstractMemory::size());
144 // determine the dram actual capacity from the DRAM config in Mbytes
145 uint64_t deviceCapacity
= deviceSize
/ (1024 * 1024) * devicesPerRank
*
148 // if actual DRAM size does not match memory capacity in system warn!
149 if (deviceCapacity
!= capacity
/ (1024 * 1024))
150 warn("DRAM device capacity (%d Mbytes) does not match the "
151 "address range assigned (%d Mbytes)\n", deviceCapacity
,
152 capacity
/ (1024 * 1024));
154 DPRINTF(DRAM
, "Memory capacity %lld (%lld) bytes\n", capacity
,
155 AbstractMemory::size());
157 DPRINTF(DRAM
, "Row buffer size %d bytes with %d columns per row buffer\n",
158 rowBufferSize
, columnsPerRowBuffer
);
160 rowsPerBank
= capacity
/ (rowBufferSize
* banksPerRank
* ranksPerChannel
);
162 // some basic sanity checks
163 if (tREFI
<= tRP
|| tREFI
<= tRFC
) {
164 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
168 // basic bank group architecture checks ->
170 // must have at least one bank per bank group
171 if (bankGroupsPerRank
> banksPerRank
) {
172 fatal("banks per rank (%d) must be equal to or larger than "
173 "banks groups per rank (%d)\n",
174 banksPerRank
, bankGroupsPerRank
);
176 // must have same number of banks in each bank group
177 if ((banksPerRank
% bankGroupsPerRank
) != 0) {
178 fatal("Banks per rank (%d) must be evenly divisible by bank groups "
179 "per rank (%d) for equal banks per bank group\n",
180 banksPerRank
, bankGroupsPerRank
);
182 // tCCD_L should be greater than minimal, back-to-back burst delay
183 if (tCCD_L
<= tBURST
) {
184 fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
185 "bank groups per rank (%d) is greater than 1\n",
186 tCCD_L
, tBURST
, bankGroupsPerRank
);
188 // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
189 // some datasheets might specify it equal to tRRD
191 fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
192 "bank groups per rank (%d) is greater than 1\n",
193 tRRD_L
, tRRD
, bankGroupsPerRank
);
202 AbstractMemory::init();
204 if (!port
.isConnected()) {
205 fatal("DRAMCtrl %s is unconnected!\n", name());
207 port
.sendRangeChange();
210 // a bit of sanity checks on the interleaving, save it for here to
211 // ensure that the system pointer is initialised
212 if (range
.interleaved()) {
213 if (channels
!= range
.stripes())
214 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
215 name(), range
.stripes(), channels
);
217 if (addrMapping
== Enums::RoRaBaChCo
) {
218 if (rowBufferSize
!= range
.granularity()) {
219 fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
220 "address map\n", name());
222 } else if (addrMapping
== Enums::RoRaBaCoCh
||
223 addrMapping
== Enums::RoCoRaBaCh
) {
224 // for the interleavings with channel bits in the bottom,
225 // if the system uses a channel striping granularity that
226 // is larger than the DRAM burst size, then map the
227 // sequential accesses within a stripe to a number of
228 // columns in the DRAM, effectively placing some of the
229 // lower-order column bits as the least-significant bits
230 // of the address (above the ones denoting the burst size)
231 assert(columnsPerStripe
>= 1);
233 // channel striping has to be done at a granularity that
234 // is equal or larger to a cache line
235 if (system()->cacheLineSize() > range
.granularity()) {
236 fatal("Channel interleaving of %s must be at least as large "
237 "as the cache line size\n", name());
240 // ...and equal or smaller than the row-buffer size
241 if (rowBufferSize
< range
.granularity()) {
242 fatal("Channel interleaving of %s must be at most as large "
243 "as the row-buffer size\n", name());
245 // this is essentially the check above, so just to be sure
246 assert(columnsPerStripe
<= columnsPerRowBuffer
);
254 // remember the memory system mode of operation
255 isTimingMode
= system()->isTimingMode();
258 // timestamp offset should be in clock cycles for DRAMPower
259 timeStampOffset
= divCeil(curTick(), tCK
);
261 // update the start tick for the precharge accounting to the
263 for (auto r
: ranks
) {
264 r
->startup(curTick() + tREFI
- tRP
);
267 // shift the bus busy time sufficiently far ahead that we never
268 // have to worry about negative values when computing the time for
269 // the next request, this will add an insignificant bubble at the
270 // start of simulation
271 busBusyUntil
= curTick() + tRP
+ tRCD
+ tCL
;
276 DRAMCtrl::recvAtomic(PacketPtr pkt
)
278 DPRINTF(DRAM
, "recvAtomic: %s 0x%x\n", pkt
->cmdString(), pkt
->getAddr());
280 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
283 // do the actual memory access and turn the packet into a response
287 if (pkt
->hasData()) {
288 // this value is not supposed to be accurate, just enough to
289 // keep things going, mimic a closed page
290 latency
= tRP
+ tRCD
+ tCL
;
296 DRAMCtrl::readQueueFull(unsigned int neededEntries
) const
298 DPRINTF(DRAM
, "Read queue limit %d, current size %d, entries needed %d\n",
299 readBufferSize
, readQueue
.size() + respQueue
.size(),
303 (readQueue
.size() + respQueue
.size() + neededEntries
) > readBufferSize
;
307 DRAMCtrl::writeQueueFull(unsigned int neededEntries
) const
309 DPRINTF(DRAM
, "Write queue limit %d, current size %d, entries needed %d\n",
310 writeBufferSize
, writeQueue
.size(), neededEntries
);
311 return (writeQueue
.size() + neededEntries
) > writeBufferSize
;
314 DRAMCtrl::DRAMPacket
*
315 DRAMCtrl::decodeAddr(PacketPtr pkt
, Addr dramPktAddr
, unsigned size
,
318 // decode the address based on the address mapping scheme, with
319 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
320 // channel, respectively
323 // use a 64-bit unsigned during the computations as the row is
324 // always the top bits, and check before creating the DRAMPacket
327 // truncate the address to a DRAM burst, which makes it unique to
328 // a specific column, row, bank, rank and channel
329 Addr addr
= dramPktAddr
/ burstSize
;
331 // we have removed the lowest order address bits that denote the
332 // position within the column
333 if (addrMapping
== Enums::RoRaBaChCo
) {
334 // the lowest order bits denote the column to ensure that
335 // sequential cache lines occupy the same row
336 addr
= addr
/ columnsPerRowBuffer
;
338 // take out the channel part of the address
339 addr
= addr
/ channels
;
341 // after the channel bits, get the bank bits to interleave
343 bank
= addr
% banksPerRank
;
344 addr
= addr
/ banksPerRank
;
346 // after the bank, we get the rank bits which thus interleaves
348 rank
= addr
% ranksPerChannel
;
349 addr
= addr
/ ranksPerChannel
;
351 // lastly, get the row bits, no need to remove them from addr
352 row
= addr
% rowsPerBank
;
353 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
354 // take out the lower-order column bits
355 addr
= addr
/ columnsPerStripe
;
357 // take out the channel part of the address
358 addr
= addr
/ channels
;
360 // next, the higher-order column bites
361 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
363 // after the column bits, we get the bank bits to interleave
365 bank
= addr
% banksPerRank
;
366 addr
= addr
/ banksPerRank
;
368 // after the bank, we get the rank bits which thus interleaves
370 rank
= addr
% ranksPerChannel
;
371 addr
= addr
/ ranksPerChannel
;
373 // lastly, get the row bits, no need to remove them from addr
374 row
= addr
% rowsPerBank
;
375 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
376 // optimise for closed page mode and utilise maximum
377 // parallelism of the DRAM (at the cost of power)
379 // take out the lower-order column bits
380 addr
= addr
/ columnsPerStripe
;
382 // take out the channel part of the address, not that this has
383 // to match with how accesses are interleaved between the
384 // controllers in the address mapping
385 addr
= addr
/ channels
;
387 // start with the bank bits, as this provides the maximum
388 // opportunity for parallelism between requests
389 bank
= addr
% banksPerRank
;
390 addr
= addr
/ banksPerRank
;
392 // next get the rank bits
393 rank
= addr
% ranksPerChannel
;
394 addr
= addr
/ ranksPerChannel
;
396 // next, the higher-order column bites
397 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
399 // lastly, get the row bits, no need to remove them from addr
400 row
= addr
% rowsPerBank
;
402 panic("Unknown address mapping policy chosen!");
404 assert(rank
< ranksPerChannel
);
405 assert(bank
< banksPerRank
);
406 assert(row
< rowsPerBank
);
407 assert(row
< Bank::NO_ROW
);
409 DPRINTF(DRAM
, "Address: %lld Rank %d Bank %d Row %d\n",
410 dramPktAddr
, rank
, bank
, row
);
412 // create the corresponding DRAM packet with the entry time and
413 // ready time set to the current tick, the latter will be updated
415 uint16_t bank_id
= banksPerRank
* rank
+ bank
;
416 return new DRAMPacket(pkt
, isRead
, rank
, bank
, row
, bank_id
, dramPktAddr
,
417 size
, ranks
[rank
]->banks
[bank
], *ranks
[rank
]);
421 DRAMCtrl::addToReadQueue(PacketPtr pkt
, unsigned int pktCount
)
423 // only add to the read queue here. whenever the request is
424 // eventually done, set the readyTime, and call schedule()
425 assert(!pkt
->isWrite());
427 assert(pktCount
!= 0);
429 // if the request size is larger than burst size, the pkt is split into
430 // multiple DRAM packets
431 // Note if the pkt starting address is not aligened to burst size, the
432 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
433 // are aligned to burst size boundaries. This is to ensure we accurately
434 // check read packets against packets in write queue.
435 Addr addr
= pkt
->getAddr();
436 unsigned pktsServicedByWrQ
= 0;
437 BurstHelper
* burst_helper
= NULL
;
438 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
439 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
440 pkt
->getAddr() + pkt
->getSize()) - addr
;
441 readPktSize
[ceilLog2(size
)]++;
444 // First check write buffer to see if the data is already at
446 bool foundInWrQ
= false;
447 Addr burst_addr
= burstAlign(addr
);
448 // if the burst address is not present then there is no need
449 // looking any further
450 if (isInWriteQueue
.find(burst_addr
) != isInWriteQueue
.end()) {
451 for (const auto& p
: writeQueue
) {
452 // check if the read is subsumed in the write queue
453 // packet we are looking at
454 if (p
->addr
<= addr
&& (addr
+ size
) <= (p
->addr
+ p
->size
)) {
458 DPRINTF(DRAM
, "Read to addr %lld with size %d serviced by "
459 "write queue\n", addr
, size
);
460 bytesReadWrQ
+= burstSize
;
466 // If not found in the write q, make a DRAM packet and
467 // push it onto the read queue
470 // Make the burst helper for split packets
471 if (pktCount
> 1 && burst_helper
== NULL
) {
472 DPRINTF(DRAM
, "Read to addr %lld translates to %d "
473 "dram requests\n", pkt
->getAddr(), pktCount
);
474 burst_helper
= new BurstHelper(pktCount
);
477 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, true);
478 dram_pkt
->burstHelper
= burst_helper
;
480 assert(!readQueueFull(1));
481 rdQLenPdf
[readQueue
.size() + respQueue
.size()]++;
483 DPRINTF(DRAM
, "Adding to read queue\n");
485 readQueue
.push_back(dram_pkt
);
487 // increment read entries of the rank
488 ++dram_pkt
->rankRef
.readEntries
;
491 avgRdQLen
= readQueue
.size() + respQueue
.size();
494 // Starting address of next dram pkt (aligend to burstSize boundary)
495 addr
= (addr
| (burstSize
- 1)) + 1;
498 // If all packets are serviced by write queue, we send the repsonse back
499 if (pktsServicedByWrQ
== pktCount
) {
500 accessAndRespond(pkt
, frontendLatency
);
504 // Update how many split packets are serviced by write queue
505 if (burst_helper
!= NULL
)
506 burst_helper
->burstsServiced
= pktsServicedByWrQ
;
508 // If we are not already scheduled to get a request out of the
510 if (!nextReqEvent
.scheduled()) {
511 DPRINTF(DRAM
, "Request scheduled immediately\n");
512 schedule(nextReqEvent
, curTick());
517 DRAMCtrl::addToWriteQueue(PacketPtr pkt
, unsigned int pktCount
)
519 // only add to the write queue here. whenever the request is
520 // eventually done, set the readyTime, and call schedule()
521 assert(pkt
->isWrite());
523 // if the request size is larger than burst size, the pkt is split into
524 // multiple DRAM packets
525 Addr addr
= pkt
->getAddr();
526 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
527 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
528 pkt
->getAddr() + pkt
->getSize()) - addr
;
529 writePktSize
[ceilLog2(size
)]++;
532 // see if we can merge with an existing item in the write
533 // queue and keep track of whether we have merged or not
534 bool merged
= isInWriteQueue
.find(burstAlign(addr
)) !=
535 isInWriteQueue
.end();
537 // if the item was not merged we need to create a new write
540 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, false);
542 assert(writeQueue
.size() < writeBufferSize
);
543 wrQLenPdf
[writeQueue
.size()]++;
545 DPRINTF(DRAM
, "Adding to write queue\n");
547 writeQueue
.push_back(dram_pkt
);
548 isInWriteQueue
.insert(burstAlign(addr
));
549 assert(writeQueue
.size() == isInWriteQueue
.size());
552 avgWrQLen
= writeQueue
.size();
554 // increment write entries of the rank
555 ++dram_pkt
->rankRef
.writeEntries
;
557 DPRINTF(DRAM
, "Merging write burst with existing queue entry\n");
559 // keep track of the fact that this burst effectively
560 // disappeared as it was merged with an existing one
564 // Starting address of next dram pkt (aligend to burstSize boundary)
565 addr
= (addr
| (burstSize
- 1)) + 1;
568 // we do not wait for the writes to be send to the actual memory,
569 // but instead take responsibility for the consistency here and
570 // snoop the write queue for any upcoming reads
571 // @todo, if a pkt size is larger than burst size, we might need a
572 // different front end latency
573 accessAndRespond(pkt
, frontendLatency
);
575 // If we are not already scheduled to get a request out of the
577 if (!nextReqEvent
.scheduled()) {
578 DPRINTF(DRAM
, "Request scheduled immediately\n");
579 schedule(nextReqEvent
, curTick());
584 DRAMCtrl::printQs() const {
585 DPRINTF(DRAM
, "===READ QUEUE===\n\n");
586 for (auto i
= readQueue
.begin() ; i
!= readQueue
.end() ; ++i
) {
587 DPRINTF(DRAM
, "Read %lu\n", (*i
)->addr
);
589 DPRINTF(DRAM
, "\n===RESP QUEUE===\n\n");
590 for (auto i
= respQueue
.begin() ; i
!= respQueue
.end() ; ++i
) {
591 DPRINTF(DRAM
, "Response %lu\n", (*i
)->addr
);
593 DPRINTF(DRAM
, "\n===WRITE QUEUE===\n\n");
594 for (auto i
= writeQueue
.begin() ; i
!= writeQueue
.end() ; ++i
) {
595 DPRINTF(DRAM
, "Write %lu\n", (*i
)->addr
);
600 DRAMCtrl::recvTimingReq(PacketPtr pkt
)
602 // This is where we enter from the outside world
603 DPRINTF(DRAM
, "recvTimingReq: request %s addr %lld size %d\n",
604 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
606 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
609 panic_if(!(pkt
->isRead() || pkt
->isWrite()),
610 "Should only see read and writes at memory controller\n");
612 // Calc avg gap between requests
613 if (prevArrival
!= 0) {
614 totGap
+= curTick() - prevArrival
;
616 prevArrival
= curTick();
619 // Find out how many dram packets a pkt translates to
620 // If the burst size is equal or larger than the pkt size, then a pkt
621 // translates to only one dram packet. Otherwise, a pkt translates to
622 // multiple dram packets
623 unsigned size
= pkt
->getSize();
624 unsigned offset
= pkt
->getAddr() & (burstSize
- 1);
625 unsigned int dram_pkt_count
= divCeil(offset
+ size
, burstSize
);
627 // check local buffers and do not accept if full
630 if (readQueueFull(dram_pkt_count
)) {
631 DPRINTF(DRAM
, "Read queue full, not accepting\n");
632 // remember that we have to retry this port
637 addToReadQueue(pkt
, dram_pkt_count
);
639 bytesReadSys
+= size
;
642 assert(pkt
->isWrite());
644 if (writeQueueFull(dram_pkt_count
)) {
645 DPRINTF(DRAM
, "Write queue full, not accepting\n");
646 // remember that we have to retry this port
651 addToWriteQueue(pkt
, dram_pkt_count
);
653 bytesWrittenSys
+= size
;
661 DRAMCtrl::processRespondEvent()
664 "processRespondEvent(): Some req has reached its readyTime\n");
666 DRAMPacket
* dram_pkt
= respQueue
.front();
668 // if a read has reached its ready-time, decrement the number of reads
669 // At this point the packet has been handled and there is a possibility
670 // to switch to low-power mode if no other packet is available
671 --dram_pkt
->rankRef
.readEntries
;
672 DPRINTF(DRAM
, "number of read entries for rank %d is %d\n",
673 dram_pkt
->rank
, dram_pkt
->rankRef
.readEntries
);
675 // counter should at least indicate one outstanding request
677 assert(dram_pkt
->rankRef
.outstandingEvents
> 0);
678 // read response received, decrement count
679 --dram_pkt
->rankRef
.outstandingEvents
;
681 // at this moment should be either ACT or IDLE depending on
682 // if PRE has occurred to close all banks
683 assert((dram_pkt
->rankRef
.pwrState
== PWR_ACT
) ||
684 (dram_pkt
->rankRef
.pwrState
== PWR_IDLE
));
686 // track if this is the last packet before idling
687 // and that there are no outstanding commands to this rank
688 if (dram_pkt
->rankRef
.lowPowerEntryReady()) {
689 // verify that there are no events scheduled
690 assert(!dram_pkt
->rankRef
.activateEvent
.scheduled());
691 assert(!dram_pkt
->rankRef
.prechargeEvent
.scheduled());
692 assert(dram_pkt
->rankRef
.refreshState
== REF_IDLE
);
694 // if coming from active state, schedule power event to
695 // active power-down else go to precharge power-down
696 DPRINTF(DRAMState
, "Rank %d sleep at tick %d; current power state is "
697 "%d\n", dram_pkt
->rank
, curTick(), dram_pkt
->rankRef
.pwrState
);
699 // default to ACT power-down unless already in IDLE state
700 // could be in IDLE if PRE issued before data returned
701 PowerState next_pwr_state
= PWR_ACT_PDN
;
702 if (dram_pkt
->rankRef
.pwrState
== PWR_IDLE
) {
703 next_pwr_state
= PWR_PRE_PDN
;
706 dram_pkt
->rankRef
.powerDownSleep(next_pwr_state
, curTick());
709 if (dram_pkt
->burstHelper
) {
710 // it is a split packet
711 dram_pkt
->burstHelper
->burstsServiced
++;
712 if (dram_pkt
->burstHelper
->burstsServiced
==
713 dram_pkt
->burstHelper
->burstCount
) {
714 // we have now serviced all children packets of a system packet
715 // so we can now respond to the requester
716 // @todo we probably want to have a different front end and back
717 // end latency for split packets
718 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
719 delete dram_pkt
->burstHelper
;
720 dram_pkt
->burstHelper
= NULL
;
723 // it is not a split packet
724 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
727 delete respQueue
.front();
728 respQueue
.pop_front();
730 if (!respQueue
.empty()) {
731 assert(respQueue
.front()->readyTime
>= curTick());
732 assert(!respondEvent
.scheduled());
733 schedule(respondEvent
, respQueue
.front()->readyTime
);
735 // if there is nothing left in any queue, signal a drain
736 if (drainState() == DrainState::Draining
&&
737 writeQueue
.empty() && readQueue
.empty() && allRanksDrained()) {
739 DPRINTF(Drain
, "DRAM controller done draining\n");
744 // We have made a location in the queue available at this point,
745 // so if there is a read that was forced to wait, retry now
753 DRAMCtrl::chooseNext(std::deque
<DRAMPacket
*>& queue
, Tick extra_col_delay
)
755 // This method does the arbitration between requests. The chosen
756 // packet is simply moved to the head of the queue. The other
757 // methods know that this is the place to look. For example, with
758 // FCFS, this method does nothing
759 assert(!queue
.empty());
761 // bool to indicate if a packet to an available rank is found
762 bool found_packet
= false;
763 if (queue
.size() == 1) {
764 DRAMPacket
* dram_pkt
= queue
.front();
765 // available rank corresponds to state refresh idle
766 if (ranks
[dram_pkt
->rank
]->isAvailable()) {
768 DPRINTF(DRAM
, "Single request, going to a free rank\n");
770 DPRINTF(DRAM
, "Single request, going to a busy rank\n");
775 if (memSchedPolicy
== Enums::fcfs
) {
776 // check if there is a packet going to a free rank
777 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
778 DRAMPacket
* dram_pkt
= *i
;
779 if (ranks
[dram_pkt
->rank
]->isAvailable()) {
781 queue
.push_front(dram_pkt
);
786 } else if (memSchedPolicy
== Enums::frfcfs
) {
787 found_packet
= reorderQueue(queue
, extra_col_delay
);
789 panic("No scheduling policy chosen\n");
794 DRAMCtrl::reorderQueue(std::deque
<DRAMPacket
*>& queue
, Tick extra_col_delay
)
796 // Only determine this if needed
797 uint64_t earliest_banks
= 0;
798 bool hidden_bank_prep
= false;
800 // search for seamless row hits first, if no seamless row hit is
801 // found then determine if there are other packets that can be issued
802 // without incurring additional bus delay due to bank timing
803 // Will select closed rows first to enable more open row possibilies
804 // in future selections
805 bool found_hidden_bank
= false;
807 // remember if we found a row hit, not seamless, but bank prepped
809 bool found_prepped_pkt
= false;
811 // if we have no row hit, prepped or not, and no seamless packet,
812 // just go for the earliest possible
813 bool found_earliest_pkt
= false;
815 auto selected_pkt_it
= queue
.end();
817 // time we need to issue a column command to be seamless
818 const Tick min_col_at
= std::max(busBusyUntil
- tCL
+ extra_col_delay
,
821 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
822 DRAMPacket
* dram_pkt
= *i
;
823 const Bank
& bank
= dram_pkt
->bankRef
;
825 // check if rank is available, if not, jump to the next packet
826 if (dram_pkt
->rankRef
.isAvailable()) {
827 // check if it is a row hit
828 if (bank
.openRow
== dram_pkt
->row
) {
829 // no additional rank-to-rank or same bank-group
830 // delays, or we switched read/write and might as well
831 // go for the row hit
832 if (bank
.colAllowedAt
<= min_col_at
) {
833 // FCFS within the hits, giving priority to
834 // commands that can issue seamlessly, without
835 // additional delay, such as same rank accesses
836 // and/or different bank-group accesses
837 DPRINTF(DRAM
, "Seamless row buffer hit\n");
839 // no need to look through the remaining queue entries
841 } else if (!found_hidden_bank
&& !found_prepped_pkt
) {
842 // if we did not find a packet to a closed row that can
843 // issue the bank commands without incurring delay, and
844 // did not yet find a packet to a prepped row, remember
847 found_prepped_pkt
= true;
848 DPRINTF(DRAM
, "Prepped row buffer hit\n");
850 } else if (!found_earliest_pkt
) {
851 // if we have not initialised the bank status, do it
852 // now, and only once per scheduling decisions
853 if (earliest_banks
== 0) {
854 // determine entries with earliest bank delay
855 pair
<uint64_t, bool> bankStatus
=
856 minBankPrep(queue
, min_col_at
);
857 earliest_banks
= bankStatus
.first
;
858 hidden_bank_prep
= bankStatus
.second
;
861 // bank is amongst first available banks
862 // minBankPrep will give priority to packets that can
864 if (bits(earliest_banks
, dram_pkt
->bankId
, dram_pkt
->bankId
)) {
865 found_earliest_pkt
= true;
866 found_hidden_bank
= hidden_bank_prep
;
868 // give priority to packets that can issue
869 // bank commands 'behind the scenes'
870 // any additional delay if any will be due to
871 // col-to-col command requirements
872 if (hidden_bank_prep
|| !found_prepped_pkt
)
879 if (selected_pkt_it
!= queue
.end()) {
880 DRAMPacket
* selected_pkt
= *selected_pkt_it
;
881 queue
.erase(selected_pkt_it
);
882 queue
.push_front(selected_pkt
);
890 DRAMCtrl::accessAndRespond(PacketPtr pkt
, Tick static_latency
)
892 DPRINTF(DRAM
, "Responding to Address %lld.. ",pkt
->getAddr());
894 bool needsResponse
= pkt
->needsResponse();
895 // do the actual memory access which also turns the packet into a
899 // turn packet around to go back to requester if response expected
901 // access already turned the packet into a response
902 assert(pkt
->isResponse());
903 // response_time consumes the static latency and is charged also
904 // with headerDelay that takes into account the delay provided by
905 // the xbar and also the payloadDelay that takes into account the
906 // number of data beats.
907 Tick response_time
= curTick() + static_latency
+ pkt
->headerDelay
+
909 // Here we reset the timing of the packet before sending it out.
910 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
912 // queue the packet in the response queue to be sent out after
913 // the static latency has passed
914 port
.schedTimingResp(pkt
, response_time
, true);
916 // @todo the packet is going to be deleted, and the DRAMPacket
917 // is still having a pointer to it
918 pendingDelete
.reset(pkt
);
921 DPRINTF(DRAM
, "Done\n");
927 DRAMCtrl::activateBank(Rank
& rank_ref
, Bank
& bank_ref
,
928 Tick act_tick
, uint32_t row
)
930 assert(rank_ref
.actTicks
.size() == activationLimit
);
932 DPRINTF(DRAM
, "Activate at tick %d\n", act_tick
);
934 // update the open row
935 assert(bank_ref
.openRow
== Bank::NO_ROW
);
936 bank_ref
.openRow
= row
;
938 // start counting anew, this covers both the case when we
939 // auto-precharged, and when this access is forced to
941 bank_ref
.bytesAccessed
= 0;
942 bank_ref
.rowAccesses
= 0;
944 ++rank_ref
.numBanksActive
;
945 assert(rank_ref
.numBanksActive
<= banksPerRank
);
947 DPRINTF(DRAM
, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
948 bank_ref
.bank
, rank_ref
.rank
, act_tick
,
949 ranks
[rank_ref
.rank
]->numBanksActive
);
951 rank_ref
.cmdList
.push_back(Command(MemCommand::ACT
, bank_ref
.bank
,
954 DPRINTF(DRAMPower
, "%llu,ACT,%d,%d\n", divCeil(act_tick
, tCK
) -
955 timeStampOffset
, bank_ref
.bank
, rank_ref
.rank
);
957 // The next access has to respect tRAS for this bank
958 bank_ref
.preAllowedAt
= act_tick
+ tRAS
;
960 // Respect the row-to-column command delay
961 bank_ref
.colAllowedAt
= std::max(act_tick
+ tRCD
, bank_ref
.colAllowedAt
);
963 // start by enforcing tRRD
964 for (int i
= 0; i
< banksPerRank
; i
++) {
965 // next activate to any bank in this rank must not happen
967 if (bankGroupArch
&& (bank_ref
.bankgr
== rank_ref
.banks
[i
].bankgr
)) {
968 // bank group architecture requires longer delays between
969 // ACT commands within the same bank group. Use tRRD_L
971 rank_ref
.banks
[i
].actAllowedAt
= std::max(act_tick
+ tRRD_L
,
972 rank_ref
.banks
[i
].actAllowedAt
);
974 // use shorter tRRD value when either
975 // 1) bank group architecture is not supportted
976 // 2) bank is in a different bank group
977 rank_ref
.banks
[i
].actAllowedAt
= std::max(act_tick
+ tRRD
,
978 rank_ref
.banks
[i
].actAllowedAt
);
982 // next, we deal with tXAW, if the activation limit is disabled
983 // then we directly schedule an activate power event
984 if (!rank_ref
.actTicks
.empty()) {
986 if (rank_ref
.actTicks
.back() &&
987 (act_tick
- rank_ref
.actTicks
.back()) < tXAW
) {
988 panic("Got %d activates in window %d (%llu - %llu) which "
989 "is smaller than %llu\n", activationLimit
, act_tick
-
990 rank_ref
.actTicks
.back(), act_tick
,
991 rank_ref
.actTicks
.back(), tXAW
);
994 // shift the times used for the book keeping, the last element
995 // (highest index) is the oldest one and hence the lowest value
996 rank_ref
.actTicks
.pop_back();
998 // record an new activation (in the future)
999 rank_ref
.actTicks
.push_front(act_tick
);
1001 // cannot activate more than X times in time window tXAW, push the
1002 // next one (the X + 1'st activate) to be tXAW away from the
1003 // oldest in our window of X
1004 if (rank_ref
.actTicks
.back() &&
1005 (act_tick
- rank_ref
.actTicks
.back()) < tXAW
) {
1006 DPRINTF(DRAM
, "Enforcing tXAW with X = %d, next activate "
1007 "no earlier than %llu\n", activationLimit
,
1008 rank_ref
.actTicks
.back() + tXAW
);
1009 for (int j
= 0; j
< banksPerRank
; j
++)
1010 // next activate must not happen before end of window
1011 rank_ref
.banks
[j
].actAllowedAt
=
1012 std::max(rank_ref
.actTicks
.back() + tXAW
,
1013 rank_ref
.banks
[j
].actAllowedAt
);
1017 // at the point when this activate takes place, make sure we
1018 // transition to the active power state
1019 if (!rank_ref
.activateEvent
.scheduled())
1020 schedule(rank_ref
.activateEvent
, act_tick
);
1021 else if (rank_ref
.activateEvent
.when() > act_tick
)
1022 // move it sooner in time
1023 reschedule(rank_ref
.activateEvent
, act_tick
);
1027 DRAMCtrl::prechargeBank(Rank
& rank_ref
, Bank
& bank
, Tick pre_at
, bool trace
)
1029 // make sure the bank has an open row
1030 assert(bank
.openRow
!= Bank::NO_ROW
);
1032 // sample the bytes per activate here since we are closing
1034 bytesPerActivate
.sample(bank
.bytesAccessed
);
1036 bank
.openRow
= Bank::NO_ROW
;
1038 // no precharge allowed before this one
1039 bank
.preAllowedAt
= pre_at
;
1041 Tick pre_done_at
= pre_at
+ tRP
;
1043 bank
.actAllowedAt
= std::max(bank
.actAllowedAt
, pre_done_at
);
1045 assert(rank_ref
.numBanksActive
!= 0);
1046 --rank_ref
.numBanksActive
;
1048 DPRINTF(DRAM
, "Precharging bank %d, rank %d at tick %lld, now got "
1049 "%d active\n", bank
.bank
, rank_ref
.rank
, pre_at
,
1050 rank_ref
.numBanksActive
);
1054 rank_ref
.cmdList
.push_back(Command(MemCommand::PRE
, bank
.bank
,
1056 DPRINTF(DRAMPower
, "%llu,PRE,%d,%d\n", divCeil(pre_at
, tCK
) -
1057 timeStampOffset
, bank
.bank
, rank_ref
.rank
);
1059 // if we look at the current number of active banks we might be
1060 // tempted to think the DRAM is now idle, however this can be
1061 // undone by an activate that is scheduled to happen before we
1062 // would have reached the idle state, so schedule an event and
1063 // rather check once we actually make it to the point in time when
1064 // the (last) precharge takes place
1065 if (!rank_ref
.prechargeEvent
.scheduled()) {
1066 schedule(rank_ref
.prechargeEvent
, pre_done_at
);
1067 // New event, increment count
1068 ++rank_ref
.outstandingEvents
;
1069 } else if (rank_ref
.prechargeEvent
.when() < pre_done_at
) {
1070 reschedule(rank_ref
.prechargeEvent
, pre_done_at
);
1075 DRAMCtrl::doDRAMAccess(DRAMPacket
* dram_pkt
)
1077 DPRINTF(DRAM
, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1078 dram_pkt
->addr
, dram_pkt
->rank
, dram_pkt
->bank
, dram_pkt
->row
);
1081 Rank
& rank
= dram_pkt
->rankRef
;
1083 // are we in or transitioning to a low-power state and have not scheduled
1084 // a power-up event?
1085 // if so, wake up from power down to issue RD/WR burst
1086 if (rank
.inLowPowerState
) {
1087 assert(rank
.pwrState
!= PWR_SREF
);
1088 rank
.scheduleWakeUpEvent(tXP
);
1092 Bank
& bank
= dram_pkt
->bankRef
;
1094 // for the state we need to track if it is a row hit or not
1095 bool row_hit
= true;
1097 // respect any constraints on the command (e.g. tRCD or tCCD)
1098 Tick cmd_at
= std::max(bank
.colAllowedAt
, curTick());
1100 // Determine the access latency and update the bank state
1101 if (bank
.openRow
== dram_pkt
->row
) {
1106 // If there is a page open, precharge it.
1107 if (bank
.openRow
!= Bank::NO_ROW
) {
1108 prechargeBank(rank
, bank
, std::max(bank
.preAllowedAt
, curTick()));
1111 // next we need to account for the delay in activating the
1113 Tick act_tick
= std::max(bank
.actAllowedAt
, curTick());
1115 // Record the activation and deal with all the global timing
1116 // constraints caused be a new activation (tRRD and tXAW)
1117 activateBank(rank
, bank
, act_tick
, dram_pkt
->row
);
1119 // issue the command as early as possible
1120 cmd_at
= bank
.colAllowedAt
;
1123 // we need to wait until the bus is available before we can issue
1125 cmd_at
= std::max(cmd_at
, busBusyUntil
- tCL
);
1127 // update the packet ready time
1128 dram_pkt
->readyTime
= cmd_at
+ tCL
+ tBURST
;
1130 // only one burst can use the bus at any one point in time
1131 assert(dram_pkt
->readyTime
- busBusyUntil
>= tBURST
);
1133 // update the time for the next read/write burst for each
1134 // bank (add a max with tCCD/tCCD_L here)
1136 for (int j
= 0; j
< ranksPerChannel
; j
++) {
1137 for (int i
= 0; i
< banksPerRank
; i
++) {
1138 // next burst to same bank group in this rank must not happen
1139 // before tCCD_L. Different bank group timing requirement is
1140 // tBURST; Add tCS for different ranks
1141 if (dram_pkt
->rank
== j
) {
1142 if (bankGroupArch
&&
1143 (bank
.bankgr
== ranks
[j
]->banks
[i
].bankgr
)) {
1144 // bank group architecture requires longer delays between
1145 // RD/WR burst commands to the same bank group.
1146 // Use tCCD_L in this case
1149 // use tBURST (equivalent to tCCD_S), the shorter
1150 // cas-to-cas delay value, when either:
1151 // 1) bank group architecture is not supportted
1152 // 2) bank is in a different bank group
1156 // different rank is by default in a different bank group
1157 // use tBURST (equivalent to tCCD_S), which is the shorter
1158 // cas-to-cas delay in this case
1159 // Add tCS to account for rank-to-rank bus delay requirements
1160 cmd_dly
= tBURST
+ tCS
;
1162 ranks
[j
]->banks
[i
].colAllowedAt
= std::max(cmd_at
+ cmd_dly
,
1163 ranks
[j
]->banks
[i
].colAllowedAt
);
1167 // Save rank of current access
1168 activeRank
= dram_pkt
->rank
;
1170 // If this is a write, we also need to respect the write recovery
1171 // time before a precharge, in the case of a read, respect the
1172 // read to precharge constraint
1173 bank
.preAllowedAt
= std::max(bank
.preAllowedAt
,
1174 dram_pkt
->isRead
? cmd_at
+ tRTP
:
1175 dram_pkt
->readyTime
+ tWR
);
1177 // increment the bytes accessed and the accesses per row
1178 bank
.bytesAccessed
+= burstSize
;
1181 // if we reached the max, then issue with an auto-precharge
1182 bool auto_precharge
= pageMgmt
== Enums::close
||
1183 bank
.rowAccesses
== maxAccessesPerRow
;
1185 // if we did not hit the limit, we might still want to
1187 if (!auto_precharge
&&
1188 (pageMgmt
== Enums::open_adaptive
||
1189 pageMgmt
== Enums::close_adaptive
)) {
1190 // a twist on the open and close page policies:
1191 // 1) open_adaptive page policy does not blindly keep the
1192 // page open, but close it if there are no row hits, and there
1193 // are bank conflicts in the queue
1194 // 2) close_adaptive page policy does not blindly close the
1195 // page, but closes it only if there are no row hits in the queue.
1196 // In this case, only force an auto precharge when there
1197 // are no same page hits in the queue
1198 bool got_more_hits
= false;
1199 bool got_bank_conflict
= false;
1201 // either look at the read queue or write queue
1202 const deque
<DRAMPacket
*>& queue
= dram_pkt
->isRead
? readQueue
:
1204 auto p
= queue
.begin();
1205 // make sure we are not considering the packet that we are
1206 // currently dealing with (which is the head of the queue)
1209 // keep on looking until we find a hit or reach the end of the queue
1210 // 1) if a hit is found, then both open and close adaptive policies keep
1212 // 2) if no hit is found, got_bank_conflict is set to true if a bank
1213 // conflict request is waiting in the queue
1214 while (!got_more_hits
&& p
!= queue
.end()) {
1215 bool same_rank_bank
= (dram_pkt
->rank
== (*p
)->rank
) &&
1216 (dram_pkt
->bank
== (*p
)->bank
);
1217 bool same_row
= dram_pkt
->row
== (*p
)->row
;
1218 got_more_hits
|= same_rank_bank
&& same_row
;
1219 got_bank_conflict
|= same_rank_bank
&& !same_row
;
1223 // auto pre-charge when either
1224 // 1) open_adaptive policy, we have not got any more hits, and
1225 // have a bank conflict
1226 // 2) close_adaptive policy and we have not got any more hits
1227 auto_precharge
= !got_more_hits
&&
1228 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
);
1231 // DRAMPower trace command to be written
1232 std::string mem_cmd
= dram_pkt
->isRead
? "RD" : "WR";
1234 // MemCommand required for DRAMPower library
1235 MemCommand::cmds command
= (mem_cmd
== "RD") ? MemCommand::RD
:
1239 busBusyUntil
= dram_pkt
->readyTime
;
1241 DPRINTF(DRAM
, "Access to %lld, ready at %lld bus busy until %lld.\n",
1242 dram_pkt
->addr
, dram_pkt
->readyTime
, busBusyUntil
);
1244 dram_pkt
->rankRef
.cmdList
.push_back(Command(command
, dram_pkt
->bank
,
1247 DPRINTF(DRAMPower
, "%llu,%s,%d,%d\n", divCeil(cmd_at
, tCK
) -
1248 timeStampOffset
, mem_cmd
, dram_pkt
->bank
, dram_pkt
->rank
);
1250 // if this access should use auto-precharge, then we are
1251 // closing the row after the read/write burst
1252 if (auto_precharge
) {
1253 // if auto-precharge push a PRE command at the correct tick to the
1254 // list used by DRAMPower library to calculate power
1255 prechargeBank(rank
, bank
, std::max(curTick(), bank
.preAllowedAt
));
1257 DPRINTF(DRAM
, "Auto-precharged bank: %d\n", dram_pkt
->bankId
);
1260 // Update the minimum timing between the requests, this is a
1261 // conservative estimate of when we have to schedule the next
1262 // request to not introduce any unecessary bubbles. In most cases
1263 // we will wake up sooner than we have to.
1264 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1266 // Update the stats and schedule the next request
1267 if (dram_pkt
->isRead
) {
1271 bytesReadDRAM
+= burstSize
;
1272 perBankRdBursts
[dram_pkt
->bankId
]++;
1274 // Update latency stats
1275 totMemAccLat
+= dram_pkt
->readyTime
- dram_pkt
->entryTime
;
1276 totBusLat
+= tBURST
;
1277 totQLat
+= cmd_at
- dram_pkt
->entryTime
;
1282 bytesWritten
+= burstSize
;
1283 perBankWrBursts
[dram_pkt
->bankId
]++;
1288 DRAMCtrl::processNextReqEvent()
1291 for (auto r
: ranks
) {
1292 if (!r
->isAvailable()) {
1293 if (r
->pwrState
!= PWR_SREF
) {
1294 // rank is busy refreshing
1295 DPRINTF(DRAMState
, "Rank %d is not available\n", r
->rank
);
1298 // let the rank know that if it was waiting to drain, it
1299 // is now done and ready to proceed
1300 r
->checkDrainDone();
1303 // check if we were in self-refresh and haven't started
1304 // to transition out
1305 if ((r
->pwrState
== PWR_SREF
) && r
->inLowPowerState
) {
1306 DPRINTF(DRAMState
, "Rank %d is in self-refresh\n", r
->rank
);
1307 // if we have commands queued to this rank and we don't have
1308 // a minimum number of active commands enqueued,
1309 // exit self-refresh
1310 if (r
->forceSelfRefreshExit()) {
1311 DPRINTF(DRAMState
, "rank %d was in self refresh and"
1312 " should wake up\n", r
->rank
);
1313 //wake up from self-refresh
1314 r
->scheduleWakeUpEvent(tXS
);
1315 // things are brought back into action once a refresh is
1316 // performed after self-refresh
1317 // continue with selection for other ranks
1323 if (busyRanks
== ranksPerChannel
) {
1324 // if all ranks are refreshing wait for them to finish
1325 // and stall this state machine without taking any further
1326 // action, and do not schedule a new nextReqEvent
1330 // pre-emptively set to false. Overwrite if in transitioning to
1332 bool switched_cmd_type
= false;
1333 if (busState
!= busStateNext
) {
1334 if (busState
== READ
) {
1335 DPRINTF(DRAM
, "Switching to writes after %d reads with %d reads "
1336 "waiting\n", readsThisTime
, readQueue
.size());
1338 // sample and reset the read-related stats as we are now
1339 // transitioning to writes, and all reads are done
1340 rdPerTurnAround
.sample(readsThisTime
);
1343 // now proceed to do the actual writes
1344 switched_cmd_type
= true;
1346 DPRINTF(DRAM
, "Switching to reads after %d writes with %d writes "
1347 "waiting\n", writesThisTime
, writeQueue
.size());
1349 wrPerTurnAround
.sample(writesThisTime
);
1352 switched_cmd_type
= true;
1354 // update busState to match next state until next transition
1355 busState
= busStateNext
;
1358 // when we get here it is either a read or a write
1359 if (busState
== READ
) {
1361 // track if we should switch or not
1362 bool switch_to_writes
= false;
1364 if (readQueue
.empty()) {
1365 // In the case there is no read request to go next,
1366 // trigger writes if we have passed the low threshold (or
1367 // if we are draining)
1368 if (!writeQueue
.empty() &&
1369 (drainState() == DrainState::Draining
||
1370 writeQueue
.size() > writeLowThreshold
)) {
1372 switch_to_writes
= true;
1374 // check if we are drained
1375 // not done draining until in PWR_IDLE state
1376 // ensuring all banks are closed and
1377 // have exited low power states
1378 if (drainState() == DrainState::Draining
&&
1379 respQueue
.empty() && allRanksDrained()) {
1381 DPRINTF(Drain
, "DRAM controller done draining\n");
1385 // nothing to do, not even any point in scheduling an
1386 // event for the next request
1390 // bool to check if there is a read to a free rank
1391 bool found_read
= false;
1393 // Figure out which read request goes next, and move it to the
1394 // front of the read queue
1395 // If we are changing command type, incorporate the minimum
1396 // bus turnaround delay which will be tCS (different rank) case
1397 found_read
= chooseNext(readQueue
,
1398 switched_cmd_type
? tCS
: 0);
1400 // if no read to an available rank is found then return
1401 // at this point. There could be writes to the available ranks
1402 // which are above the required threshold. However, to
1403 // avoid adding more complexity to the code, return and wait
1404 // for a refresh event to kick things into action again.
1408 DRAMPacket
* dram_pkt
= readQueue
.front();
1409 assert(dram_pkt
->rankRef
.isAvailable());
1411 // here we get a bit creative and shift the bus busy time not
1412 // just the tWTR, but also a CAS latency to capture the fact
1413 // that we are allowed to prepare a new bank, but not issue a
1414 // read command until after tWTR, in essence we capture a
1415 // bubble on the data bus that is tWTR + tCL
1416 if (switched_cmd_type
&& dram_pkt
->rank
== activeRank
) {
1417 busBusyUntil
+= tWTR
+ tCL
;
1420 doDRAMAccess(dram_pkt
);
1422 // At this point we're done dealing with the request
1423 readQueue
.pop_front();
1425 // Every respQueue which will generate an event, increment count
1426 ++dram_pkt
->rankRef
.outstandingEvents
;
1429 assert(dram_pkt
->size
<= burstSize
);
1430 assert(dram_pkt
->readyTime
>= curTick());
1432 // Insert into response queue. It will be sent back to the
1433 // requestor at its readyTime
1434 if (respQueue
.empty()) {
1435 assert(!respondEvent
.scheduled());
1436 schedule(respondEvent
, dram_pkt
->readyTime
);
1438 assert(respQueue
.back()->readyTime
<= dram_pkt
->readyTime
);
1439 assert(respondEvent
.scheduled());
1442 respQueue
.push_back(dram_pkt
);
1444 // we have so many writes that we have to transition
1445 if (writeQueue
.size() > writeHighThreshold
) {
1446 switch_to_writes
= true;
1450 // switching to writes, either because the read queue is empty
1451 // and the writes have passed the low threshold (or we are
1452 // draining), or because the writes hit the hight threshold
1453 if (switch_to_writes
) {
1454 // transition to writing
1455 busStateNext
= WRITE
;
1458 // bool to check if write to free rank is found
1459 bool found_write
= false;
1461 // If we are changing command type, incorporate the minimum
1462 // bus turnaround delay
1463 found_write
= chooseNext(writeQueue
,
1464 switched_cmd_type
? std::min(tRTW
, tCS
) : 0);
1466 // if no writes to an available rank are found then return.
1467 // There could be reads to the available ranks. However, to avoid
1468 // adding more complexity to the code, return at this point and wait
1469 // for a refresh event to kick things into action again.
1473 DRAMPacket
* dram_pkt
= writeQueue
.front();
1474 assert(dram_pkt
->rankRef
.isAvailable());
1476 assert(dram_pkt
->size
<= burstSize
);
1478 // add a bubble to the data bus, as defined by the
1479 // tRTW when access is to the same rank as previous burst
1480 // Different rank timing is handled with tCS, which is
1481 // applied to colAllowedAt
1482 if (switched_cmd_type
&& dram_pkt
->rank
== activeRank
) {
1483 busBusyUntil
+= tRTW
;
1486 doDRAMAccess(dram_pkt
);
1488 writeQueue
.pop_front();
1490 // removed write from queue, decrement count
1491 --dram_pkt
->rankRef
.writeEntries
;
1493 // Schedule write done event to decrement event count
1494 // after the readyTime has been reached
1495 // Only schedule latest write event to minimize events
1496 // required; only need to ensure that final event scheduled covers
1497 // the time that writes are outstanding and bus is active
1498 // to holdoff power-down entry events
1499 if (!dram_pkt
->rankRef
.writeDoneEvent
.scheduled()) {
1500 schedule(dram_pkt
->rankRef
.writeDoneEvent
, dram_pkt
->readyTime
);
1501 // New event, increment count
1502 ++dram_pkt
->rankRef
.outstandingEvents
;
1504 } else if (dram_pkt
->rankRef
.writeDoneEvent
.when() <
1505 dram_pkt
-> readyTime
) {
1506 reschedule(dram_pkt
->rankRef
.writeDoneEvent
, dram_pkt
->readyTime
);
1509 isInWriteQueue
.erase(burstAlign(dram_pkt
->addr
));
1512 // If we emptied the write queue, or got sufficiently below the
1513 // threshold (using the minWritesPerSwitch as the hysteresis) and
1514 // are not draining, or we have reads waiting and have done enough
1515 // writes, then switch to reads.
1516 if (writeQueue
.empty() ||
1517 (writeQueue
.size() + minWritesPerSwitch
< writeLowThreshold
&&
1518 drainState() != DrainState::Draining
) ||
1519 (!readQueue
.empty() && writesThisTime
>= minWritesPerSwitch
)) {
1520 // turn the bus back around for reads again
1521 busStateNext
= READ
;
1523 // note that the we switch back to reads also in the idle
1524 // case, which eventually will check for any draining and
1525 // also pause any further scheduling if there is really
1529 // It is possible that a refresh to another rank kicks things back into
1530 // action before reaching this point.
1531 if (!nextReqEvent
.scheduled())
1532 schedule(nextReqEvent
, std::max(nextReqTime
, curTick()));
1534 // If there is space available and we have writes waiting then let
1535 // them retry. This is done here to ensure that the retry does not
1536 // cause a nextReqEvent to be scheduled before we do so as part of
1537 // the next request processing
1538 if (retryWrReq
&& writeQueue
.size() < writeBufferSize
) {
1540 port
.sendRetryReq();
1544 pair
<uint64_t, bool>
1545 DRAMCtrl::minBankPrep(const deque
<DRAMPacket
*>& queue
,
1546 Tick min_col_at
) const
1548 uint64_t bank_mask
= 0;
1549 Tick min_act_at
= MaxTick
;
1551 // latest Tick for which ACT can occur without incurring additoinal
1552 // delay on the data bus
1553 const Tick hidden_act_max
= std::max(min_col_at
- tRCD
, curTick());
1555 // Flag condition when burst can issue back-to-back with previous burst
1556 bool found_seamless_bank
= false;
1558 // Flag condition when bank can be opened without incurring additional
1559 // delay on the data bus
1560 bool hidden_bank_prep
= false;
1562 // determine if we have queued transactions targetting the
1564 vector
<bool> got_waiting(ranksPerChannel
* banksPerRank
, false);
1565 for (const auto& p
: queue
) {
1566 if (p
->rankRef
.isAvailable())
1567 got_waiting
[p
->bankId
] = true;
1570 // Find command with optimal bank timing
1571 // Will prioritize commands that can issue seamlessly.
1572 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1573 for (int j
= 0; j
< banksPerRank
; j
++) {
1574 uint16_t bank_id
= i
* banksPerRank
+ j
;
1576 // if we have waiting requests for the bank, and it is
1577 // amongst the first available, update the mask
1578 if (got_waiting
[bank_id
]) {
1579 // make sure this rank is not currently refreshing.
1580 assert(ranks
[i
]->isAvailable());
1581 // simplistic approximation of when the bank can issue
1582 // an activate, ignoring any rank-to-rank switching
1583 // cost in this calculation
1584 Tick act_at
= ranks
[i
]->banks
[j
].openRow
== Bank::NO_ROW
?
1585 std::max(ranks
[i
]->banks
[j
].actAllowedAt
, curTick()) :
1586 std::max(ranks
[i
]->banks
[j
].preAllowedAt
, curTick()) + tRP
;
1588 // When is the earliest the R/W burst can issue?
1589 Tick col_at
= std::max(ranks
[i
]->banks
[j
].colAllowedAt
,
1592 // bank can issue burst back-to-back (seamlessly) with
1594 bool new_seamless_bank
= col_at
<= min_col_at
;
1596 // if we found a new seamless bank or we have no
1597 // seamless banks, and got a bank with an earlier
1598 // activate time, it should be added to the bit mask
1599 if (new_seamless_bank
||
1600 (!found_seamless_bank
&& act_at
<= min_act_at
)) {
1601 // if we did not have a seamless bank before, and
1602 // we do now, reset the bank mask, also reset it
1603 // if we have not yet found a seamless bank and
1604 // the activate time is smaller than what we have
1606 if (!found_seamless_bank
&&
1607 (new_seamless_bank
|| act_at
< min_act_at
)) {
1611 found_seamless_bank
|= new_seamless_bank
;
1613 // ACT can occur 'behind the scenes'
1614 hidden_bank_prep
= act_at
<= hidden_act_max
;
1616 // set the bit corresponding to the available bank
1617 replaceBits(bank_mask
, bank_id
, bank_id
, 1);
1618 min_act_at
= act_at
;
1624 return make_pair(bank_mask
, hidden_bank_prep
);
1627 DRAMCtrl::Rank::Rank(DRAMCtrl
& _memory
, const DRAMCtrlParams
* _p
)
1628 : EventManager(&_memory
), memory(_memory
),
1629 pwrStateTrans(PWR_IDLE
), pwrStatePostRefresh(PWR_IDLE
),
1630 pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE
),
1631 refreshState(REF_IDLE
), inLowPowerState(false), rank(0),
1632 readEntries(0), writeEntries(0), outstandingEvents(0),
1633 wakeUpAllowedAt(0), power(_p
, false), numBanksActive(0),
1634 writeDoneEvent(*this), activateEvent(*this), prechargeEvent(*this),
1635 refreshEvent(*this), powerEvent(*this), wakeUpEvent(*this)
1639 DRAMCtrl::Rank::startup(Tick ref_tick
)
1641 assert(ref_tick
> curTick());
1643 pwrStateTick
= curTick();
1645 // kick off the refresh, and give ourselves enough time to
1647 schedule(refreshEvent
, ref_tick
);
1651 DRAMCtrl::Rank::suspend()
1653 deschedule(refreshEvent
);
1658 // don't automatically transition back to LP state after next REF
1659 pwrStatePostRefresh
= PWR_IDLE
;
1663 DRAMCtrl::Rank::lowPowerEntryReady() const
1665 bool no_queued_cmds
= ((memory
.busStateNext
== READ
) && (readEntries
== 0))
1666 || ((memory
.busStateNext
== WRITE
) &&
1667 (writeEntries
== 0));
1669 if (refreshState
== REF_RUN
) {
1670 // have not decremented outstandingEvents for refresh command
1671 // still check if there are no commands queued to force PD
1672 // entry after refresh completes
1673 return no_queued_cmds
;
1675 // ensure no commands in Q and no commands scheduled
1676 return (no_queued_cmds
&& (outstandingEvents
== 0));
1681 DRAMCtrl::Rank::checkDrainDone()
1683 // if this rank was waiting to drain it is now able to proceed to
1685 if (refreshState
== REF_DRAIN
) {
1686 DPRINTF(DRAM
, "Refresh drain done, now precharging\n");
1688 refreshState
= REF_PD_EXIT
;
1690 // hand control back to the refresh event loop
1691 schedule(refreshEvent
, curTick());
1696 DRAMCtrl::Rank::flushCmdList()
1698 // at the moment sort the list of commands and update the counters
1699 // for DRAMPower libray when doing a refresh
1700 sort(cmdList
.begin(), cmdList
.end(), DRAMCtrl::sortTime
);
1702 auto next_iter
= cmdList
.begin();
1703 // push to commands to DRAMPower
1704 for ( ; next_iter
!= cmdList
.end() ; ++next_iter
) {
1705 Command cmd
= *next_iter
;
1706 if (cmd
.timeStamp
<= curTick()) {
1707 // Move all commands at or before curTick to DRAMPower
1708 power
.powerlib
.doCommand(cmd
.type
, cmd
.bank
,
1709 divCeil(cmd
.timeStamp
, memory
.tCK
) -
1710 memory
.timeStampOffset
);
1712 // done - found all commands at or before curTick()
1713 // next_iter references the 1st command after curTick
1717 // reset cmdList to only contain commands after curTick
1718 // if there are no commands after curTick, updated cmdList will be empty
1719 // in this case, next_iter is cmdList.end()
1720 cmdList
.assign(next_iter
, cmdList
.end());
1724 DRAMCtrl::Rank::processActivateEvent()
1726 // we should transition to the active state as soon as any bank is active
1727 if (pwrState
!= PWR_ACT
)
1728 // note that at this point numBanksActive could be back at
1729 // zero again due to a precharge scheduled in the future
1730 schedulePowerEvent(PWR_ACT
, curTick());
1734 DRAMCtrl::Rank::processPrechargeEvent()
1736 // counter should at least indicate one outstanding request
1737 // for this precharge
1738 assert(outstandingEvents
> 0);
1739 // precharge complete, decrement count
1740 --outstandingEvents
;
1742 // if we reached zero, then special conditions apply as we track
1743 // if all banks are precharged for the power models
1744 if (numBanksActive
== 0) {
1745 // no reads to this rank in the Q and no pending
1746 // RD/WR or refresh commands
1747 if (lowPowerEntryReady()) {
1748 // should still be in ACT state since bank still open
1749 assert(pwrState
== PWR_ACT
);
1751 // All banks closed - switch to precharge power down state.
1752 DPRINTF(DRAMState
, "Rank %d sleep at tick %d\n",
1754 powerDownSleep(PWR_PRE_PDN
, curTick());
1756 // we should transition to the idle state when the last bank
1758 schedulePowerEvent(PWR_IDLE
, curTick());
1764 DRAMCtrl::Rank::processWriteDoneEvent()
1766 // counter should at least indicate one outstanding request
1768 assert(outstandingEvents
> 0);
1769 // Write transfer on bus has completed
1770 // decrement per rank counter
1771 --outstandingEvents
;
1775 DRAMCtrl::Rank::processRefreshEvent()
1777 // when first preparing the refresh, remember when it was due
1778 if ((refreshState
== REF_IDLE
) || (refreshState
== REF_SREF_EXIT
)) {
1779 // remember when the refresh is due
1780 refreshDueAt
= curTick();
1783 refreshState
= REF_DRAIN
;
1785 // make nonzero while refresh is pending to ensure
1786 // power down and self-refresh are not entered
1787 ++outstandingEvents
;
1789 DPRINTF(DRAM
, "Refresh due\n");
1792 // let any scheduled read or write to the same rank go ahead,
1793 // after which it will
1794 // hand control back to this event loop
1795 if (refreshState
== REF_DRAIN
) {
1796 // if a request is at the moment being handled and this request is
1797 // accessing the current rank then wait for it to finish
1798 if ((rank
== memory
.activeRank
)
1799 && (memory
.nextReqEvent
.scheduled())) {
1800 // hand control over to the request loop until it is
1802 DPRINTF(DRAM
, "Refresh awaiting draining\n");
1806 refreshState
= REF_PD_EXIT
;
1810 // at this point, ensure that rank is not in a power-down state
1811 if (refreshState
== REF_PD_EXIT
) {
1812 // if rank was sleeping and we have't started exit process,
1813 // wake-up for refresh
1814 if (inLowPowerState
) {
1815 DPRINTF(DRAM
, "Wake Up for refresh\n");
1816 // save state and return after refresh completes
1817 scheduleWakeUpEvent(memory
.tXP
);
1820 refreshState
= REF_PRE
;
1824 // at this point, ensure that all banks are precharged
1825 if (refreshState
== REF_PRE
) {
1826 // precharge any active bank
1827 if (numBanksActive
!= 0) {
1828 // at the moment, we use a precharge all even if there is
1829 // only a single bank open
1830 DPRINTF(DRAM
, "Precharging all\n");
1832 // first determine when we can precharge
1833 Tick pre_at
= curTick();
1835 for (auto &b
: banks
) {
1836 // respect both causality and any existing bank
1837 // constraints, some banks could already have a
1838 // (auto) precharge scheduled
1839 pre_at
= std::max(b
.preAllowedAt
, pre_at
);
1842 // make sure all banks per rank are precharged, and for those that
1843 // already are, update their availability
1844 Tick act_allowed_at
= pre_at
+ memory
.tRP
;
1846 for (auto &b
: banks
) {
1847 if (b
.openRow
!= Bank::NO_ROW
) {
1848 memory
.prechargeBank(*this, b
, pre_at
, false);
1850 b
.actAllowedAt
= std::max(b
.actAllowedAt
, act_allowed_at
);
1851 b
.preAllowedAt
= std::max(b
.preAllowedAt
, pre_at
);
1855 // precharge all banks in rank
1856 cmdList
.push_back(Command(MemCommand::PREA
, 0, pre_at
));
1858 DPRINTF(DRAMPower
, "%llu,PREA,0,%d\n",
1859 divCeil(pre_at
, memory
.tCK
) -
1860 memory
.timeStampOffset
, rank
);
1861 } else if ((pwrState
== PWR_IDLE
) && (outstandingEvents
== 1)) {
1862 // Banks are closed, have transitioned to IDLE state, and
1863 // no outstanding ACT,RD/WR,Auto-PRE sequence scheduled
1864 DPRINTF(DRAM
, "All banks already precharged, starting refresh\n");
1866 // go ahead and kick the power state machine into gear since
1867 // we are already idle
1868 schedulePowerEvent(PWR_REF
, curTick());
1870 // banks state is closed but haven't transitioned pwrState to IDLE
1871 // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled
1872 // should have outstanding precharge event in this case
1873 assert(prechargeEvent
.scheduled());
1874 // will start refresh when pwrState transitions to IDLE
1877 assert(numBanksActive
== 0);
1879 // wait for all banks to be precharged, at which point the
1880 // power state machine will transition to the idle state, and
1881 // automatically move to a refresh, at that point it will also
1882 // call this method to get the refresh event loop going again
1886 // last but not least we perform the actual refresh
1887 if (refreshState
== REF_START
) {
1888 // should never get here with any banks active
1889 assert(numBanksActive
== 0);
1890 assert(pwrState
== PWR_REF
);
1892 Tick ref_done_at
= curTick() + memory
.tRFC
;
1894 for (auto &b
: banks
) {
1895 b
.actAllowedAt
= ref_done_at
;
1898 // at the moment this affects all ranks
1899 cmdList
.push_back(Command(MemCommand::REF
, 0, curTick()));
1904 DPRINTF(DRAMPower
, "%llu,REF,0,%d\n", divCeil(curTick(), memory
.tCK
) -
1905 memory
.timeStampOffset
, rank
);
1907 // Update for next refresh
1908 refreshDueAt
+= memory
.tREFI
;
1910 // make sure we did not wait so long that we cannot make up
1912 if (refreshDueAt
< ref_done_at
) {
1913 fatal("Refresh was delayed so long we cannot catch up\n");
1916 // Run the refresh and schedule event to transition power states
1917 // when refresh completes
1918 refreshState
= REF_RUN
;
1919 schedule(refreshEvent
, ref_done_at
);
1923 if (refreshState
== REF_RUN
) {
1924 // should never get here with any banks active
1925 assert(numBanksActive
== 0);
1926 assert(pwrState
== PWR_REF
);
1928 assert(!powerEvent
.scheduled());
1930 if ((memory
.drainState() == DrainState::Draining
) ||
1931 (memory
.drainState() == DrainState::Drained
)) {
1932 // if draining, do not re-enter low-power mode.
1933 // simply go to IDLE and wait
1934 schedulePowerEvent(PWR_IDLE
, curTick());
1936 // At the moment, we sleep when the refresh ends and wait to be
1937 // woken up again if previously in a low-power state.
1938 if (pwrStatePostRefresh
!= PWR_IDLE
) {
1939 // power State should be power Refresh
1940 assert(pwrState
== PWR_REF
);
1941 DPRINTF(DRAMState
, "Rank %d sleeping after refresh and was in "
1942 "power state %d before refreshing\n", rank
,
1943 pwrStatePostRefresh
);
1944 powerDownSleep(pwrState
, curTick());
1946 // Force PRE power-down if there are no outstanding commands
1947 // in Q after refresh.
1948 } else if (lowPowerEntryReady()) {
1949 DPRINTF(DRAMState
, "Rank %d sleeping after refresh but was NOT"
1950 " in a low power state before refreshing\n", rank
);
1951 powerDownSleep(PWR_PRE_PDN
, curTick());
1954 // move to the idle power state once the refresh is done, this
1955 // will also move the refresh state machine to the refresh
1957 schedulePowerEvent(PWR_IDLE
, curTick());
1961 // if transitioning to self refresh do not schedule a new refresh;
1962 // when waking from self refresh, a refresh is scheduled again.
1963 if (pwrStateTrans
!= PWR_SREF
) {
1964 // compensate for the delay in actually performing the refresh
1965 // when scheduling the next one
1966 schedule(refreshEvent
, refreshDueAt
- memory
.tRP
);
1968 DPRINTF(DRAMState
, "Refresh done at %llu and next refresh"
1969 " at %llu\n", curTick(), refreshDueAt
);
1975 DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state
, Tick tick
)
1977 // respect causality
1978 assert(tick
>= curTick());
1980 if (!powerEvent
.scheduled()) {
1981 DPRINTF(DRAMState
, "Scheduling power event at %llu to state %d\n",
1984 // insert the new transition
1985 pwrStateTrans
= pwr_state
;
1987 schedule(powerEvent
, tick
);
1989 panic("Scheduled power event at %llu to state %d, "
1990 "with scheduled event at %llu to %d\n", tick
, pwr_state
,
1991 powerEvent
.when(), pwrStateTrans
);
1996 DRAMCtrl::Rank::powerDownSleep(PowerState pwr_state
, Tick tick
)
1998 // if low power state is active low, schedule to active low power state.
1999 // in reality tCKE is needed to enter active low power. This is neglected
2000 // here and could be added in the future.
2001 if (pwr_state
== PWR_ACT_PDN
) {
2002 schedulePowerEvent(pwr_state
, tick
);
2003 // push command to DRAMPower
2004 cmdList
.push_back(Command(MemCommand::PDN_F_ACT
, 0, tick
));
2005 DPRINTF(DRAMPower
, "%llu,PDN_F_ACT,0,%d\n", divCeil(tick
,
2006 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2007 } else if (pwr_state
== PWR_PRE_PDN
) {
2008 // if low power state is precharge low, schedule to precharge low
2009 // power state. In reality tCKE is needed to enter active low power.
2010 // This is neglected here.
2011 schedulePowerEvent(pwr_state
, tick
);
2012 //push Command to DRAMPower
2013 cmdList
.push_back(Command(MemCommand::PDN_F_PRE
, 0, tick
));
2014 DPRINTF(DRAMPower
, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick
,
2015 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2016 } else if (pwr_state
== PWR_REF
) {
2017 // if a refresh just occured
2018 // transition to PRE_PDN now that all banks are closed
2019 // do not transition to SREF if commands are in Q; stay in PRE_PDN
2020 if (pwrStatePostRefresh
== PWR_ACT_PDN
|| !lowPowerEntryReady()) {
2021 // prechage power down requires tCKE to enter. For simplicity
2022 // this is not considered.
2023 schedulePowerEvent(PWR_PRE_PDN
, tick
);
2024 //push Command to DRAMPower
2025 cmdList
.push_back(Command(MemCommand::PDN_F_PRE
, 0, tick
));
2026 DPRINTF(DRAMPower
, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick
,
2027 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2029 // last low power State was power precharge
2030 assert(pwrStatePostRefresh
== PWR_PRE_PDN
);
2031 // self refresh requires time tCKESR to enter. For simplicity,
2032 // this is not considered.
2033 schedulePowerEvent(PWR_SREF
, tick
);
2034 // push Command to DRAMPower
2035 cmdList
.push_back(Command(MemCommand::SREN
, 0, tick
));
2036 DPRINTF(DRAMPower
, "%llu,SREN,0,%d\n", divCeil(tick
,
2037 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2040 // Ensure that we don't power-down and back up in same tick
2041 // Once we commit to PD entry, do it and wait for at least 1tCK
2042 // This could be replaced with tCKE if/when that is added to the model
2043 wakeUpAllowedAt
= tick
+ memory
.tCK
;
2045 // Transitioning to a low power state, set flag
2046 inLowPowerState
= true;
2050 DRAMCtrl::Rank::scheduleWakeUpEvent(Tick exit_delay
)
2052 Tick wake_up_tick
= std::max(curTick(), wakeUpAllowedAt
);
2054 DPRINTF(DRAMState
, "Scheduling wake-up for rank %d at tick %d\n",
2055 rank
, wake_up_tick
);
2057 // if waking for refresh, hold previous state
2058 // else reset state back to IDLE
2059 if (refreshState
== REF_PD_EXIT
) {
2060 pwrStatePostRefresh
= pwrState
;
2062 // don't automatically transition back to LP state after next REF
2063 pwrStatePostRefresh
= PWR_IDLE
;
2066 // schedule wake-up with event to ensure entry has completed before
2067 // we try to wake-up
2068 schedule(wakeUpEvent
, wake_up_tick
);
2070 for (auto &b
: banks
) {
2071 // respect both causality and any existing bank
2072 // constraints, some banks could already have a
2073 // (auto) precharge scheduled
2074 b
.colAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.colAllowedAt
);
2075 b
.preAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.preAllowedAt
);
2076 b
.actAllowedAt
= std::max(wake_up_tick
+ exit_delay
, b
.actAllowedAt
);
2078 // Transitioning out of low power state, clear flag
2079 inLowPowerState
= false;
2081 // push to DRAMPower
2082 // use pwrStateTrans for cases where we have a power event scheduled
2083 // to enter low power that has not yet been processed
2084 if (pwrStateTrans
== PWR_ACT_PDN
) {
2085 cmdList
.push_back(Command(MemCommand::PUP_ACT
, 0, wake_up_tick
));
2086 DPRINTF(DRAMPower
, "%llu,PUP_ACT,0,%d\n", divCeil(wake_up_tick
,
2087 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2089 } else if (pwrStateTrans
== PWR_PRE_PDN
) {
2090 cmdList
.push_back(Command(MemCommand::PUP_PRE
, 0, wake_up_tick
));
2091 DPRINTF(DRAMPower
, "%llu,PUP_PRE,0,%d\n", divCeil(wake_up_tick
,
2092 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2093 } else if (pwrStateTrans
== PWR_SREF
) {
2094 cmdList
.push_back(Command(MemCommand::SREX
, 0, wake_up_tick
));
2095 DPRINTF(DRAMPower
, "%llu,SREX,0,%d\n", divCeil(wake_up_tick
,
2096 memory
.tCK
) - memory
.timeStampOffset
, rank
);
2101 DRAMCtrl::Rank::processWakeUpEvent()
2103 // Should be in a power-down or self-refresh state
2104 assert((pwrState
== PWR_ACT_PDN
) || (pwrState
== PWR_PRE_PDN
) ||
2105 (pwrState
== PWR_SREF
));
2107 // Check current state to determine transition state
2108 if (pwrState
== PWR_ACT_PDN
) {
2109 // banks still open, transition to PWR_ACT
2110 schedulePowerEvent(PWR_ACT
, curTick());
2112 // transitioning from a precharge power-down or self-refresh state
2113 // banks are closed - transition to PWR_IDLE
2114 schedulePowerEvent(PWR_IDLE
, curTick());
2119 DRAMCtrl::Rank::processPowerEvent()
2121 assert(curTick() >= pwrStateTick
);
2122 // remember where we were, and for how long
2123 Tick duration
= curTick() - pwrStateTick
;
2124 PowerState prev_state
= pwrState
;
2126 // update the accounting
2127 pwrStateTime
[prev_state
] += duration
;
2129 // track to total idle time
2130 if ((prev_state
== PWR_PRE_PDN
) || (prev_state
== PWR_ACT_PDN
) ||
2131 (prev_state
== PWR_SREF
)) {
2132 totalIdleTime
+= duration
;
2135 pwrState
= pwrStateTrans
;
2136 pwrStateTick
= curTick();
2138 // if rank was refreshing, make sure to start scheduling requests again
2139 if (prev_state
== PWR_REF
) {
2140 // bus IDLED prior to REF
2141 // counter should be one for refresh command only
2142 assert(outstandingEvents
== 1);
2143 // REF complete, decrement count
2144 --outstandingEvents
;
2146 DPRINTF(DRAMState
, "Was refreshing for %llu ticks\n", duration
);
2147 // if sleeping after refresh
2148 if (pwrState
!= PWR_IDLE
) {
2149 assert((pwrState
== PWR_PRE_PDN
) || (pwrState
== PWR_SREF
));
2150 DPRINTF(DRAMState
, "Switching to power down state after refreshing"
2151 " rank %d at %llu tick\n", rank
, curTick());
2153 if (pwrState
!= PWR_SREF
) {
2154 // rank is not available in SREF
2155 // don't transition to IDLE in this case
2156 refreshState
= REF_IDLE
;
2158 // a request event could be already scheduled by the state
2159 // machine of the other rank
2160 if (!memory
.nextReqEvent
.scheduled()) {
2161 DPRINTF(DRAM
, "Scheduling next request after refreshing rank %d\n",
2163 schedule(memory
.nextReqEvent
, curTick());
2165 } else if (pwrState
== PWR_ACT
) {
2166 if (refreshState
== REF_PD_EXIT
) {
2167 // kick the refresh event loop into action again
2168 assert(prev_state
== PWR_ACT_PDN
);
2170 // go back to REF event and close banks
2171 refreshState
= REF_PRE
;
2172 schedule(refreshEvent
, curTick());
2174 } else if (pwrState
== PWR_IDLE
) {
2175 DPRINTF(DRAMState
, "All banks precharged\n");
2176 if (prev_state
== PWR_SREF
) {
2177 // set refresh state to REF_SREF_EXIT, ensuring isAvailable
2178 // continues to return false during tXS after SREF exit
2179 // Schedule a refresh which kicks things back into action
2181 refreshState
= REF_SREF_EXIT
;
2182 schedule(refreshEvent
, curTick() + memory
.tXS
);
2184 // if we have a pending refresh, and are now moving to
2185 // the idle state, directly transition to a refresh
2186 if ((refreshState
== REF_PRE
) || (refreshState
== REF_PD_EXIT
)) {
2187 // ensure refresh is restarted only after final PRE command.
2188 // do not restart refresh if controller is in an intermediate
2189 // state, after PRE_PDN exit, when banks are IDLE but an
2190 // ACT is scheduled.
2191 if (!activateEvent
.scheduled()) {
2192 // there should be nothing waiting at this point
2193 assert(!powerEvent
.scheduled());
2194 // update the state in zero time and proceed below
2197 // must have PRE scheduled to transition back to IDLE
2198 // and re-kick off refresh
2199 assert(prechargeEvent
.scheduled());
2205 // we transition to the refresh state, let the refresh state
2206 // machine know of this state update and let it deal with the
2207 // scheduling of the next power state transition as well as the
2208 // following refresh
2209 if (pwrState
== PWR_REF
) {
2210 assert(refreshState
== REF_PRE
|| refreshState
== REF_PD_EXIT
);
2211 DPRINTF(DRAMState
, "Refreshing\n");
2213 // kick the refresh event loop into action again, and that
2214 // in turn will schedule a transition to the idle power
2215 // state once the refresh is done
2216 if (refreshState
== REF_PD_EXIT
) {
2217 // Wait for PD exit timing to complete before issuing REF
2218 schedule(refreshEvent
, curTick() + memory
.tXP
);
2220 schedule(refreshEvent
, curTick());
2222 // Banks transitioned to IDLE, start REF
2223 refreshState
= REF_START
;
2228 DRAMCtrl::Rank::updatePowerStats()
2230 // All commands up to refresh have completed
2231 // flush cmdList to DRAMPower
2234 // update the counters for DRAMPower, passing false to
2235 // indicate that this is not the last command in the
2236 // list. DRAMPower requires this information for the
2237 // correct calculation of the background energy at the end
2238 // of the simulation. Ideally we would want to call this
2239 // function with true once at the end of the
2240 // simulation. However, the discarded energy is extremly
2241 // small and does not effect the final results.
2242 power
.powerlib
.updateCounters(false);
2244 // call the energy function
2245 power
.powerlib
.calcEnergy();
2247 // Get the energy and power from DRAMPower
2248 Data::MemoryPowerModel::Energy energy
=
2249 power
.powerlib
.getEnergy();
2250 Data::MemoryPowerModel::Power rank_power
=
2251 power
.powerlib
.getPower();
2253 actEnergy
= energy
.act_energy
* memory
.devicesPerRank
;
2254 preEnergy
= energy
.pre_energy
* memory
.devicesPerRank
;
2255 readEnergy
= energy
.read_energy
* memory
.devicesPerRank
;
2256 writeEnergy
= energy
.write_energy
* memory
.devicesPerRank
;
2257 refreshEnergy
= energy
.ref_energy
* memory
.devicesPerRank
;
2258 actBackEnergy
= energy
.act_stdby_energy
* memory
.devicesPerRank
;
2259 preBackEnergy
= energy
.pre_stdby_energy
* memory
.devicesPerRank
;
2260 actPowerDownEnergy
= energy
.f_act_pd_energy
* memory
.devicesPerRank
;
2261 prePowerDownEnergy
= energy
.f_pre_pd_energy
* memory
.devicesPerRank
;
2262 selfRefreshEnergy
= energy
.sref_energy
* memory
.devicesPerRank
;
2263 totalEnergy
= energy
.total_energy
* memory
.devicesPerRank
;
2264 averagePower
= rank_power
.average_power
* memory
.devicesPerRank
;
2268 DRAMCtrl::Rank::computeStats()
2270 DPRINTF(DRAM
,"Computing final stats\n");
2272 // Force DRAM power to update counters based on time spent in
2273 // current state up to curTick()
2274 cmdList
.push_back(Command(MemCommand::NOP
, 0, curTick()));
2279 // final update of power state times
2280 pwrStateTime
[pwrState
] += (curTick() - pwrStateTick
);
2281 pwrStateTick
= curTick();
2286 DRAMCtrl::Rank::regStats()
2288 using namespace Stats
;
2292 .name(name() + ".memoryStateTime")
2293 .desc("Time in different power states");
2294 pwrStateTime
.subname(0, "IDLE");
2295 pwrStateTime
.subname(1, "REF");
2296 pwrStateTime
.subname(2, "SREF");
2297 pwrStateTime
.subname(3, "PRE_PDN");
2298 pwrStateTime
.subname(4, "ACT");
2299 pwrStateTime
.subname(5, "ACT_PDN");
2302 .name(name() + ".actEnergy")
2303 .desc("Energy for activate commands per rank (pJ)");
2306 .name(name() + ".preEnergy")
2307 .desc("Energy for precharge commands per rank (pJ)");
2310 .name(name() + ".readEnergy")
2311 .desc("Energy for read commands per rank (pJ)");
2314 .name(name() + ".writeEnergy")
2315 .desc("Energy for write commands per rank (pJ)");
2318 .name(name() + ".refreshEnergy")
2319 .desc("Energy for refresh commands per rank (pJ)");
2322 .name(name() + ".actBackEnergy")
2323 .desc("Energy for active background per rank (pJ)");
2326 .name(name() + ".preBackEnergy")
2327 .desc("Energy for precharge background per rank (pJ)");
2330 .name(name() + ".actPowerDownEnergy")
2331 .desc("Energy for active power-down per rank (pJ)");
2334 .name(name() + ".prePowerDownEnergy")
2335 .desc("Energy for precharge power-down per rank (pJ)");
2338 .name(name() + ".selfRefreshEnergy")
2339 .desc("Energy for self refresh per rank (pJ)");
2342 .name(name() + ".totalEnergy")
2343 .desc("Total energy per rank (pJ)");
2346 .name(name() + ".averagePower")
2347 .desc("Core power per rank (mW)");
2350 .name(name() + ".totalIdleTime")
2351 .desc("Total Idle time Per DRAM Rank");
2353 registerDumpCallback(new RankDumpCallback(this));
2356 DRAMCtrl::regStats()
2358 using namespace Stats
;
2360 AbstractMemory::regStats();
2362 for (auto r
: ranks
) {
2367 .name(name() + ".readReqs")
2368 .desc("Number of read requests accepted");
2371 .name(name() + ".writeReqs")
2372 .desc("Number of write requests accepted");
2375 .name(name() + ".readBursts")
2376 .desc("Number of DRAM read bursts, "
2377 "including those serviced by the write queue");
2380 .name(name() + ".writeBursts")
2381 .desc("Number of DRAM write bursts, "
2382 "including those merged in the write queue");
2385 .name(name() + ".servicedByWrQ")
2386 .desc("Number of DRAM read bursts serviced by the write queue");
2389 .name(name() + ".mergedWrBursts")
2390 .desc("Number of DRAM write bursts merged with an existing one");
2393 .name(name() + ".neitherReadNorWriteReqs")
2394 .desc("Number of requests that are neither read nor write");
2397 .init(banksPerRank
* ranksPerChannel
)
2398 .name(name() + ".perBankRdBursts")
2399 .desc("Per bank write bursts");
2402 .init(banksPerRank
* ranksPerChannel
)
2403 .name(name() + ".perBankWrBursts")
2404 .desc("Per bank write bursts");
2407 .name(name() + ".avgRdQLen")
2408 .desc("Average read queue length when enqueuing")
2412 .name(name() + ".avgWrQLen")
2413 .desc("Average write queue length when enqueuing")
2417 .name(name() + ".totQLat")
2418 .desc("Total ticks spent queuing");
2421 .name(name() + ".totBusLat")
2422 .desc("Total ticks spent in databus transfers");
2425 .name(name() + ".totMemAccLat")
2426 .desc("Total ticks spent from burst creation until serviced "
2430 .name(name() + ".avgQLat")
2431 .desc("Average queueing delay per DRAM burst")
2434 avgQLat
= totQLat
/ (readBursts
- servicedByWrQ
);
2437 .name(name() + ".avgBusLat")
2438 .desc("Average bus latency per DRAM burst")
2441 avgBusLat
= totBusLat
/ (readBursts
- servicedByWrQ
);
2444 .name(name() + ".avgMemAccLat")
2445 .desc("Average memory access latency per DRAM burst")
2448 avgMemAccLat
= totMemAccLat
/ (readBursts
- servicedByWrQ
);
2451 .name(name() + ".numRdRetry")
2452 .desc("Number of times read queue was full causing retry");
2455 .name(name() + ".numWrRetry")
2456 .desc("Number of times write queue was full causing retry");
2459 .name(name() + ".readRowHits")
2460 .desc("Number of row buffer hits during reads");
2463 .name(name() + ".writeRowHits")
2464 .desc("Number of row buffer hits during writes");
2467 .name(name() + ".readRowHitRate")
2468 .desc("Row buffer hit rate for reads")
2471 readRowHitRate
= (readRowHits
/ (readBursts
- servicedByWrQ
)) * 100;
2474 .name(name() + ".writeRowHitRate")
2475 .desc("Row buffer hit rate for writes")
2478 writeRowHitRate
= (writeRowHits
/ (writeBursts
- mergedWrBursts
)) * 100;
2481 .init(ceilLog2(burstSize
) + 1)
2482 .name(name() + ".readPktSize")
2483 .desc("Read request sizes (log2)");
2486 .init(ceilLog2(burstSize
) + 1)
2487 .name(name() + ".writePktSize")
2488 .desc("Write request sizes (log2)");
2491 .init(readBufferSize
)
2492 .name(name() + ".rdQLenPdf")
2493 .desc("What read queue length does an incoming req see");
2496 .init(writeBufferSize
)
2497 .name(name() + ".wrQLenPdf")
2498 .desc("What write queue length does an incoming req see");
2501 .init(maxAccessesPerRow
)
2502 .name(name() + ".bytesPerActivate")
2503 .desc("Bytes accessed per row activation")
2507 .init(readBufferSize
)
2508 .name(name() + ".rdPerTurnAround")
2509 .desc("Reads before turning the bus around for writes")
2513 .init(writeBufferSize
)
2514 .name(name() + ".wrPerTurnAround")
2515 .desc("Writes before turning the bus around for reads")
2519 .name(name() + ".bytesReadDRAM")
2520 .desc("Total number of bytes read from DRAM");
2523 .name(name() + ".bytesReadWrQ")
2524 .desc("Total number of bytes read from write queue");
2527 .name(name() + ".bytesWritten")
2528 .desc("Total number of bytes written to DRAM");
2531 .name(name() + ".bytesReadSys")
2532 .desc("Total read bytes from the system interface side");
2535 .name(name() + ".bytesWrittenSys")
2536 .desc("Total written bytes from the system interface side");
2539 .name(name() + ".avgRdBW")
2540 .desc("Average DRAM read bandwidth in MiByte/s")
2543 avgRdBW
= (bytesReadDRAM
/ 1000000) / simSeconds
;
2546 .name(name() + ".avgWrBW")
2547 .desc("Average achieved write bandwidth in MiByte/s")
2550 avgWrBW
= (bytesWritten
/ 1000000) / simSeconds
;
2553 .name(name() + ".avgRdBWSys")
2554 .desc("Average system read bandwidth in MiByte/s")
2557 avgRdBWSys
= (bytesReadSys
/ 1000000) / simSeconds
;
2560 .name(name() + ".avgWrBWSys")
2561 .desc("Average system write bandwidth in MiByte/s")
2564 avgWrBWSys
= (bytesWrittenSys
/ 1000000) / simSeconds
;
2567 .name(name() + ".peakBW")
2568 .desc("Theoretical peak bandwidth in MiByte/s")
2571 peakBW
= (SimClock::Frequency
/ tBURST
) * burstSize
/ 1000000;
2574 .name(name() + ".busUtil")
2575 .desc("Data bus utilization in percentage")
2577 busUtil
= (avgRdBW
+ avgWrBW
) / peakBW
* 100;
2580 .name(name() + ".totGap")
2581 .desc("Total gap between requests");
2584 .name(name() + ".avgGap")
2585 .desc("Average gap between requests")
2588 avgGap
= totGap
/ (readReqs
+ writeReqs
);
2590 // Stats for DRAM Power calculation based on Micron datasheet
2592 .name(name() + ".busUtilRead")
2593 .desc("Data bus utilization in percentage for reads")
2596 busUtilRead
= avgRdBW
/ peakBW
* 100;
2599 .name(name() + ".busUtilWrite")
2600 .desc("Data bus utilization in percentage for writes")
2603 busUtilWrite
= avgWrBW
/ peakBW
* 100;
2606 .name(name() + ".pageHitRate")
2607 .desc("Row buffer hit rate, read and write combined")
2610 pageHitRate
= (writeRowHits
+ readRowHits
) /
2611 (writeBursts
- mergedWrBursts
+ readBursts
- servicedByWrQ
) * 100;
2615 DRAMCtrl::recvFunctional(PacketPtr pkt
)
2617 // rely on the abstract memory
2618 functionalAccess(pkt
);
2622 DRAMCtrl::getSlavePort(const string
&if_name
, PortID idx
)
2624 if (if_name
!= "port") {
2625 return MemObject::getSlavePort(if_name
, idx
);
2634 // if there is anything in any of our internal queues, keep track
2636 if (!(writeQueue
.empty() && readQueue
.empty() && respQueue
.empty() &&
2637 allRanksDrained())) {
2639 DPRINTF(Drain
, "DRAM controller not drained, write: %d, read: %d,"
2640 " resp: %d\n", writeQueue
.size(), readQueue
.size(),
2643 // the only queue that is not drained automatically over time
2644 // is the write queue, thus kick things into action if needed
2645 if (!writeQueue
.empty() && !nextReqEvent
.scheduled()) {
2646 schedule(nextReqEvent
, curTick());
2649 // also need to kick off events to exit self-refresh
2650 for (auto r
: ranks
) {
2651 // force self-refresh exit, which in turn will issue auto-refresh
2652 if (r
->pwrState
== PWR_SREF
) {
2653 DPRINTF(DRAM
,"Rank%d: Forcing self-refresh wakeup in drain\n",
2655 r
->scheduleWakeUpEvent(tXS
);
2659 return DrainState::Draining
;
2661 return DrainState::Drained
;
2666 DRAMCtrl::allRanksDrained() const
2668 // true until proven false
2669 bool all_ranks_drained
= true;
2670 for (auto r
: ranks
) {
2671 // then verify that the power state is IDLE
2672 // ensuring all banks are closed and rank is not in a low power state
2673 all_ranks_drained
= r
->inPwrIdleState() && all_ranks_drained
;
2675 return all_ranks_drained
;
2679 DRAMCtrl::drainResume()
2681 if (!isTimingMode
&& system()->isTimingMode()) {
2682 // if we switched to timing mode, kick things into action,
2683 // and behave as if we restored from a checkpoint
2685 } else if (isTimingMode
&& !system()->isTimingMode()) {
2686 // if we switch from timing mode, stop the refresh events to
2687 // not cause issues with KVM
2688 for (auto r
: ranks
) {
2694 isTimingMode
= system()->isTimingMode();
2697 DRAMCtrl::MemoryPort::MemoryPort(const std::string
& name
, DRAMCtrl
& _memory
)
2698 : QueuedSlavePort(name
, &_memory
, queue
), queue(_memory
, *this),
2703 DRAMCtrl::MemoryPort::getAddrRanges() const
2705 AddrRangeList ranges
;
2706 ranges
.push_back(memory
.getAddrRange());
2711 DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt
)
2713 pkt
->pushLabel(memory
.name());
2715 if (!queue
.checkFunctional(pkt
)) {
2716 // Default implementation of SimpleTimingPort::recvFunctional()
2717 // calls recvAtomic() and throws away the latency; we can save a
2718 // little here by just not calculating the latency.
2719 memory
.recvFunctional(pkt
);
2726 DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt
)
2728 return memory
.recvAtomic(pkt
);
2732 DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt
)
2734 // pass it to the memory controller
2735 return memory
.recvTimingReq(pkt
);
2739 DRAMCtrlParams::create()
2741 return new DRAMCtrl(this);