2 * Copyright (c) 2010-2016 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
46 #include "base/bitfield.hh"
47 #include "base/trace.hh"
48 #include "debug/DRAM.hh"
49 #include "debug/DRAMPower.hh"
50 #include "debug/DRAMState.hh"
51 #include "debug/Drain.hh"
52 #include "mem/dram_ctrl.hh"
53 #include "sim/system.hh"
58 DRAMCtrl::DRAMCtrl(const DRAMCtrlParams
* p
) :
60 port(name() + ".port", *this), isTimingMode(false),
61 retryRdReq(false), retryWrReq(false),
63 nextReqEvent(this), respondEvent(this),
64 deviceSize(p
->device_size
),
65 deviceBusWidth(p
->device_bus_width
), burstLength(p
->burst_length
),
66 deviceRowBufferSize(p
->device_rowbuffer_size
),
67 devicesPerRank(p
->devices_per_rank
),
68 burstSize((devicesPerRank
* burstLength
* deviceBusWidth
) / 8),
69 rowBufferSize(devicesPerRank
* deviceRowBufferSize
),
70 columnsPerRowBuffer(rowBufferSize
/ burstSize
),
71 columnsPerStripe(range
.interleaved() ? range
.granularity() / burstSize
: 1),
72 ranksPerChannel(p
->ranks_per_channel
),
73 bankGroupsPerRank(p
->bank_groups_per_rank
),
74 bankGroupArch(p
->bank_groups_per_rank
> 0),
75 banksPerRank(p
->banks_per_rank
), channels(p
->channels
), rowsPerBank(0),
76 readBufferSize(p
->read_buffer_size
),
77 writeBufferSize(p
->write_buffer_size
),
78 writeHighThreshold(writeBufferSize
* p
->write_high_thresh_perc
/ 100.0),
79 writeLowThreshold(writeBufferSize
* p
->write_low_thresh_perc
/ 100.0),
80 minWritesPerSwitch(p
->min_writes_per_switch
),
81 writesThisTime(0), readsThisTime(0),
82 tCK(p
->tCK
), tWTR(p
->tWTR
), tRTW(p
->tRTW
), tCS(p
->tCS
), tBURST(p
->tBURST
),
83 tCCD_L(p
->tCCD_L
), tRCD(p
->tRCD
), tCL(p
->tCL
), tRP(p
->tRP
), tRAS(p
->tRAS
),
84 tWR(p
->tWR
), tRTP(p
->tRTP
), tRFC(p
->tRFC
), tREFI(p
->tREFI
), tRRD(p
->tRRD
),
85 tRRD_L(p
->tRRD_L
), tXAW(p
->tXAW
), tXP(p
->tXP
), tXS(p
->tXS
),
86 activationLimit(p
->activation_limit
),
87 memSchedPolicy(p
->mem_sched_policy
), addrMapping(p
->addr_mapping
),
88 pageMgmt(p
->page_policy
),
89 maxAccessesPerRow(p
->max_accesses_per_row
),
90 frontendLatency(p
->static_frontend_latency
),
91 backendLatency(p
->static_backend_latency
),
92 busBusyUntil(0), prevArrival(0),
93 nextReqTime(0), activeRank(0), timeStampOffset(0)
95 // sanity check the ranks since we rely on bit slicing for the
97 fatal_if(!isPowerOf2(ranksPerChannel
), "DRAM rank count of %d is not "
98 "allowed, must be a power of two\n", ranksPerChannel
);
100 fatal_if(!isPowerOf2(burstSize
), "DRAM burst size %d is not allowed, "
101 "must be a power of two\n", burstSize
);
103 for (int i
= 0; i
< ranksPerChannel
; i
++) {
104 Rank
* rank
= new Rank(*this, p
);
105 ranks
.push_back(rank
);
107 rank
->actTicks
.resize(activationLimit
, 0);
108 rank
->banks
.resize(banksPerRank
);
111 for (int b
= 0; b
< banksPerRank
; b
++) {
112 rank
->banks
[b
].bank
= b
;
113 // GDDR addressing of banks to BG is linear.
114 // Here we assume that all DRAM generations address bank groups as
117 // Simply assign lower bits to bank group in order to
118 // rotate across bank groups as banks are incremented
119 // e.g. with 4 banks per bank group and 16 banks total:
120 // banks 0,4,8,12 are in bank group 0
121 // banks 1,5,9,13 are in bank group 1
122 // banks 2,6,10,14 are in bank group 2
123 // banks 3,7,11,15 are in bank group 3
124 rank
->banks
[b
].bankgr
= b
% bankGroupsPerRank
;
126 // No bank groups; simply assign to bank number
127 rank
->banks
[b
].bankgr
= b
;
132 // perform a basic check of the write thresholds
133 if (p
->write_low_thresh_perc
>= p
->write_high_thresh_perc
)
134 fatal("Write buffer low threshold %d must be smaller than the "
135 "high threshold %d\n", p
->write_low_thresh_perc
,
136 p
->write_high_thresh_perc
);
138 // determine the rows per bank by looking at the total capacity
139 uint64_t capacity
= ULL(1) << ceilLog2(AbstractMemory::size());
141 // determine the dram actual capacity from the DRAM config in Mbytes
142 uint64_t deviceCapacity
= deviceSize
/ (1024 * 1024) * devicesPerRank
*
145 // if actual DRAM size does not match memory capacity in system warn!
146 if (deviceCapacity
!= capacity
/ (1024 * 1024))
147 warn("DRAM device capacity (%d Mbytes) does not match the "
148 "address range assigned (%d Mbytes)\n", deviceCapacity
,
149 capacity
/ (1024 * 1024));
151 DPRINTF(DRAM
, "Memory capacity %lld (%lld) bytes\n", capacity
,
152 AbstractMemory::size());
154 DPRINTF(DRAM
, "Row buffer size %d bytes with %d columns per row buffer\n",
155 rowBufferSize
, columnsPerRowBuffer
);
157 rowsPerBank
= capacity
/ (rowBufferSize
* banksPerRank
* ranksPerChannel
);
159 // some basic sanity checks
160 if (tREFI
<= tRP
|| tREFI
<= tRFC
) {
161 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
165 // basic bank group architecture checks ->
167 // must have at least one bank per bank group
168 if (bankGroupsPerRank
> banksPerRank
) {
169 fatal("banks per rank (%d) must be equal to or larger than "
170 "banks groups per rank (%d)\n",
171 banksPerRank
, bankGroupsPerRank
);
173 // must have same number of banks in each bank group
174 if ((banksPerRank
% bankGroupsPerRank
) != 0) {
175 fatal("Banks per rank (%d) must be evenly divisible by bank groups "
176 "per rank (%d) for equal banks per bank group\n",
177 banksPerRank
, bankGroupsPerRank
);
179 // tCCD_L should be greater than minimal, back-to-back burst delay
180 if (tCCD_L
<= tBURST
) {
181 fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
182 "bank groups per rank (%d) is greater than 1\n",
183 tCCD_L
, tBURST
, bankGroupsPerRank
);
185 // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
186 // some datasheets might specify it equal to tRRD
188 fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
189 "bank groups per rank (%d) is greater than 1\n",
190 tRRD_L
, tRRD
, bankGroupsPerRank
);
199 AbstractMemory::init();
201 if (!port
.isConnected()) {
202 fatal("DRAMCtrl %s is unconnected!\n", name());
204 port
.sendRangeChange();
207 // a bit of sanity checks on the interleaving, save it for here to
208 // ensure that the system pointer is initialised
209 if (range
.interleaved()) {
210 if (channels
!= range
.stripes())
211 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
212 name(), range
.stripes(), channels
);
214 if (addrMapping
== Enums::RoRaBaChCo
) {
215 if (rowBufferSize
!= range
.granularity()) {
216 fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
217 "address map\n", name());
219 } else if (addrMapping
== Enums::RoRaBaCoCh
||
220 addrMapping
== Enums::RoCoRaBaCh
) {
221 // for the interleavings with channel bits in the bottom,
222 // if the system uses a channel striping granularity that
223 // is larger than the DRAM burst size, then map the
224 // sequential accesses within a stripe to a number of
225 // columns in the DRAM, effectively placing some of the
226 // lower-order column bits as the least-significant bits
227 // of the address (above the ones denoting the burst size)
228 assert(columnsPerStripe
>= 1);
230 // channel striping has to be done at a granularity that
231 // is equal or larger to a cache line
232 if (system()->cacheLineSize() > range
.granularity()) {
233 fatal("Channel interleaving of %s must be at least as large "
234 "as the cache line size\n", name());
237 // ...and equal or smaller than the row-buffer size
238 if (rowBufferSize
< range
.granularity()) {
239 fatal("Channel interleaving of %s must be at most as large "
240 "as the row-buffer size\n", name());
242 // this is essentially the check above, so just to be sure
243 assert(columnsPerStripe
<= columnsPerRowBuffer
);
251 // remember the memory system mode of operation
252 isTimingMode
= system()->isTimingMode();
255 // timestamp offset should be in clock cycles for DRAMPower
256 timeStampOffset
= divCeil(curTick(), tCK
);
258 // update the start tick for the precharge accounting to the
260 for (auto r
: ranks
) {
261 r
->startup(curTick() + tREFI
- tRP
);
264 // shift the bus busy time sufficiently far ahead that we never
265 // have to worry about negative values when computing the time for
266 // the next request, this will add an insignificant bubble at the
267 // start of simulation
268 busBusyUntil
= curTick() + tRP
+ tRCD
+ tCL
;
273 DRAMCtrl::recvAtomic(PacketPtr pkt
)
275 DPRINTF(DRAM
, "recvAtomic: %s 0x%x\n", pkt
->cmdString(), pkt
->getAddr());
277 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
280 // do the actual memory access and turn the packet into a response
284 if (pkt
->hasData()) {
285 // this value is not supposed to be accurate, just enough to
286 // keep things going, mimic a closed page
287 latency
= tRP
+ tRCD
+ tCL
;
293 DRAMCtrl::readQueueFull(unsigned int neededEntries
) const
295 DPRINTF(DRAM
, "Read queue limit %d, current size %d, entries needed %d\n",
296 readBufferSize
, readQueue
.size() + respQueue
.size(),
300 (readQueue
.size() + respQueue
.size() + neededEntries
) > readBufferSize
;
304 DRAMCtrl::writeQueueFull(unsigned int neededEntries
) const
306 DPRINTF(DRAM
, "Write queue limit %d, current size %d, entries needed %d\n",
307 writeBufferSize
, writeQueue
.size(), neededEntries
);
308 return (writeQueue
.size() + neededEntries
) > writeBufferSize
;
311 DRAMCtrl::DRAMPacket
*
312 DRAMCtrl::decodeAddr(PacketPtr pkt
, Addr dramPktAddr
, unsigned size
,
315 // decode the address based on the address mapping scheme, with
316 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
317 // channel, respectively
320 // use a 64-bit unsigned during the computations as the row is
321 // always the top bits, and check before creating the DRAMPacket
324 // truncate the address to a DRAM burst, which makes it unique to
325 // a specific column, row, bank, rank and channel
326 Addr addr
= dramPktAddr
/ burstSize
;
328 // we have removed the lowest order address bits that denote the
329 // position within the column
330 if (addrMapping
== Enums::RoRaBaChCo
) {
331 // the lowest order bits denote the column to ensure that
332 // sequential cache lines occupy the same row
333 addr
= addr
/ columnsPerRowBuffer
;
335 // take out the channel part of the address
336 addr
= addr
/ channels
;
338 // after the channel bits, get the bank bits to interleave
340 bank
= addr
% banksPerRank
;
341 addr
= addr
/ banksPerRank
;
343 // after the bank, we get the rank bits which thus interleaves
345 rank
= addr
% ranksPerChannel
;
346 addr
= addr
/ ranksPerChannel
;
348 // lastly, get the row bits, no need to remove them from addr
349 row
= addr
% rowsPerBank
;
350 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
351 // take out the lower-order column bits
352 addr
= addr
/ columnsPerStripe
;
354 // take out the channel part of the address
355 addr
= addr
/ channels
;
357 // next, the higher-order column bites
358 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
360 // after the column bits, we get the bank bits to interleave
362 bank
= addr
% banksPerRank
;
363 addr
= addr
/ banksPerRank
;
365 // after the bank, we get the rank bits which thus interleaves
367 rank
= addr
% ranksPerChannel
;
368 addr
= addr
/ ranksPerChannel
;
370 // lastly, get the row bits, no need to remove them from addr
371 row
= addr
% rowsPerBank
;
372 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
373 // optimise for closed page mode and utilise maximum
374 // parallelism of the DRAM (at the cost of power)
376 // take out the lower-order column bits
377 addr
= addr
/ columnsPerStripe
;
379 // take out the channel part of the address, not that this has
380 // to match with how accesses are interleaved between the
381 // controllers in the address mapping
382 addr
= addr
/ channels
;
384 // start with the bank bits, as this provides the maximum
385 // opportunity for parallelism between requests
386 bank
= addr
% banksPerRank
;
387 addr
= addr
/ banksPerRank
;
389 // next get the rank bits
390 rank
= addr
% ranksPerChannel
;
391 addr
= addr
/ ranksPerChannel
;
393 // next, the higher-order column bites
394 addr
= addr
/ (columnsPerRowBuffer
/ columnsPerStripe
);
396 // lastly, get the row bits, no need to remove them from addr
397 row
= addr
% rowsPerBank
;
399 panic("Unknown address mapping policy chosen!");
401 assert(rank
< ranksPerChannel
);
402 assert(bank
< banksPerRank
);
403 assert(row
< rowsPerBank
);
404 assert(row
< Bank::NO_ROW
);
406 DPRINTF(DRAM
, "Address: %lld Rank %d Bank %d Row %d\n",
407 dramPktAddr
, rank
, bank
, row
);
409 // create the corresponding DRAM packet with the entry time and
410 // ready time set to the current tick, the latter will be updated
412 uint16_t bank_id
= banksPerRank
* rank
+ bank
;
413 return new DRAMPacket(pkt
, isRead
, rank
, bank
, row
, bank_id
, dramPktAddr
,
414 size
, ranks
[rank
]->banks
[bank
], *ranks
[rank
]);
418 DRAMCtrl::addToReadQueue(PacketPtr pkt
, unsigned int pktCount
)
420 // only add to the read queue here. whenever the request is
421 // eventually done, set the readyTime, and call schedule()
422 assert(!pkt
->isWrite());
424 assert(pktCount
!= 0);
426 // if the request size is larger than burst size, the pkt is split into
427 // multiple DRAM packets
428 // Note if the pkt starting address is not aligened to burst size, the
429 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
430 // are aligned to burst size boundaries. This is to ensure we accurately
431 // check read packets against packets in write queue.
432 Addr addr
= pkt
->getAddr();
433 unsigned pktsServicedByWrQ
= 0;
434 BurstHelper
* burst_helper
= NULL
;
435 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
436 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
437 pkt
->getAddr() + pkt
->getSize()) - addr
;
438 readPktSize
[ceilLog2(size
)]++;
441 // First check write buffer to see if the data is already at
443 bool foundInWrQ
= false;
444 Addr burst_addr
= burstAlign(addr
);
445 // if the burst address is not present then there is no need
446 // looking any further
447 if (isInWriteQueue
.find(burst_addr
) != isInWriteQueue
.end()) {
448 for (const auto& p
: writeQueue
) {
449 // check if the read is subsumed in the write queue
450 // packet we are looking at
451 if (p
->addr
<= addr
&& (addr
+ size
) <= (p
->addr
+ p
->size
)) {
455 DPRINTF(DRAM
, "Read to addr %lld with size %d serviced by "
456 "write queue\n", addr
, size
);
457 bytesReadWrQ
+= burstSize
;
463 // If not found in the write q, make a DRAM packet and
464 // push it onto the read queue
467 // Make the burst helper for split packets
468 if (pktCount
> 1 && burst_helper
== NULL
) {
469 DPRINTF(DRAM
, "Read to addr %lld translates to %d "
470 "dram requests\n", pkt
->getAddr(), pktCount
);
471 burst_helper
= new BurstHelper(pktCount
);
474 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, true);
475 dram_pkt
->burstHelper
= burst_helper
;
477 assert(!readQueueFull(1));
478 rdQLenPdf
[readQueue
.size() + respQueue
.size()]++;
480 DPRINTF(DRAM
, "Adding to read queue\n");
482 readQueue
.push_back(dram_pkt
);
485 avgRdQLen
= readQueue
.size() + respQueue
.size();
488 // Starting address of next dram pkt (aligend to burstSize boundary)
489 addr
= (addr
| (burstSize
- 1)) + 1;
492 // If all packets are serviced by write queue, we send the repsonse back
493 if (pktsServicedByWrQ
== pktCount
) {
494 accessAndRespond(pkt
, frontendLatency
);
498 // Update how many split packets are serviced by write queue
499 if (burst_helper
!= NULL
)
500 burst_helper
->burstsServiced
= pktsServicedByWrQ
;
502 // If we are not already scheduled to get a request out of the
504 if (!nextReqEvent
.scheduled()) {
505 DPRINTF(DRAM
, "Request scheduled immediately\n");
506 schedule(nextReqEvent
, curTick());
511 DRAMCtrl::addToWriteQueue(PacketPtr pkt
, unsigned int pktCount
)
513 // only add to the write queue here. whenever the request is
514 // eventually done, set the readyTime, and call schedule()
515 assert(pkt
->isWrite());
517 // if the request size is larger than burst size, the pkt is split into
518 // multiple DRAM packets
519 Addr addr
= pkt
->getAddr();
520 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
521 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
522 pkt
->getAddr() + pkt
->getSize()) - addr
;
523 writePktSize
[ceilLog2(size
)]++;
526 // see if we can merge with an existing item in the write
527 // queue and keep track of whether we have merged or not
528 bool merged
= isInWriteQueue
.find(burstAlign(addr
)) !=
529 isInWriteQueue
.end();
531 // if the item was not merged we need to create a new write
534 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, false);
536 assert(writeQueue
.size() < writeBufferSize
);
537 wrQLenPdf
[writeQueue
.size()]++;
539 DPRINTF(DRAM
, "Adding to write queue\n");
541 writeQueue
.push_back(dram_pkt
);
542 isInWriteQueue
.insert(burstAlign(addr
));
543 assert(writeQueue
.size() == isInWriteQueue
.size());
546 avgWrQLen
= writeQueue
.size();
548 DPRINTF(DRAM
, "Merging write burst with existing queue entry\n");
550 // keep track of the fact that this burst effectively
551 // disappeared as it was merged with an existing one
555 // Starting address of next dram pkt (aligend to burstSize boundary)
556 addr
= (addr
| (burstSize
- 1)) + 1;
559 // we do not wait for the writes to be send to the actual memory,
560 // but instead take responsibility for the consistency here and
561 // snoop the write queue for any upcoming reads
562 // @todo, if a pkt size is larger than burst size, we might need a
563 // different front end latency
564 accessAndRespond(pkt
, frontendLatency
);
566 // If we are not already scheduled to get a request out of the
568 if (!nextReqEvent
.scheduled()) {
569 DPRINTF(DRAM
, "Request scheduled immediately\n");
570 schedule(nextReqEvent
, curTick());
575 DRAMCtrl::printQs() const {
576 DPRINTF(DRAM
, "===READ QUEUE===\n\n");
577 for (auto i
= readQueue
.begin() ; i
!= readQueue
.end() ; ++i
) {
578 DPRINTF(DRAM
, "Read %lu\n", (*i
)->addr
);
580 DPRINTF(DRAM
, "\n===RESP QUEUE===\n\n");
581 for (auto i
= respQueue
.begin() ; i
!= respQueue
.end() ; ++i
) {
582 DPRINTF(DRAM
, "Response %lu\n", (*i
)->addr
);
584 DPRINTF(DRAM
, "\n===WRITE QUEUE===\n\n");
585 for (auto i
= writeQueue
.begin() ; i
!= writeQueue
.end() ; ++i
) {
586 DPRINTF(DRAM
, "Write %lu\n", (*i
)->addr
);
591 DRAMCtrl::recvTimingReq(PacketPtr pkt
)
593 // This is where we enter from the outside world
594 DPRINTF(DRAM
, "recvTimingReq: request %s addr %lld size %d\n",
595 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
597 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
600 panic_if(!(pkt
->isRead() || pkt
->isWrite()),
601 "Should only see read and writes at memory controller\n");
603 // Calc avg gap between requests
604 if (prevArrival
!= 0) {
605 totGap
+= curTick() - prevArrival
;
607 prevArrival
= curTick();
610 // Find out how many dram packets a pkt translates to
611 // If the burst size is equal or larger than the pkt size, then a pkt
612 // translates to only one dram packet. Otherwise, a pkt translates to
613 // multiple dram packets
614 unsigned size
= pkt
->getSize();
615 unsigned offset
= pkt
->getAddr() & (burstSize
- 1);
616 unsigned int dram_pkt_count
= divCeil(offset
+ size
, burstSize
);
618 // check local buffers and do not accept if full
621 if (readQueueFull(dram_pkt_count
)) {
622 DPRINTF(DRAM
, "Read queue full, not accepting\n");
623 // remember that we have to retry this port
628 addToReadQueue(pkt
, dram_pkt_count
);
630 bytesReadSys
+= size
;
633 assert(pkt
->isWrite());
635 if (writeQueueFull(dram_pkt_count
)) {
636 DPRINTF(DRAM
, "Write queue full, not accepting\n");
637 // remember that we have to retry this port
642 addToWriteQueue(pkt
, dram_pkt_count
);
644 bytesWrittenSys
+= size
;
652 DRAMCtrl::processRespondEvent()
655 "processRespondEvent(): Some req has reached its readyTime\n");
657 DRAMPacket
* dram_pkt
= respQueue
.front();
659 if (dram_pkt
->burstHelper
) {
660 // it is a split packet
661 dram_pkt
->burstHelper
->burstsServiced
++;
662 if (dram_pkt
->burstHelper
->burstsServiced
==
663 dram_pkt
->burstHelper
->burstCount
) {
664 // we have now serviced all children packets of a system packet
665 // so we can now respond to the requester
666 // @todo we probably want to have a different front end and back
667 // end latency for split packets
668 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
669 delete dram_pkt
->burstHelper
;
670 dram_pkt
->burstHelper
= NULL
;
673 // it is not a split packet
674 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
677 delete respQueue
.front();
678 respQueue
.pop_front();
680 if (!respQueue
.empty()) {
681 assert(respQueue
.front()->readyTime
>= curTick());
682 assert(!respondEvent
.scheduled());
683 schedule(respondEvent
, respQueue
.front()->readyTime
);
685 // if there is nothing left in any queue, signal a drain
686 if (drainState() == DrainState::Draining
&&
687 writeQueue
.empty() && readQueue
.empty() && allRanksDrained()) {
689 DPRINTF(Drain
, "DRAM controller done draining\n");
694 // We have made a location in the queue available at this point,
695 // so if there is a read that was forced to wait, retry now
703 DRAMCtrl::chooseNext(std::deque
<DRAMPacket
*>& queue
, Tick extra_col_delay
)
705 // This method does the arbitration between requests. The chosen
706 // packet is simply moved to the head of the queue. The other
707 // methods know that this is the place to look. For example, with
708 // FCFS, this method does nothing
709 assert(!queue
.empty());
711 // bool to indicate if a packet to an available rank is found
712 bool found_packet
= false;
713 if (queue
.size() == 1) {
714 DRAMPacket
* dram_pkt
= queue
.front();
715 // available rank corresponds to state refresh idle
716 if (ranks
[dram_pkt
->rank
]->isAvailable()) {
718 DPRINTF(DRAM
, "Single request, going to a free rank\n");
720 DPRINTF(DRAM
, "Single request, going to a busy rank\n");
725 if (memSchedPolicy
== Enums::fcfs
) {
726 // check if there is a packet going to a free rank
727 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
728 DRAMPacket
* dram_pkt
= *i
;
729 if (ranks
[dram_pkt
->rank
]->isAvailable()) {
731 queue
.push_front(dram_pkt
);
736 } else if (memSchedPolicy
== Enums::frfcfs
) {
737 found_packet
= reorderQueue(queue
, extra_col_delay
);
739 panic("No scheduling policy chosen\n");
744 DRAMCtrl::reorderQueue(std::deque
<DRAMPacket
*>& queue
, Tick extra_col_delay
)
746 // Only determine this if needed
747 uint64_t earliest_banks
= 0;
748 bool hidden_bank_prep
= false;
750 // search for seamless row hits first, if no seamless row hit is
751 // found then determine if there are other packets that can be issued
752 // without incurring additional bus delay due to bank timing
753 // Will select closed rows first to enable more open row possibilies
754 // in future selections
755 bool found_hidden_bank
= false;
757 // remember if we found a row hit, not seamless, but bank prepped
759 bool found_prepped_pkt
= false;
761 // if we have no row hit, prepped or not, and no seamless packet,
762 // just go for the earliest possible
763 bool found_earliest_pkt
= false;
765 auto selected_pkt_it
= queue
.end();
767 // time we need to issue a column command to be seamless
768 const Tick min_col_at
= std::max(busBusyUntil
- tCL
+ extra_col_delay
,
771 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
772 DRAMPacket
* dram_pkt
= *i
;
773 const Bank
& bank
= dram_pkt
->bankRef
;
775 // check if rank is available, if not, jump to the next packet
776 if (dram_pkt
->rankRef
.isAvailable()) {
777 // check if it is a row hit
778 if (bank
.openRow
== dram_pkt
->row
) {
779 // no additional rank-to-rank or same bank-group
780 // delays, or we switched read/write and might as well
781 // go for the row hit
782 if (bank
.colAllowedAt
<= min_col_at
) {
783 // FCFS within the hits, giving priority to
784 // commands that can issue seamlessly, without
785 // additional delay, such as same rank accesses
786 // and/or different bank-group accesses
787 DPRINTF(DRAM
, "Seamless row buffer hit\n");
789 // no need to look through the remaining queue entries
791 } else if (!found_hidden_bank
&& !found_prepped_pkt
) {
792 // if we did not find a packet to a closed row that can
793 // issue the bank commands without incurring delay, and
794 // did not yet find a packet to a prepped row, remember
797 found_prepped_pkt
= true;
798 DPRINTF(DRAM
, "Prepped row buffer hit\n");
800 } else if (!found_earliest_pkt
) {
801 // if we have not initialised the bank status, do it
802 // now, and only once per scheduling decisions
803 if (earliest_banks
== 0) {
804 // determine entries with earliest bank delay
805 pair
<uint64_t, bool> bankStatus
=
806 minBankPrep(queue
, min_col_at
);
807 earliest_banks
= bankStatus
.first
;
808 hidden_bank_prep
= bankStatus
.second
;
811 // bank is amongst first available banks
812 // minBankPrep will give priority to packets that can
814 if (bits(earliest_banks
, dram_pkt
->bankId
, dram_pkt
->bankId
)) {
815 found_earliest_pkt
= true;
816 found_hidden_bank
= hidden_bank_prep
;
818 // give priority to packets that can issue
819 // bank commands 'behind the scenes'
820 // any additional delay if any will be due to
821 // col-to-col command requirements
822 if (hidden_bank_prep
|| !found_prepped_pkt
)
829 if (selected_pkt_it
!= queue
.end()) {
830 DRAMPacket
* selected_pkt
= *selected_pkt_it
;
831 queue
.erase(selected_pkt_it
);
832 queue
.push_front(selected_pkt
);
840 DRAMCtrl::accessAndRespond(PacketPtr pkt
, Tick static_latency
)
842 DPRINTF(DRAM
, "Responding to Address %lld.. ",pkt
->getAddr());
844 bool needsResponse
= pkt
->needsResponse();
845 // do the actual memory access which also turns the packet into a
849 // turn packet around to go back to requester if response expected
851 // access already turned the packet into a response
852 assert(pkt
->isResponse());
853 // response_time consumes the static latency and is charged also
854 // with headerDelay that takes into account the delay provided by
855 // the xbar and also the payloadDelay that takes into account the
856 // number of data beats.
857 Tick response_time
= curTick() + static_latency
+ pkt
->headerDelay
+
859 // Here we reset the timing of the packet before sending it out.
860 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
862 // queue the packet in the response queue to be sent out after
863 // the static latency has passed
864 port
.schedTimingResp(pkt
, response_time
, true);
866 // @todo the packet is going to be deleted, and the DRAMPacket
867 // is still having a pointer to it
868 pendingDelete
.reset(pkt
);
871 DPRINTF(DRAM
, "Done\n");
877 DRAMCtrl::activateBank(Rank
& rank_ref
, Bank
& bank_ref
,
878 Tick act_tick
, uint32_t row
)
880 assert(rank_ref
.actTicks
.size() == activationLimit
);
882 DPRINTF(DRAM
, "Activate at tick %d\n", act_tick
);
884 // update the open row
885 assert(bank_ref
.openRow
== Bank::NO_ROW
);
886 bank_ref
.openRow
= row
;
888 // start counting anew, this covers both the case when we
889 // auto-precharged, and when this access is forced to
891 bank_ref
.bytesAccessed
= 0;
892 bank_ref
.rowAccesses
= 0;
894 ++rank_ref
.numBanksActive
;
895 assert(rank_ref
.numBanksActive
<= banksPerRank
);
897 DPRINTF(DRAM
, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
898 bank_ref
.bank
, rank_ref
.rank
, act_tick
,
899 ranks
[rank_ref
.rank
]->numBanksActive
);
901 rank_ref
.cmdList
.push_back(Command(MemCommand::ACT
, bank_ref
.bank
,
904 DPRINTF(DRAMPower
, "%llu,ACT,%d,%d\n", divCeil(act_tick
, tCK
) -
905 timeStampOffset
, bank_ref
.bank
, rank_ref
.rank
);
907 // The next access has to respect tRAS for this bank
908 bank_ref
.preAllowedAt
= act_tick
+ tRAS
;
910 // Respect the row-to-column command delay
911 bank_ref
.colAllowedAt
= std::max(act_tick
+ tRCD
, bank_ref
.colAllowedAt
);
913 // start by enforcing tRRD
914 for (int i
= 0; i
< banksPerRank
; i
++) {
915 // next activate to any bank in this rank must not happen
917 if (bankGroupArch
&& (bank_ref
.bankgr
== rank_ref
.banks
[i
].bankgr
)) {
918 // bank group architecture requires longer delays between
919 // ACT commands within the same bank group. Use tRRD_L
921 rank_ref
.banks
[i
].actAllowedAt
= std::max(act_tick
+ tRRD_L
,
922 rank_ref
.banks
[i
].actAllowedAt
);
924 // use shorter tRRD value when either
925 // 1) bank group architecture is not supportted
926 // 2) bank is in a different bank group
927 rank_ref
.banks
[i
].actAllowedAt
= std::max(act_tick
+ tRRD
,
928 rank_ref
.banks
[i
].actAllowedAt
);
932 // next, we deal with tXAW, if the activation limit is disabled
933 // then we directly schedule an activate power event
934 if (!rank_ref
.actTicks
.empty()) {
936 if (rank_ref
.actTicks
.back() &&
937 (act_tick
- rank_ref
.actTicks
.back()) < tXAW
) {
938 panic("Got %d activates in window %d (%llu - %llu) which "
939 "is smaller than %llu\n", activationLimit
, act_tick
-
940 rank_ref
.actTicks
.back(), act_tick
,
941 rank_ref
.actTicks
.back(), tXAW
);
944 // shift the times used for the book keeping, the last element
945 // (highest index) is the oldest one and hence the lowest value
946 rank_ref
.actTicks
.pop_back();
948 // record an new activation (in the future)
949 rank_ref
.actTicks
.push_front(act_tick
);
951 // cannot activate more than X times in time window tXAW, push the
952 // next one (the X + 1'st activate) to be tXAW away from the
953 // oldest in our window of X
954 if (rank_ref
.actTicks
.back() &&
955 (act_tick
- rank_ref
.actTicks
.back()) < tXAW
) {
956 DPRINTF(DRAM
, "Enforcing tXAW with X = %d, next activate "
957 "no earlier than %llu\n", activationLimit
,
958 rank_ref
.actTicks
.back() + tXAW
);
959 for (int j
= 0; j
< banksPerRank
; j
++)
960 // next activate must not happen before end of window
961 rank_ref
.banks
[j
].actAllowedAt
=
962 std::max(rank_ref
.actTicks
.back() + tXAW
,
963 rank_ref
.banks
[j
].actAllowedAt
);
967 // at the point when this activate takes place, make sure we
968 // transition to the active power state
969 if (!rank_ref
.activateEvent
.scheduled())
970 schedule(rank_ref
.activateEvent
, act_tick
);
971 else if (rank_ref
.activateEvent
.when() > act_tick
)
972 // move it sooner in time
973 reschedule(rank_ref
.activateEvent
, act_tick
);
977 DRAMCtrl::prechargeBank(Rank
& rank_ref
, Bank
& bank
, Tick pre_at
, bool trace
)
979 // make sure the bank has an open row
980 assert(bank
.openRow
!= Bank::NO_ROW
);
982 // sample the bytes per activate here since we are closing
984 bytesPerActivate
.sample(bank
.bytesAccessed
);
986 bank
.openRow
= Bank::NO_ROW
;
988 // no precharge allowed before this one
989 bank
.preAllowedAt
= pre_at
;
991 Tick pre_done_at
= pre_at
+ tRP
;
993 bank
.actAllowedAt
= std::max(bank
.actAllowedAt
, pre_done_at
);
995 assert(rank_ref
.numBanksActive
!= 0);
996 --rank_ref
.numBanksActive
;
998 DPRINTF(DRAM
, "Precharging bank %d, rank %d at tick %lld, now got "
999 "%d active\n", bank
.bank
, rank_ref
.rank
, pre_at
,
1000 rank_ref
.numBanksActive
);
1004 rank_ref
.cmdList
.push_back(Command(MemCommand::PRE
, bank
.bank
,
1006 DPRINTF(DRAMPower
, "%llu,PRE,%d,%d\n", divCeil(pre_at
, tCK
) -
1007 timeStampOffset
, bank
.bank
, rank_ref
.rank
);
1009 // if we look at the current number of active banks we might be
1010 // tempted to think the DRAM is now idle, however this can be
1011 // undone by an activate that is scheduled to happen before we
1012 // would have reached the idle state, so schedule an event and
1013 // rather check once we actually make it to the point in time when
1014 // the (last) precharge takes place
1015 if (!rank_ref
.prechargeEvent
.scheduled())
1016 schedule(rank_ref
.prechargeEvent
, pre_done_at
);
1017 else if (rank_ref
.prechargeEvent
.when() < pre_done_at
)
1018 reschedule(rank_ref
.prechargeEvent
, pre_done_at
);
1022 DRAMCtrl::doDRAMAccess(DRAMPacket
* dram_pkt
)
1024 DPRINTF(DRAM
, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1025 dram_pkt
->addr
, dram_pkt
->rank
, dram_pkt
->bank
, dram_pkt
->row
);
1028 Rank
& rank
= dram_pkt
->rankRef
;
1031 Bank
& bank
= dram_pkt
->bankRef
;
1033 // for the state we need to track if it is a row hit or not
1034 bool row_hit
= true;
1036 // respect any constraints on the command (e.g. tRCD or tCCD)
1037 Tick cmd_at
= std::max(bank
.colAllowedAt
, curTick());
1039 // Determine the access latency and update the bank state
1040 if (bank
.openRow
== dram_pkt
->row
) {
1045 // If there is a page open, precharge it.
1046 if (bank
.openRow
!= Bank::NO_ROW
) {
1047 prechargeBank(rank
, bank
, std::max(bank
.preAllowedAt
, curTick()));
1050 // next we need to account for the delay in activating the
1052 Tick act_tick
= std::max(bank
.actAllowedAt
, curTick());
1054 // Record the activation and deal with all the global timing
1055 // constraints caused be a new activation (tRRD and tXAW)
1056 activateBank(rank
, bank
, act_tick
, dram_pkt
->row
);
1058 // issue the command as early as possible
1059 cmd_at
= bank
.colAllowedAt
;
1062 // we need to wait until the bus is available before we can issue
1064 cmd_at
= std::max(cmd_at
, busBusyUntil
- tCL
);
1066 // update the packet ready time
1067 dram_pkt
->readyTime
= cmd_at
+ tCL
+ tBURST
;
1069 // only one burst can use the bus at any one point in time
1070 assert(dram_pkt
->readyTime
- busBusyUntil
>= tBURST
);
1072 // update the time for the next read/write burst for each
1073 // bank (add a max with tCCD/tCCD_L here)
1075 for (int j
= 0; j
< ranksPerChannel
; j
++) {
1076 for (int i
= 0; i
< banksPerRank
; i
++) {
1077 // next burst to same bank group in this rank must not happen
1078 // before tCCD_L. Different bank group timing requirement is
1079 // tBURST; Add tCS for different ranks
1080 if (dram_pkt
->rank
== j
) {
1081 if (bankGroupArch
&&
1082 (bank
.bankgr
== ranks
[j
]->banks
[i
].bankgr
)) {
1083 // bank group architecture requires longer delays between
1084 // RD/WR burst commands to the same bank group.
1085 // Use tCCD_L in this case
1088 // use tBURST (equivalent to tCCD_S), the shorter
1089 // cas-to-cas delay value, when either:
1090 // 1) bank group architecture is not supportted
1091 // 2) bank is in a different bank group
1095 // different rank is by default in a different bank group
1096 // use tBURST (equivalent to tCCD_S), which is the shorter
1097 // cas-to-cas delay in this case
1098 // Add tCS to account for rank-to-rank bus delay requirements
1099 cmd_dly
= tBURST
+ tCS
;
1101 ranks
[j
]->banks
[i
].colAllowedAt
= std::max(cmd_at
+ cmd_dly
,
1102 ranks
[j
]->banks
[i
].colAllowedAt
);
1106 // Save rank of current access
1107 activeRank
= dram_pkt
->rank
;
1109 // If this is a write, we also need to respect the write recovery
1110 // time before a precharge, in the case of a read, respect the
1111 // read to precharge constraint
1112 bank
.preAllowedAt
= std::max(bank
.preAllowedAt
,
1113 dram_pkt
->isRead
? cmd_at
+ tRTP
:
1114 dram_pkt
->readyTime
+ tWR
);
1116 // increment the bytes accessed and the accesses per row
1117 bank
.bytesAccessed
+= burstSize
;
1120 // if we reached the max, then issue with an auto-precharge
1121 bool auto_precharge
= pageMgmt
== Enums::close
||
1122 bank
.rowAccesses
== maxAccessesPerRow
;
1124 // if we did not hit the limit, we might still want to
1126 if (!auto_precharge
&&
1127 (pageMgmt
== Enums::open_adaptive
||
1128 pageMgmt
== Enums::close_adaptive
)) {
1129 // a twist on the open and close page policies:
1130 // 1) open_adaptive page policy does not blindly keep the
1131 // page open, but close it if there are no row hits, and there
1132 // are bank conflicts in the queue
1133 // 2) close_adaptive page policy does not blindly close the
1134 // page, but closes it only if there are no row hits in the queue.
1135 // In this case, only force an auto precharge when there
1136 // are no same page hits in the queue
1137 bool got_more_hits
= false;
1138 bool got_bank_conflict
= false;
1140 // either look at the read queue or write queue
1141 const deque
<DRAMPacket
*>& queue
= dram_pkt
->isRead
? readQueue
:
1143 auto p
= queue
.begin();
1144 // make sure we are not considering the packet that we are
1145 // currently dealing with (which is the head of the queue)
1148 // keep on looking until we find a hit or reach the end of the queue
1149 // 1) if a hit is found, then both open and close adaptive policies keep
1151 // 2) if no hit is found, got_bank_conflict is set to true if a bank
1152 // conflict request is waiting in the queue
1153 while (!got_more_hits
&& p
!= queue
.end()) {
1154 bool same_rank_bank
= (dram_pkt
->rank
== (*p
)->rank
) &&
1155 (dram_pkt
->bank
== (*p
)->bank
);
1156 bool same_row
= dram_pkt
->row
== (*p
)->row
;
1157 got_more_hits
|= same_rank_bank
&& same_row
;
1158 got_bank_conflict
|= same_rank_bank
&& !same_row
;
1162 // auto pre-charge when either
1163 // 1) open_adaptive policy, we have not got any more hits, and
1164 // have a bank conflict
1165 // 2) close_adaptive policy and we have not got any more hits
1166 auto_precharge
= !got_more_hits
&&
1167 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
);
1170 // DRAMPower trace command to be written
1171 std::string mem_cmd
= dram_pkt
->isRead
? "RD" : "WR";
1173 // MemCommand required for DRAMPower library
1174 MemCommand::cmds command
= (mem_cmd
== "RD") ? MemCommand::RD
:
1178 busBusyUntil
= dram_pkt
->readyTime
;
1180 DPRINTF(DRAM
, "Access to %lld, ready at %lld bus busy until %lld.\n",
1181 dram_pkt
->addr
, dram_pkt
->readyTime
, busBusyUntil
);
1183 dram_pkt
->rankRef
.cmdList
.push_back(Command(command
, dram_pkt
->bank
,
1186 DPRINTF(DRAMPower
, "%llu,%s,%d,%d\n", divCeil(cmd_at
, tCK
) -
1187 timeStampOffset
, mem_cmd
, dram_pkt
->bank
, dram_pkt
->rank
);
1189 // if this access should use auto-precharge, then we are
1190 // closing the row after the read/write burst
1191 if (auto_precharge
) {
1192 // if auto-precharge push a PRE command at the correct tick to the
1193 // list used by DRAMPower library to calculate power
1194 prechargeBank(rank
, bank
, std::max(curTick(), bank
.preAllowedAt
));
1196 DPRINTF(DRAM
, "Auto-precharged bank: %d\n", dram_pkt
->bankId
);
1199 // Update the minimum timing between the requests, this is a
1200 // conservative estimate of when we have to schedule the next
1201 // request to not introduce any unecessary bubbles. In most cases
1202 // we will wake up sooner than we have to.
1203 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1205 // Update the stats and schedule the next request
1206 if (dram_pkt
->isRead
) {
1210 bytesReadDRAM
+= burstSize
;
1211 perBankRdBursts
[dram_pkt
->bankId
]++;
1213 // Update latency stats
1214 totMemAccLat
+= dram_pkt
->readyTime
- dram_pkt
->entryTime
;
1215 totBusLat
+= tBURST
;
1216 totQLat
+= cmd_at
- dram_pkt
->entryTime
;
1221 bytesWritten
+= burstSize
;
1222 perBankWrBursts
[dram_pkt
->bankId
]++;
1227 DRAMCtrl::processNextReqEvent()
1230 for (auto r
: ranks
) {
1231 if (!r
->isAvailable()) {
1232 // rank is busy refreshing
1235 // let the rank know that if it was waiting to drain, it
1236 // is now done and ready to proceed
1237 r
->checkDrainDone();
1241 if (busyRanks
== ranksPerChannel
) {
1242 // if all ranks are refreshing wait for them to finish
1243 // and stall this state machine without taking any further
1244 // action, and do not schedule a new nextReqEvent
1248 // pre-emptively set to false. Overwrite if in READ_TO_WRITE
1249 // or WRITE_TO_READ state
1250 bool switched_cmd_type
= false;
1251 if (busState
== READ_TO_WRITE
) {
1252 DPRINTF(DRAM
, "Switching to writes after %d reads with %d reads "
1253 "waiting\n", readsThisTime
, readQueue
.size());
1255 // sample and reset the read-related stats as we are now
1256 // transitioning to writes, and all reads are done
1257 rdPerTurnAround
.sample(readsThisTime
);
1260 // now proceed to do the actual writes
1262 switched_cmd_type
= true;
1263 } else if (busState
== WRITE_TO_READ
) {
1264 DPRINTF(DRAM
, "Switching to reads after %d writes with %d writes "
1265 "waiting\n", writesThisTime
, writeQueue
.size());
1267 wrPerTurnAround
.sample(writesThisTime
);
1271 switched_cmd_type
= true;
1274 // when we get here it is either a read or a write
1275 if (busState
== READ
) {
1277 // track if we should switch or not
1278 bool switch_to_writes
= false;
1280 if (readQueue
.empty()) {
1281 // In the case there is no read request to go next,
1282 // trigger writes if we have passed the low threshold (or
1283 // if we are draining)
1284 if (!writeQueue
.empty() &&
1285 (drainState() == DrainState::Draining
||
1286 writeQueue
.size() > writeLowThreshold
)) {
1288 switch_to_writes
= true;
1290 // check if we are drained
1291 // not done draining until in PWR_IDLE state
1292 // ensuring all banks are closed and
1293 // have exited low power states
1294 if (drainState() == DrainState::Draining
&&
1295 respQueue
.empty() && allRanksDrained()) {
1297 DPRINTF(Drain
, "DRAM controller done draining\n");
1301 // nothing to do, not even any point in scheduling an
1302 // event for the next request
1306 // bool to check if there is a read to a free rank
1307 bool found_read
= false;
1309 // Figure out which read request goes next, and move it to the
1310 // front of the read queue
1311 // If we are changing command type, incorporate the minimum
1312 // bus turnaround delay which will be tCS (different rank) case
1313 found_read
= chooseNext(readQueue
,
1314 switched_cmd_type
? tCS
: 0);
1316 // if no read to an available rank is found then return
1317 // at this point. There could be writes to the available ranks
1318 // which are above the required threshold. However, to
1319 // avoid adding more complexity to the code, return and wait
1320 // for a refresh event to kick things into action again.
1324 DRAMPacket
* dram_pkt
= readQueue
.front();
1325 assert(dram_pkt
->rankRef
.isAvailable());
1326 // here we get a bit creative and shift the bus busy time not
1327 // just the tWTR, but also a CAS latency to capture the fact
1328 // that we are allowed to prepare a new bank, but not issue a
1329 // read command until after tWTR, in essence we capture a
1330 // bubble on the data bus that is tWTR + tCL
1331 if (switched_cmd_type
&& dram_pkt
->rank
== activeRank
) {
1332 busBusyUntil
+= tWTR
+ tCL
;
1335 doDRAMAccess(dram_pkt
);
1337 // At this point we're done dealing with the request
1338 readQueue
.pop_front();
1341 assert(dram_pkt
->size
<= burstSize
);
1342 assert(dram_pkt
->readyTime
>= curTick());
1344 // Insert into response queue. It will be sent back to the
1345 // requestor at its readyTime
1346 if (respQueue
.empty()) {
1347 assert(!respondEvent
.scheduled());
1348 schedule(respondEvent
, dram_pkt
->readyTime
);
1350 assert(respQueue
.back()->readyTime
<= dram_pkt
->readyTime
);
1351 assert(respondEvent
.scheduled());
1354 respQueue
.push_back(dram_pkt
);
1356 // we have so many writes that we have to transition
1357 if (writeQueue
.size() > writeHighThreshold
) {
1358 switch_to_writes
= true;
1362 // switching to writes, either because the read queue is empty
1363 // and the writes have passed the low threshold (or we are
1364 // draining), or because the writes hit the hight threshold
1365 if (switch_to_writes
) {
1366 // transition to writing
1367 busState
= READ_TO_WRITE
;
1370 // bool to check if write to free rank is found
1371 bool found_write
= false;
1373 // If we are changing command type, incorporate the minimum
1374 // bus turnaround delay
1375 found_write
= chooseNext(writeQueue
,
1376 switched_cmd_type
? std::min(tRTW
, tCS
) : 0);
1378 // if no writes to an available rank are found then return.
1379 // There could be reads to the available ranks. However, to avoid
1380 // adding more complexity to the code, return at this point and wait
1381 // for a refresh event to kick things into action again.
1385 DRAMPacket
* dram_pkt
= writeQueue
.front();
1386 assert(dram_pkt
->rankRef
.isAvailable());
1388 assert(dram_pkt
->size
<= burstSize
);
1390 // add a bubble to the data bus, as defined by the
1391 // tRTW when access is to the same rank as previous burst
1392 // Different rank timing is handled with tCS, which is
1393 // applied to colAllowedAt
1394 if (switched_cmd_type
&& dram_pkt
->rank
== activeRank
) {
1395 busBusyUntil
+= tRTW
;
1398 doDRAMAccess(dram_pkt
);
1400 writeQueue
.pop_front();
1401 isInWriteQueue
.erase(burstAlign(dram_pkt
->addr
));
1404 // If we emptied the write queue, or got sufficiently below the
1405 // threshold (using the minWritesPerSwitch as the hysteresis) and
1406 // are not draining, or we have reads waiting and have done enough
1407 // writes, then switch to reads.
1408 if (writeQueue
.empty() ||
1409 (writeQueue
.size() + minWritesPerSwitch
< writeLowThreshold
&&
1410 drainState() != DrainState::Draining
) ||
1411 (!readQueue
.empty() && writesThisTime
>= minWritesPerSwitch
)) {
1412 // turn the bus back around for reads again
1413 busState
= WRITE_TO_READ
;
1415 // note that the we switch back to reads also in the idle
1416 // case, which eventually will check for any draining and
1417 // also pause any further scheduling if there is really
1421 // It is possible that a refresh to another rank kicks things back into
1422 // action before reaching this point.
1423 if (!nextReqEvent
.scheduled())
1424 schedule(nextReqEvent
, std::max(nextReqTime
, curTick()));
1426 // If there is space available and we have writes waiting then let
1427 // them retry. This is done here to ensure that the retry does not
1428 // cause a nextReqEvent to be scheduled before we do so as part of
1429 // the next request processing
1430 if (retryWrReq
&& writeQueue
.size() < writeBufferSize
) {
1432 port
.sendRetryReq();
1436 pair
<uint64_t, bool>
1437 DRAMCtrl::minBankPrep(const deque
<DRAMPacket
*>& queue
,
1438 Tick min_col_at
) const
1440 uint64_t bank_mask
= 0;
1441 Tick min_act_at
= MaxTick
;
1443 // latest Tick for which ACT can occur without incurring additoinal
1444 // delay on the data bus
1445 const Tick hidden_act_max
= std::max(min_col_at
- tRCD
, curTick());
1447 // Flag condition when burst can issue back-to-back with previous burst
1448 bool found_seamless_bank
= false;
1450 // Flag condition when bank can be opened without incurring additional
1451 // delay on the data bus
1452 bool hidden_bank_prep
= false;
1454 // determine if we have queued transactions targetting the
1456 vector
<bool> got_waiting(ranksPerChannel
* banksPerRank
, false);
1457 for (const auto& p
: queue
) {
1458 if (p
->rankRef
.isAvailable())
1459 got_waiting
[p
->bankId
] = true;
1462 // Find command with optimal bank timing
1463 // Will prioritize commands that can issue seamlessly.
1464 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1465 for (int j
= 0; j
< banksPerRank
; j
++) {
1466 uint16_t bank_id
= i
* banksPerRank
+ j
;
1468 // if we have waiting requests for the bank, and it is
1469 // amongst the first available, update the mask
1470 if (got_waiting
[bank_id
]) {
1471 // make sure this rank is not currently refreshing.
1472 assert(ranks
[i
]->isAvailable());
1473 // simplistic approximation of when the bank can issue
1474 // an activate, ignoring any rank-to-rank switching
1475 // cost in this calculation
1476 Tick act_at
= ranks
[i
]->banks
[j
].openRow
== Bank::NO_ROW
?
1477 std::max(ranks
[i
]->banks
[j
].actAllowedAt
, curTick()) :
1478 std::max(ranks
[i
]->banks
[j
].preAllowedAt
, curTick()) + tRP
;
1480 // When is the earliest the R/W burst can issue?
1481 Tick col_at
= std::max(ranks
[i
]->banks
[j
].colAllowedAt
,
1484 // bank can issue burst back-to-back (seamlessly) with
1486 bool new_seamless_bank
= col_at
<= min_col_at
;
1488 // if we found a new seamless bank or we have no
1489 // seamless banks, and got a bank with an earlier
1490 // activate time, it should be added to the bit mask
1491 if (new_seamless_bank
||
1492 (!found_seamless_bank
&& act_at
<= min_act_at
)) {
1493 // if we did not have a seamless bank before, and
1494 // we do now, reset the bank mask, also reset it
1495 // if we have not yet found a seamless bank and
1496 // the activate time is smaller than what we have
1498 if (!found_seamless_bank
&&
1499 (new_seamless_bank
|| act_at
< min_act_at
)) {
1503 found_seamless_bank
|= new_seamless_bank
;
1505 // ACT can occur 'behind the scenes'
1506 hidden_bank_prep
= act_at
<= hidden_act_max
;
1508 // set the bit corresponding to the available bank
1509 replaceBits(bank_mask
, bank_id
, bank_id
, 1);
1510 min_act_at
= act_at
;
1516 return make_pair(bank_mask
, hidden_bank_prep
);
1519 DRAMCtrl::Rank::Rank(DRAMCtrl
& _memory
, const DRAMCtrlParams
* _p
)
1520 : EventManager(&_memory
), memory(_memory
),
1521 pwrStateTrans(PWR_IDLE
), pwrState(PWR_IDLE
), pwrStateTick(0),
1522 refreshState(REF_IDLE
), refreshDueAt(0),
1523 power(_p
, false), numBanksActive(0),
1524 activateEvent(*this), prechargeEvent(*this),
1525 refreshEvent(*this), powerEvent(*this)
1529 DRAMCtrl::Rank::startup(Tick ref_tick
)
1531 assert(ref_tick
> curTick());
1533 pwrStateTick
= curTick();
1535 // kick off the refresh, and give ourselves enough time to
1537 schedule(refreshEvent
, ref_tick
);
1541 DRAMCtrl::Rank::suspend()
1543 deschedule(refreshEvent
);
1550 DRAMCtrl::Rank::checkDrainDone()
1552 // if this rank was waiting to drain it is now able to proceed to
1554 if (refreshState
== REF_DRAIN
) {
1555 DPRINTF(DRAM
, "Refresh drain done, now precharging\n");
1557 refreshState
= REF_PRE
;
1559 // hand control back to the refresh event loop
1560 schedule(refreshEvent
, curTick());
1565 DRAMCtrl::Rank::flushCmdList()
1567 // at the moment sort the list of commands and update the counters
1568 // for DRAMPower libray when doing a refresh
1569 sort(cmdList
.begin(), cmdList
.end(), DRAMCtrl::sortTime
);
1571 auto next_iter
= cmdList
.begin();
1572 // push to commands to DRAMPower
1573 for ( ; next_iter
!= cmdList
.end() ; ++next_iter
) {
1574 Command cmd
= *next_iter
;
1575 if (cmd
.timeStamp
<= curTick()) {
1576 // Move all commands at or before curTick to DRAMPower
1577 power
.powerlib
.doCommand(cmd
.type
, cmd
.bank
,
1578 divCeil(cmd
.timeStamp
, memory
.tCK
) -
1579 memory
.timeStampOffset
);
1581 // done - found all commands at or before curTick()
1582 // next_iter references the 1st command after curTick
1586 // reset cmdList to only contain commands after curTick
1587 // if there are no commands after curTick, updated cmdList will be empty
1588 // in this case, next_iter is cmdList.end()
1589 cmdList
.assign(next_iter
, cmdList
.end());
1593 DRAMCtrl::Rank::processActivateEvent()
1595 // we should transition to the active state as soon as any bank is active
1596 if (pwrState
!= PWR_ACT
)
1597 // note that at this point numBanksActive could be back at
1598 // zero again due to a precharge scheduled in the future
1599 schedulePowerEvent(PWR_ACT
, curTick());
1603 DRAMCtrl::Rank::processPrechargeEvent()
1605 // if we reached zero, then special conditions apply as we track
1606 // if all banks are precharged for the power models
1607 if (numBanksActive
== 0) {
1608 // we should transition to the idle state when the last bank
1610 schedulePowerEvent(PWR_IDLE
, curTick());
1615 DRAMCtrl::Rank::processRefreshEvent()
1617 // when first preparing the refresh, remember when it was due
1618 if (refreshState
== REF_IDLE
) {
1619 // remember when the refresh is due
1620 refreshDueAt
= curTick();
1623 refreshState
= REF_DRAIN
;
1625 DPRINTF(DRAM
, "Refresh due\n");
1628 // let any scheduled read or write to the same rank go ahead,
1629 // after which it will
1630 // hand control back to this event loop
1631 if (refreshState
== REF_DRAIN
) {
1632 // if a request is at the moment being handled and this request is
1633 // accessing the current rank then wait for it to finish
1634 if ((rank
== memory
.activeRank
)
1635 && (memory
.nextReqEvent
.scheduled())) {
1636 // hand control over to the request loop until it is
1638 DPRINTF(DRAM
, "Refresh awaiting draining\n");
1642 refreshState
= REF_PRE
;
1646 // at this point, ensure that all banks are precharged
1647 if (refreshState
== REF_PRE
) {
1648 // precharge any active bank if we are not already in the idle
1650 if (pwrState
!= PWR_IDLE
) {
1651 // at the moment, we use a precharge all even if there is
1652 // only a single bank open
1653 DPRINTF(DRAM
, "Precharging all\n");
1655 // first determine when we can precharge
1656 Tick pre_at
= curTick();
1658 for (auto &b
: banks
) {
1659 // respect both causality and any existing bank
1660 // constraints, some banks could already have a
1661 // (auto) precharge scheduled
1662 pre_at
= std::max(b
.preAllowedAt
, pre_at
);
1665 // make sure all banks per rank are precharged, and for those that
1666 // already are, update their availability
1667 Tick act_allowed_at
= pre_at
+ memory
.tRP
;
1669 for (auto &b
: banks
) {
1670 if (b
.openRow
!= Bank::NO_ROW
) {
1671 memory
.prechargeBank(*this, b
, pre_at
, false);
1673 b
.actAllowedAt
= std::max(b
.actAllowedAt
, act_allowed_at
);
1674 b
.preAllowedAt
= std::max(b
.preAllowedAt
, pre_at
);
1678 // precharge all banks in rank
1679 cmdList
.push_back(Command(MemCommand::PREA
, 0, pre_at
));
1681 DPRINTF(DRAMPower
, "%llu,PREA,0,%d\n",
1682 divCeil(pre_at
, memory
.tCK
) -
1683 memory
.timeStampOffset
, rank
);
1685 DPRINTF(DRAM
, "All banks already precharged, starting refresh\n");
1687 // go ahead and kick the power state machine into gear if
1688 // we are already idle
1689 schedulePowerEvent(PWR_REF
, curTick());
1692 refreshState
= REF_RUN
;
1693 assert(numBanksActive
== 0);
1695 // wait for all banks to be precharged, at which point the
1696 // power state machine will transition to the idle state, and
1697 // automatically move to a refresh, at that point it will also
1698 // call this method to get the refresh event loop going again
1702 // last but not least we perform the actual refresh
1703 if (refreshState
== REF_RUN
) {
1704 // should never get here with any banks active
1705 assert(numBanksActive
== 0);
1706 assert(pwrState
== PWR_REF
);
1708 Tick ref_done_at
= curTick() + memory
.tRFC
;
1710 for (auto &b
: banks
) {
1711 b
.actAllowedAt
= ref_done_at
;
1714 // at the moment this affects all ranks
1715 cmdList
.push_back(Command(MemCommand::REF
, 0, curTick()));
1720 DPRINTF(DRAMPower
, "%llu,REF,0,%d\n", divCeil(curTick(), memory
.tCK
) -
1721 memory
.timeStampOffset
, rank
);
1723 // make sure we did not wait so long that we cannot make up
1725 if (refreshDueAt
+ memory
.tREFI
< ref_done_at
) {
1726 fatal("Refresh was delayed so long we cannot catch up\n");
1729 // compensate for the delay in actually performing the refresh
1730 // when scheduling the next one
1731 schedule(refreshEvent
, refreshDueAt
+ memory
.tREFI
- memory
.tRP
);
1733 assert(!powerEvent
.scheduled());
1735 // move to the idle power state once the refresh is done, this
1736 // will also move the refresh state machine to the refresh
1738 schedulePowerEvent(PWR_IDLE
, ref_done_at
);
1740 DPRINTF(DRAMState
, "Refresh done at %llu and next refresh at %llu\n",
1741 ref_done_at
, refreshDueAt
+ memory
.tREFI
);
1746 DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state
, Tick tick
)
1748 // respect causality
1749 assert(tick
>= curTick());
1751 if (!powerEvent
.scheduled()) {
1752 DPRINTF(DRAMState
, "Scheduling power event at %llu to state %d\n",
1755 // insert the new transition
1756 pwrStateTrans
= pwr_state
;
1758 schedule(powerEvent
, tick
);
1760 panic("Scheduled power event at %llu to state %d, "
1761 "with scheduled event at %llu to %d\n", tick
, pwr_state
,
1762 powerEvent
.when(), pwrStateTrans
);
1767 DRAMCtrl::Rank::processPowerEvent()
1769 // remember where we were, and for how long
1770 Tick duration
= curTick() - pwrStateTick
;
1771 PowerState prev_state
= pwrState
;
1773 // update the accounting
1774 pwrStateTime
[prev_state
] += duration
;
1776 pwrState
= pwrStateTrans
;
1777 pwrStateTick
= curTick();
1779 if (pwrState
== PWR_IDLE
) {
1780 DPRINTF(DRAMState
, "All banks precharged\n");
1782 // if we were refreshing, make sure we start scheduling requests again
1783 if (prev_state
== PWR_REF
) {
1784 DPRINTF(DRAMState
, "Was refreshing for %llu ticks\n", duration
);
1785 assert(pwrState
== PWR_IDLE
);
1787 // kick things into action again
1788 refreshState
= REF_IDLE
;
1789 // a request event could be already scheduled by the state
1790 // machine of the other rank
1791 if (!memory
.nextReqEvent
.scheduled())
1792 schedule(memory
.nextReqEvent
, curTick());
1794 assert(prev_state
== PWR_ACT
);
1796 // if we have a pending refresh, and are now moving to
1797 // the idle state, direclty transition to a refresh
1798 if (refreshState
== REF_RUN
) {
1799 // there should be nothing waiting at this point
1800 assert(!powerEvent
.scheduled());
1802 // update the state in zero time and proceed below
1808 // we transition to the refresh state, let the refresh state
1809 // machine know of this state update and let it deal with the
1810 // scheduling of the next power state transition as well as the
1811 // following refresh
1812 if (pwrState
== PWR_REF
) {
1813 DPRINTF(DRAMState
, "Refreshing\n");
1814 // kick the refresh event loop into action again, and that
1815 // in turn will schedule a transition to the idle power
1816 // state once the refresh is done
1817 assert(refreshState
== REF_RUN
);
1818 processRefreshEvent();
1823 DRAMCtrl::Rank::updatePowerStats()
1825 // All commands up to refresh have completed
1826 // flush cmdList to DRAMPower
1829 // update the counters for DRAMPower, passing false to
1830 // indicate that this is not the last command in the
1831 // list. DRAMPower requires this information for the
1832 // correct calculation of the background energy at the end
1833 // of the simulation. Ideally we would want to call this
1834 // function with true once at the end of the
1835 // simulation. However, the discarded energy is extremly
1836 // small and does not effect the final results.
1837 power
.powerlib
.updateCounters(false);
1839 // call the energy function
1840 power
.powerlib
.calcEnergy();
1842 // Get the energy and power from DRAMPower
1843 Data::MemoryPowerModel::Energy energy
=
1844 power
.powerlib
.getEnergy();
1845 Data::MemoryPowerModel::Power rank_power
=
1846 power
.powerlib
.getPower();
1848 actEnergy
= energy
.act_energy
* memory
.devicesPerRank
;
1849 preEnergy
= energy
.pre_energy
* memory
.devicesPerRank
;
1850 readEnergy
= energy
.read_energy
* memory
.devicesPerRank
;
1851 writeEnergy
= energy
.write_energy
* memory
.devicesPerRank
;
1852 refreshEnergy
= energy
.ref_energy
* memory
.devicesPerRank
;
1853 actBackEnergy
= energy
.act_stdby_energy
* memory
.devicesPerRank
;
1854 preBackEnergy
= energy
.pre_stdby_energy
* memory
.devicesPerRank
;
1855 totalEnergy
= energy
.total_energy
* memory
.devicesPerRank
;
1856 averagePower
= rank_power
.average_power
* memory
.devicesPerRank
;
1860 DRAMCtrl::Rank::computeStats()
1862 DPRINTF(DRAM
,"Computing final stats\n");
1864 // Force DRAM power to update counters based on time spent in
1865 // current state up to curTick()
1866 cmdList
.push_back(Command(MemCommand::NOP
, 0, curTick()));
1871 // final update of power state times
1872 pwrStateTime
[pwrState
] += (curTick() - pwrStateTick
);
1873 pwrStateTick
= curTick();
1878 DRAMCtrl::Rank::regStats()
1880 using namespace Stats
;
1884 .name(name() + ".memoryStateTime")
1885 .desc("Time in different power states");
1886 pwrStateTime
.subname(0, "IDLE");
1887 pwrStateTime
.subname(1, "REF");
1888 pwrStateTime
.subname(2, "PRE_PDN");
1889 pwrStateTime
.subname(3, "ACT");
1890 pwrStateTime
.subname(4, "ACT_PDN");
1893 .name(name() + ".actEnergy")
1894 .desc("Energy for activate commands per rank (pJ)");
1897 .name(name() + ".preEnergy")
1898 .desc("Energy for precharge commands per rank (pJ)");
1901 .name(name() + ".readEnergy")
1902 .desc("Energy for read commands per rank (pJ)");
1905 .name(name() + ".writeEnergy")
1906 .desc("Energy for write commands per rank (pJ)");
1909 .name(name() + ".refreshEnergy")
1910 .desc("Energy for refresh commands per rank (pJ)");
1913 .name(name() + ".actBackEnergy")
1914 .desc("Energy for active background per rank (pJ)");
1917 .name(name() + ".preBackEnergy")
1918 .desc("Energy for precharge background per rank (pJ)");
1921 .name(name() + ".totalEnergy")
1922 .desc("Total energy per rank (pJ)");
1925 .name(name() + ".averagePower")
1926 .desc("Core power per rank (mW)");
1928 registerDumpCallback(new RankDumpCallback(this));
1931 DRAMCtrl::regStats()
1933 using namespace Stats
;
1935 AbstractMemory::regStats();
1937 for (auto r
: ranks
) {
1942 .name(name() + ".readReqs")
1943 .desc("Number of read requests accepted");
1946 .name(name() + ".writeReqs")
1947 .desc("Number of write requests accepted");
1950 .name(name() + ".readBursts")
1951 .desc("Number of DRAM read bursts, "
1952 "including those serviced by the write queue");
1955 .name(name() + ".writeBursts")
1956 .desc("Number of DRAM write bursts, "
1957 "including those merged in the write queue");
1960 .name(name() + ".servicedByWrQ")
1961 .desc("Number of DRAM read bursts serviced by the write queue");
1964 .name(name() + ".mergedWrBursts")
1965 .desc("Number of DRAM write bursts merged with an existing one");
1968 .name(name() + ".neitherReadNorWriteReqs")
1969 .desc("Number of requests that are neither read nor write");
1972 .init(banksPerRank
* ranksPerChannel
)
1973 .name(name() + ".perBankRdBursts")
1974 .desc("Per bank write bursts");
1977 .init(banksPerRank
* ranksPerChannel
)
1978 .name(name() + ".perBankWrBursts")
1979 .desc("Per bank write bursts");
1982 .name(name() + ".avgRdQLen")
1983 .desc("Average read queue length when enqueuing")
1987 .name(name() + ".avgWrQLen")
1988 .desc("Average write queue length when enqueuing")
1992 .name(name() + ".totQLat")
1993 .desc("Total ticks spent queuing");
1996 .name(name() + ".totBusLat")
1997 .desc("Total ticks spent in databus transfers");
2000 .name(name() + ".totMemAccLat")
2001 .desc("Total ticks spent from burst creation until serviced "
2005 .name(name() + ".avgQLat")
2006 .desc("Average queueing delay per DRAM burst")
2009 avgQLat
= totQLat
/ (readBursts
- servicedByWrQ
);
2012 .name(name() + ".avgBusLat")
2013 .desc("Average bus latency per DRAM burst")
2016 avgBusLat
= totBusLat
/ (readBursts
- servicedByWrQ
);
2019 .name(name() + ".avgMemAccLat")
2020 .desc("Average memory access latency per DRAM burst")
2023 avgMemAccLat
= totMemAccLat
/ (readBursts
- servicedByWrQ
);
2026 .name(name() + ".numRdRetry")
2027 .desc("Number of times read queue was full causing retry");
2030 .name(name() + ".numWrRetry")
2031 .desc("Number of times write queue was full causing retry");
2034 .name(name() + ".readRowHits")
2035 .desc("Number of row buffer hits during reads");
2038 .name(name() + ".writeRowHits")
2039 .desc("Number of row buffer hits during writes");
2042 .name(name() + ".readRowHitRate")
2043 .desc("Row buffer hit rate for reads")
2046 readRowHitRate
= (readRowHits
/ (readBursts
- servicedByWrQ
)) * 100;
2049 .name(name() + ".writeRowHitRate")
2050 .desc("Row buffer hit rate for writes")
2053 writeRowHitRate
= (writeRowHits
/ (writeBursts
- mergedWrBursts
)) * 100;
2056 .init(ceilLog2(burstSize
) + 1)
2057 .name(name() + ".readPktSize")
2058 .desc("Read request sizes (log2)");
2061 .init(ceilLog2(burstSize
) + 1)
2062 .name(name() + ".writePktSize")
2063 .desc("Write request sizes (log2)");
2066 .init(readBufferSize
)
2067 .name(name() + ".rdQLenPdf")
2068 .desc("What read queue length does an incoming req see");
2071 .init(writeBufferSize
)
2072 .name(name() + ".wrQLenPdf")
2073 .desc("What write queue length does an incoming req see");
2076 .init(maxAccessesPerRow
)
2077 .name(name() + ".bytesPerActivate")
2078 .desc("Bytes accessed per row activation")
2082 .init(readBufferSize
)
2083 .name(name() + ".rdPerTurnAround")
2084 .desc("Reads before turning the bus around for writes")
2088 .init(writeBufferSize
)
2089 .name(name() + ".wrPerTurnAround")
2090 .desc("Writes before turning the bus around for reads")
2094 .name(name() + ".bytesReadDRAM")
2095 .desc("Total number of bytes read from DRAM");
2098 .name(name() + ".bytesReadWrQ")
2099 .desc("Total number of bytes read from write queue");
2102 .name(name() + ".bytesWritten")
2103 .desc("Total number of bytes written to DRAM");
2106 .name(name() + ".bytesReadSys")
2107 .desc("Total read bytes from the system interface side");
2110 .name(name() + ".bytesWrittenSys")
2111 .desc("Total written bytes from the system interface side");
2114 .name(name() + ".avgRdBW")
2115 .desc("Average DRAM read bandwidth in MiByte/s")
2118 avgRdBW
= (bytesReadDRAM
/ 1000000) / simSeconds
;
2121 .name(name() + ".avgWrBW")
2122 .desc("Average achieved write bandwidth in MiByte/s")
2125 avgWrBW
= (bytesWritten
/ 1000000) / simSeconds
;
2128 .name(name() + ".avgRdBWSys")
2129 .desc("Average system read bandwidth in MiByte/s")
2132 avgRdBWSys
= (bytesReadSys
/ 1000000) / simSeconds
;
2135 .name(name() + ".avgWrBWSys")
2136 .desc("Average system write bandwidth in MiByte/s")
2139 avgWrBWSys
= (bytesWrittenSys
/ 1000000) / simSeconds
;
2142 .name(name() + ".peakBW")
2143 .desc("Theoretical peak bandwidth in MiByte/s")
2146 peakBW
= (SimClock::Frequency
/ tBURST
) * burstSize
/ 1000000;
2149 .name(name() + ".busUtil")
2150 .desc("Data bus utilization in percentage")
2152 busUtil
= (avgRdBW
+ avgWrBW
) / peakBW
* 100;
2155 .name(name() + ".totGap")
2156 .desc("Total gap between requests");
2159 .name(name() + ".avgGap")
2160 .desc("Average gap between requests")
2163 avgGap
= totGap
/ (readReqs
+ writeReqs
);
2165 // Stats for DRAM Power calculation based on Micron datasheet
2167 .name(name() + ".busUtilRead")
2168 .desc("Data bus utilization in percentage for reads")
2171 busUtilRead
= avgRdBW
/ peakBW
* 100;
2174 .name(name() + ".busUtilWrite")
2175 .desc("Data bus utilization in percentage for writes")
2178 busUtilWrite
= avgWrBW
/ peakBW
* 100;
2181 .name(name() + ".pageHitRate")
2182 .desc("Row buffer hit rate, read and write combined")
2185 pageHitRate
= (writeRowHits
+ readRowHits
) /
2186 (writeBursts
- mergedWrBursts
+ readBursts
- servicedByWrQ
) * 100;
2190 DRAMCtrl::recvFunctional(PacketPtr pkt
)
2192 // rely on the abstract memory
2193 functionalAccess(pkt
);
2197 DRAMCtrl::getSlavePort(const string
&if_name
, PortID idx
)
2199 if (if_name
!= "port") {
2200 return MemObject::getSlavePort(if_name
, idx
);
2209 // if there is anything in any of our internal queues, keep track
2211 if (!(writeQueue
.empty() && readQueue
.empty() && respQueue
.empty() &&
2212 allRanksDrained())) {
2214 DPRINTF(Drain
, "DRAM controller not drained, write: %d, read: %d,"
2215 " resp: %d\n", writeQueue
.size(), readQueue
.size(),
2218 // the only part that is not drained automatically over time
2219 // is the write queue, thus kick things into action if needed
2220 if (!writeQueue
.empty() && !nextReqEvent
.scheduled()) {
2221 schedule(nextReqEvent
, curTick());
2223 return DrainState::Draining
;
2225 return DrainState::Drained
;
2230 DRAMCtrl::allRanksDrained() const
2232 // true until proven false
2233 bool all_ranks_drained
= true;
2234 for (auto r
: ranks
) {
2235 // then verify that the power state is IDLE
2236 // ensuring all banks are closed and rank is not in a low power state
2237 all_ranks_drained
= r
->inPwrIdleState() && all_ranks_drained
;
2239 return all_ranks_drained
;
2243 DRAMCtrl::drainResume()
2245 if (!isTimingMode
&& system()->isTimingMode()) {
2246 // if we switched to timing mode, kick things into action,
2247 // and behave as if we restored from a checkpoint
2249 } else if (isTimingMode
&& !system()->isTimingMode()) {
2250 // if we switch from timing mode, stop the refresh events to
2251 // not cause issues with KVM
2252 for (auto r
: ranks
) {
2258 isTimingMode
= system()->isTimingMode();
2261 DRAMCtrl::MemoryPort::MemoryPort(const std::string
& name
, DRAMCtrl
& _memory
)
2262 : QueuedSlavePort(name
, &_memory
, queue
), queue(_memory
, *this),
2267 DRAMCtrl::MemoryPort::getAddrRanges() const
2269 AddrRangeList ranges
;
2270 ranges
.push_back(memory
.getAddrRange());
2275 DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt
)
2277 pkt
->pushLabel(memory
.name());
2279 if (!queue
.checkFunctional(pkt
)) {
2280 // Default implementation of SimpleTimingPort::recvFunctional()
2281 // calls recvAtomic() and throws away the latency; we can save a
2282 // little here by just not calculating the latency.
2283 memory
.recvFunctional(pkt
);
2290 DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt
)
2292 return memory
.recvAtomic(pkt
);
2296 DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt
)
2298 // pass it to the memory controller
2299 return memory
.recvTimingReq(pkt
);
2303 DRAMCtrlParams::create()
2305 return new DRAMCtrl(this);