2 * Copyright (c) 2010-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
45 #include "base/bitfield.hh"
46 #include "base/trace.hh"
47 #include "debug/DRAM.hh"
48 #include "debug/DRAMState.hh"
49 #include "debug/Drain.hh"
50 #include "mem/dram_ctrl.hh"
51 #include "sim/system.hh"
55 DRAMCtrl::DRAMCtrl(const DRAMCtrlParams
* p
) :
57 port(name() + ".port", *this),
58 retryRdReq(false), retryWrReq(false),
60 nextReqEvent(this), respondEvent(this), activateEvent(this),
61 prechargeEvent(this), refreshEvent(this), powerEvent(this),
63 deviceBusWidth(p
->device_bus_width
), burstLength(p
->burst_length
),
64 deviceRowBufferSize(p
->device_rowbuffer_size
),
65 devicesPerRank(p
->devices_per_rank
),
66 burstSize((devicesPerRank
* burstLength
* deviceBusWidth
) / 8),
67 rowBufferSize(devicesPerRank
* deviceRowBufferSize
),
68 columnsPerRowBuffer(rowBufferSize
/ burstSize
),
69 ranksPerChannel(p
->ranks_per_channel
),
70 banksPerRank(p
->banks_per_rank
), channels(p
->channels
), rowsPerBank(0),
71 readBufferSize(p
->read_buffer_size
),
72 writeBufferSize(p
->write_buffer_size
),
73 writeHighThreshold(writeBufferSize
* p
->write_high_thresh_perc
/ 100.0),
74 writeLowThreshold(writeBufferSize
* p
->write_low_thresh_perc
/ 100.0),
75 minWritesPerSwitch(p
->min_writes_per_switch
),
76 writesThisTime(0), readsThisTime(0),
77 tCK(p
->tCK
), tWTR(p
->tWTR
), tRTW(p
->tRTW
), tBURST(p
->tBURST
),
78 tRCD(p
->tRCD
), tCL(p
->tCL
), tRP(p
->tRP
), tRAS(p
->tRAS
), tWR(p
->tWR
),
79 tRTP(p
->tRTP
), tRFC(p
->tRFC
), tREFI(p
->tREFI
), tRRD(p
->tRRD
),
80 tXAW(p
->tXAW
), activationLimit(p
->activation_limit
),
81 memSchedPolicy(p
->mem_sched_policy
), addrMapping(p
->addr_mapping
),
82 pageMgmt(p
->page_policy
),
83 maxAccessesPerRow(p
->max_accesses_per_row
),
84 frontendLatency(p
->static_frontend_latency
),
85 backendLatency(p
->static_backend_latency
),
86 busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE
),
87 pwrStateTrans(PWR_IDLE
), pwrState(PWR_IDLE
), prevArrival(0),
88 nextReqTime(0), pwrStateTick(0), numBanksActive(0)
90 // create the bank states based on the dimensions of the ranks and
92 banks
.resize(ranksPerChannel
);
93 actTicks
.resize(ranksPerChannel
);
94 for (size_t c
= 0; c
< ranksPerChannel
; ++c
) {
95 banks
[c
].resize(banksPerRank
);
96 actTicks
[c
].resize(activationLimit
, 0);
99 // perform a basic check of the write thresholds
100 if (p
->write_low_thresh_perc
>= p
->write_high_thresh_perc
)
101 fatal("Write buffer low threshold %d must be smaller than the "
102 "high threshold %d\n", p
->write_low_thresh_perc
,
103 p
->write_high_thresh_perc
);
105 // determine the rows per bank by looking at the total capacity
106 uint64_t capacity
= ULL(1) << ceilLog2(AbstractMemory::size());
108 DPRINTF(DRAM
, "Memory capacity %lld (%lld) bytes\n", capacity
,
109 AbstractMemory::size());
111 DPRINTF(DRAM
, "Row buffer size %d bytes with %d columns per row buffer\n",
112 rowBufferSize
, columnsPerRowBuffer
);
114 rowsPerBank
= capacity
/ (rowBufferSize
* banksPerRank
* ranksPerChannel
);
116 if (range
.interleaved()) {
117 if (channels
!= range
.stripes())
118 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
119 name(), range
.stripes(), channels
);
121 if (addrMapping
== Enums::RoRaBaChCo
) {
122 if (rowBufferSize
!= range
.granularity()) {
123 fatal("Interleaving of %s doesn't match RoRaBaChCo "
124 "address map\n", name());
126 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
127 if (system()->cacheLineSize() != range
.granularity()) {
128 fatal("Interleaving of %s doesn't match RoRaBaCoCh "
129 "address map\n", name());
131 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
132 if (system()->cacheLineSize() != range
.granularity())
133 fatal("Interleaving of %s doesn't match RoCoRaBaCh "
134 "address map\n", name());
138 // some basic sanity checks
139 if (tREFI
<= tRP
|| tREFI
<= tRFC
) {
140 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
148 if (!port
.isConnected()) {
149 fatal("DRAMCtrl %s is unconnected!\n", name());
151 port
.sendRangeChange();
158 // update the start tick for the precharge accounting to the
160 pwrStateTick
= curTick();
162 // shift the bus busy time sufficiently far ahead that we never
163 // have to worry about negative values when computing the time for
164 // the next request, this will add an insignificant bubble at the
165 // start of simulation
166 busBusyUntil
= curTick() + tRP
+ tRCD
+ tCL
;
168 // kick off the refresh, and give ourselves enough time to
170 schedule(refreshEvent
, curTick() + tREFI
- tRP
);
174 DRAMCtrl::recvAtomic(PacketPtr pkt
)
176 DPRINTF(DRAM
, "recvAtomic: %s 0x%x\n", pkt
->cmdString(), pkt
->getAddr());
178 // do the actual memory access and turn the packet into a response
182 if (!pkt
->memInhibitAsserted() && pkt
->hasData()) {
183 // this value is not supposed to be accurate, just enough to
184 // keep things going, mimic a closed page
185 latency
= tRP
+ tRCD
+ tCL
;
191 DRAMCtrl::readQueueFull(unsigned int neededEntries
) const
193 DPRINTF(DRAM
, "Read queue limit %d, current size %d, entries needed %d\n",
194 readBufferSize
, readQueue
.size() + respQueue
.size(),
198 (readQueue
.size() + respQueue
.size() + neededEntries
) > readBufferSize
;
202 DRAMCtrl::writeQueueFull(unsigned int neededEntries
) const
204 DPRINTF(DRAM
, "Write queue limit %d, current size %d, entries needed %d\n",
205 writeBufferSize
, writeQueue
.size(), neededEntries
);
206 return (writeQueue
.size() + neededEntries
) > writeBufferSize
;
209 DRAMCtrl::DRAMPacket
*
210 DRAMCtrl::decodeAddr(PacketPtr pkt
, Addr dramPktAddr
, unsigned size
,
213 // decode the address based on the address mapping scheme, with
214 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
215 // channel, respectively
220 // truncate the address to the access granularity
221 Addr addr
= dramPktAddr
/ burstSize
;
223 // we have removed the lowest order address bits that denote the
224 // position within the column
225 if (addrMapping
== Enums::RoRaBaChCo
) {
226 // the lowest order bits denote the column to ensure that
227 // sequential cache lines occupy the same row
228 addr
= addr
/ columnsPerRowBuffer
;
230 // take out the channel part of the address
231 addr
= addr
/ channels
;
233 // after the channel bits, get the bank bits to interleave
235 bank
= addr
% banksPerRank
;
236 addr
= addr
/ banksPerRank
;
238 // after the bank, we get the rank bits which thus interleaves
240 rank
= addr
% ranksPerChannel
;
241 addr
= addr
/ ranksPerChannel
;
243 // lastly, get the row bits
244 row
= addr
% rowsPerBank
;
245 addr
= addr
/ rowsPerBank
;
246 } else if (addrMapping
== Enums::RoRaBaCoCh
) {
247 // take out the channel part of the address
248 addr
= addr
/ channels
;
251 addr
= addr
/ columnsPerRowBuffer
;
253 // after the column bits, we get the bank bits to interleave
255 bank
= addr
% banksPerRank
;
256 addr
= addr
/ banksPerRank
;
258 // after the bank, we get the rank bits which thus interleaves
260 rank
= addr
% ranksPerChannel
;
261 addr
= addr
/ ranksPerChannel
;
263 // lastly, get the row bits
264 row
= addr
% rowsPerBank
;
265 addr
= addr
/ rowsPerBank
;
266 } else if (addrMapping
== Enums::RoCoRaBaCh
) {
267 // optimise for closed page mode and utilise maximum
268 // parallelism of the DRAM (at the cost of power)
270 // take out the channel part of the address, not that this has
271 // to match with how accesses are interleaved between the
272 // controllers in the address mapping
273 addr
= addr
/ channels
;
275 // start with the bank bits, as this provides the maximum
276 // opportunity for parallelism between requests
277 bank
= addr
% banksPerRank
;
278 addr
= addr
/ banksPerRank
;
280 // next get the rank bits
281 rank
= addr
% ranksPerChannel
;
282 addr
= addr
/ ranksPerChannel
;
284 // next the column bits which we do not need to keep track of
285 // and simply skip past
286 addr
= addr
/ columnsPerRowBuffer
;
288 // lastly, get the row bits
289 row
= addr
% rowsPerBank
;
290 addr
= addr
/ rowsPerBank
;
292 panic("Unknown address mapping policy chosen!");
294 assert(rank
< ranksPerChannel
);
295 assert(bank
< banksPerRank
);
296 assert(row
< rowsPerBank
);
298 DPRINTF(DRAM
, "Address: %lld Rank %d Bank %d Row %d\n",
299 dramPktAddr
, rank
, bank
, row
);
301 // create the corresponding DRAM packet with the entry time and
302 // ready time set to the current tick, the latter will be updated
304 uint16_t bank_id
= banksPerRank
* rank
+ bank
;
305 return new DRAMPacket(pkt
, isRead
, rank
, bank
, row
, bank_id
, dramPktAddr
,
306 size
, banks
[rank
][bank
]);
310 DRAMCtrl::addToReadQueue(PacketPtr pkt
, unsigned int pktCount
)
312 // only add to the read queue here. whenever the request is
313 // eventually done, set the readyTime, and call schedule()
314 assert(!pkt
->isWrite());
316 assert(pktCount
!= 0);
318 // if the request size is larger than burst size, the pkt is split into
319 // multiple DRAM packets
320 // Note if the pkt starting address is not aligened to burst size, the
321 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
322 // are aligned to burst size boundaries. This is to ensure we accurately
323 // check read packets against packets in write queue.
324 Addr addr
= pkt
->getAddr();
325 unsigned pktsServicedByWrQ
= 0;
326 BurstHelper
* burst_helper
= NULL
;
327 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
328 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
329 pkt
->getAddr() + pkt
->getSize()) - addr
;
330 readPktSize
[ceilLog2(size
)]++;
333 // First check write buffer to see if the data is already at
335 bool foundInWrQ
= false;
336 for (auto i
= writeQueue
.begin(); i
!= writeQueue
.end(); ++i
) {
337 // check if the read is subsumed in the write entry we are
339 if ((*i
)->addr
<= addr
&&
340 (addr
+ size
) <= ((*i
)->addr
+ (*i
)->size
)) {
344 DPRINTF(DRAM
, "Read to addr %lld with size %d serviced by "
345 "write queue\n", addr
, size
);
346 bytesReadWrQ
+= burstSize
;
351 // If not found in the write q, make a DRAM packet and
352 // push it onto the read queue
355 // Make the burst helper for split packets
356 if (pktCount
> 1 && burst_helper
== NULL
) {
357 DPRINTF(DRAM
, "Read to addr %lld translates to %d "
358 "dram requests\n", pkt
->getAddr(), pktCount
);
359 burst_helper
= new BurstHelper(pktCount
);
362 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, true);
363 dram_pkt
->burstHelper
= burst_helper
;
365 assert(!readQueueFull(1));
366 rdQLenPdf
[readQueue
.size() + respQueue
.size()]++;
368 DPRINTF(DRAM
, "Adding to read queue\n");
370 readQueue
.push_back(dram_pkt
);
373 avgRdQLen
= readQueue
.size() + respQueue
.size();
376 // Starting address of next dram pkt (aligend to burstSize boundary)
377 addr
= (addr
| (burstSize
- 1)) + 1;
380 // If all packets are serviced by write queue, we send the repsonse back
381 if (pktsServicedByWrQ
== pktCount
) {
382 accessAndRespond(pkt
, frontendLatency
);
386 // Update how many split packets are serviced by write queue
387 if (burst_helper
!= NULL
)
388 burst_helper
->burstsServiced
= pktsServicedByWrQ
;
390 // If we are not already scheduled to get a request out of the
392 if (!nextReqEvent
.scheduled()) {
393 DPRINTF(DRAM
, "Request scheduled immediately\n");
394 schedule(nextReqEvent
, curTick());
399 DRAMCtrl::addToWriteQueue(PacketPtr pkt
, unsigned int pktCount
)
401 // only add to the write queue here. whenever the request is
402 // eventually done, set the readyTime, and call schedule()
403 assert(pkt
->isWrite());
405 // if the request size is larger than burst size, the pkt is split into
406 // multiple DRAM packets
407 Addr addr
= pkt
->getAddr();
408 for (int cnt
= 0; cnt
< pktCount
; ++cnt
) {
409 unsigned size
= std::min((addr
| (burstSize
- 1)) + 1,
410 pkt
->getAddr() + pkt
->getSize()) - addr
;
411 writePktSize
[ceilLog2(size
)]++;
414 // see if we can merge with an existing item in the write
415 // queue and keep track of whether we have merged or not so we
416 // can stop at that point and also avoid enqueueing a new
419 auto w
= writeQueue
.begin();
421 while(!merged
&& w
!= writeQueue
.end()) {
422 // either of the two could be first, if they are the same
423 // it does not matter which way we go
424 if ((*w
)->addr
>= addr
) {
425 // the existing one starts after the new one, figure
426 // out where the new one ends with respect to the
428 if ((addr
+ size
) >= ((*w
)->addr
+ (*w
)->size
)) {
429 // check if the existing one is completely
430 // subsumed in the new one
431 DPRINTF(DRAM
, "Merging write covering existing burst\n");
433 // update both the address and the size
436 } else if ((addr
+ size
) >= (*w
)->addr
&&
437 ((*w
)->addr
+ (*w
)->size
- addr
) <= burstSize
) {
438 // the new one is just before or partially
439 // overlapping with the existing one, and together
440 // they fit within a burst
441 DPRINTF(DRAM
, "Merging write before existing burst\n");
443 // the existing queue item needs to be adjusted with
444 // respect to both address and size
445 (*w
)->size
= (*w
)->addr
+ (*w
)->size
- addr
;
449 // the new one starts after the current one, figure
450 // out where the existing one ends with respect to the
452 if (((*w
)->addr
+ (*w
)->size
) >= (addr
+ size
)) {
453 // check if the new one is completely subsumed in the
455 DPRINTF(DRAM
, "Merging write into existing burst\n");
457 // no adjustments necessary
458 } else if (((*w
)->addr
+ (*w
)->size
) >= addr
&&
459 (addr
+ size
- (*w
)->addr
) <= burstSize
) {
460 // the existing one is just before or partially
461 // overlapping with the new one, and together
462 // they fit within a burst
463 DPRINTF(DRAM
, "Merging write after existing burst\n");
465 // the address is right, and only the size has
467 (*w
)->size
= addr
+ size
- (*w
)->addr
;
473 // if the item was not merged we need to create a new write
476 DRAMPacket
* dram_pkt
= decodeAddr(pkt
, addr
, size
, false);
478 assert(writeQueue
.size() < writeBufferSize
);
479 wrQLenPdf
[writeQueue
.size()]++;
481 DPRINTF(DRAM
, "Adding to write queue\n");
483 writeQueue
.push_back(dram_pkt
);
486 avgWrQLen
= writeQueue
.size();
488 // keep track of the fact that this burst effectively
489 // disappeared as it was merged with an existing one
493 // Starting address of next dram pkt (aligend to burstSize boundary)
494 addr
= (addr
| (burstSize
- 1)) + 1;
497 // we do not wait for the writes to be send to the actual memory,
498 // but instead take responsibility for the consistency here and
499 // snoop the write queue for any upcoming reads
500 // @todo, if a pkt size is larger than burst size, we might need a
501 // different front end latency
502 accessAndRespond(pkt
, frontendLatency
);
504 // If we are not already scheduled to get a request out of the
506 if (!nextReqEvent
.scheduled()) {
507 DPRINTF(DRAM
, "Request scheduled immediately\n");
508 schedule(nextReqEvent
, curTick());
513 DRAMCtrl::printQs() const {
514 DPRINTF(DRAM
, "===READ QUEUE===\n\n");
515 for (auto i
= readQueue
.begin() ; i
!= readQueue
.end() ; ++i
) {
516 DPRINTF(DRAM
, "Read %lu\n", (*i
)->addr
);
518 DPRINTF(DRAM
, "\n===RESP QUEUE===\n\n");
519 for (auto i
= respQueue
.begin() ; i
!= respQueue
.end() ; ++i
) {
520 DPRINTF(DRAM
, "Response %lu\n", (*i
)->addr
);
522 DPRINTF(DRAM
, "\n===WRITE QUEUE===\n\n");
523 for (auto i
= writeQueue
.begin() ; i
!= writeQueue
.end() ; ++i
) {
524 DPRINTF(DRAM
, "Write %lu\n", (*i
)->addr
);
529 DRAMCtrl::recvTimingReq(PacketPtr pkt
)
531 /// @todo temporary hack to deal with memory corruption issues until
532 /// 4-phase transactions are complete
533 for (int x
= 0; x
< pendingDelete
.size(); x
++)
534 delete pendingDelete
[x
];
535 pendingDelete
.clear();
537 // This is where we enter from the outside world
538 DPRINTF(DRAM
, "recvTimingReq: request %s addr %lld size %d\n",
539 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
541 // simply drop inhibited packets for now
542 if (pkt
->memInhibitAsserted()) {
543 DPRINTF(DRAM
, "Inhibited packet -- Dropping it now\n");
544 pendingDelete
.push_back(pkt
);
548 // Calc avg gap between requests
549 if (prevArrival
!= 0) {
550 totGap
+= curTick() - prevArrival
;
552 prevArrival
= curTick();
555 // Find out how many dram packets a pkt translates to
556 // If the burst size is equal or larger than the pkt size, then a pkt
557 // translates to only one dram packet. Otherwise, a pkt translates to
558 // multiple dram packets
559 unsigned size
= pkt
->getSize();
560 unsigned offset
= pkt
->getAddr() & (burstSize
- 1);
561 unsigned int dram_pkt_count
= divCeil(offset
+ size
, burstSize
);
563 // check local buffers and do not accept if full
566 if (readQueueFull(dram_pkt_count
)) {
567 DPRINTF(DRAM
, "Read queue full, not accepting\n");
568 // remember that we have to retry this port
573 addToReadQueue(pkt
, dram_pkt_count
);
575 bytesReadSys
+= size
;
577 } else if (pkt
->isWrite()) {
579 if (writeQueueFull(dram_pkt_count
)) {
580 DPRINTF(DRAM
, "Write queue full, not accepting\n");
581 // remember that we have to retry this port
586 addToWriteQueue(pkt
, dram_pkt_count
);
588 bytesWrittenSys
+= size
;
591 DPRINTF(DRAM
,"Neither read nor write, ignore timing\n");
592 neitherReadNorWrite
++;
593 accessAndRespond(pkt
, 1);
600 DRAMCtrl::processRespondEvent()
603 "processRespondEvent(): Some req has reached its readyTime\n");
605 DRAMPacket
* dram_pkt
= respQueue
.front();
607 if (dram_pkt
->burstHelper
) {
608 // it is a split packet
609 dram_pkt
->burstHelper
->burstsServiced
++;
610 if (dram_pkt
->burstHelper
->burstsServiced
==
611 dram_pkt
->burstHelper
->burstCount
) {
612 // we have now serviced all children packets of a system packet
613 // so we can now respond to the requester
614 // @todo we probably want to have a different front end and back
615 // end latency for split packets
616 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
617 delete dram_pkt
->burstHelper
;
618 dram_pkt
->burstHelper
= NULL
;
621 // it is not a split packet
622 accessAndRespond(dram_pkt
->pkt
, frontendLatency
+ backendLatency
);
625 delete respQueue
.front();
626 respQueue
.pop_front();
628 if (!respQueue
.empty()) {
629 assert(respQueue
.front()->readyTime
>= curTick());
630 assert(!respondEvent
.scheduled());
631 schedule(respondEvent
, respQueue
.front()->readyTime
);
633 // if there is nothing left in any queue, signal a drain
634 if (writeQueue
.empty() && readQueue
.empty() &&
636 drainManager
->signalDrainDone();
641 // We have made a location in the queue available at this point,
642 // so if there is a read that was forced to wait, retry now
650 DRAMCtrl::chooseNext(std::deque
<DRAMPacket
*>& queue
)
652 // This method does the arbitration between requests. The chosen
653 // packet is simply moved to the head of the queue. The other
654 // methods know that this is the place to look. For example, with
655 // FCFS, this method does nothing
656 assert(!queue
.empty());
658 if (queue
.size() == 1) {
659 DPRINTF(DRAM
, "Single request, nothing to do\n");
663 if (memSchedPolicy
== Enums::fcfs
) {
664 // Do nothing, since the correct request is already head
665 } else if (memSchedPolicy
== Enums::frfcfs
) {
668 panic("No scheduling policy chosen\n");
672 DRAMCtrl::reorderQueue(std::deque
<DRAMPacket
*>& queue
)
674 // Only determine this when needed
675 uint64_t earliest_banks
= 0;
677 // Search for row hits first, if no row hit is found then schedule the
678 // packet to one of the earliest banks available
679 bool found_earliest_pkt
= false;
680 auto selected_pkt_it
= queue
.begin();
682 for (auto i
= queue
.begin(); i
!= queue
.end() ; ++i
) {
683 DRAMPacket
* dram_pkt
= *i
;
684 const Bank
& bank
= dram_pkt
->bankRef
;
685 // Check if it is a row hit
686 if (bank
.openRow
== dram_pkt
->row
) {
687 // FCFS within the hits
688 DPRINTF(DRAM
, "Row buffer hit\n");
691 } else if (!found_earliest_pkt
) {
692 // No row hit, go for first ready
693 if (earliest_banks
== 0)
694 earliest_banks
= minBankActAt(queue
);
696 // simplistic approximation of when the bank can issue an
697 // activate, this is calculated in minBankActAt and could
699 Tick act_at
= bank
.openRow
== Bank::NO_ROW
?
701 std::max(bank
.preAllowedAt
, curTick()) + tRP
;
703 // Bank is ready or is the first available bank
704 if (act_at
<= curTick() ||
705 bits(earliest_banks
, dram_pkt
->bankId
, dram_pkt
->bankId
)) {
706 // Remember the packet to be scheduled to one of the earliest
707 // banks available, FCFS amongst the earliest banks
709 found_earliest_pkt
= true;
714 DRAMPacket
* selected_pkt
= *selected_pkt_it
;
715 queue
.erase(selected_pkt_it
);
716 queue
.push_front(selected_pkt
);
720 DRAMCtrl::accessAndRespond(PacketPtr pkt
, Tick static_latency
)
722 DPRINTF(DRAM
, "Responding to Address %lld.. ",pkt
->getAddr());
724 bool needsResponse
= pkt
->needsResponse();
725 // do the actual memory access which also turns the packet into a
729 // turn packet around to go back to requester if response expected
731 // access already turned the packet into a response
732 assert(pkt
->isResponse());
734 // @todo someone should pay for this
735 pkt
->busFirstWordDelay
= pkt
->busLastWordDelay
= 0;
737 // queue the packet in the response queue to be sent out after
738 // the static latency has passed
739 port
.schedTimingResp(pkt
, curTick() + static_latency
);
741 // @todo the packet is going to be deleted, and the DRAMPacket
742 // is still having a pointer to it
743 pendingDelete
.push_back(pkt
);
746 DPRINTF(DRAM
, "Done\n");
752 DRAMCtrl::activateBank(Tick act_tick
, uint8_t rank
, uint8_t bank
,
753 uint16_t row
, Bank
& bank_ref
)
755 assert(0 <= rank
&& rank
< ranksPerChannel
);
756 assert(actTicks
[rank
].size() == activationLimit
);
758 DPRINTF(DRAM
, "Activate at tick %d\n", act_tick
);
760 // update the open row
761 assert(bank_ref
.openRow
== Bank::NO_ROW
);
762 bank_ref
.openRow
= row
;
764 // start counting anew, this covers both the case when we
765 // auto-precharged, and when this access is forced to
767 bank_ref
.bytesAccessed
= 0;
768 bank_ref
.rowAccesses
= 0;
771 assert(numBanksActive
<= banksPerRank
* ranksPerChannel
);
773 DPRINTF(DRAM
, "Activate bank at tick %lld, now got %d active\n",
774 act_tick
, numBanksActive
);
776 // The next access has to respect tRAS for this bank
777 bank_ref
.preAllowedAt
= act_tick
+ tRAS
;
779 // Respect the row-to-column command delay
780 bank_ref
.colAllowedAt
= act_tick
+ tRCD
;
782 // start by enforcing tRRD
783 for(int i
= 0; i
< banksPerRank
; i
++) {
784 // next activate to any bank in this rank must not happen
786 banks
[rank
][i
].actAllowedAt
= std::max(act_tick
+ tRRD
,
787 banks
[rank
][i
].actAllowedAt
);
790 // next, we deal with tXAW, if the activation limit is disabled
792 if (actTicks
[rank
].empty())
796 if (actTicks
[rank
].back() && (act_tick
- actTicks
[rank
].back()) < tXAW
) {
797 panic("Got %d activates in window %d (%llu - %llu) which is smaller "
798 "than %llu\n", activationLimit
, act_tick
- actTicks
[rank
].back(),
799 act_tick
, actTicks
[rank
].back(), tXAW
);
802 // shift the times used for the book keeping, the last element
803 // (highest index) is the oldest one and hence the lowest value
804 actTicks
[rank
].pop_back();
806 // record an new activation (in the future)
807 actTicks
[rank
].push_front(act_tick
);
809 // cannot activate more than X times in time window tXAW, push the
810 // next one (the X + 1'st activate) to be tXAW away from the
811 // oldest in our window of X
812 if (actTicks
[rank
].back() && (act_tick
- actTicks
[rank
].back()) < tXAW
) {
813 DPRINTF(DRAM
, "Enforcing tXAW with X = %d, next activate no earlier "
814 "than %llu\n", activationLimit
, actTicks
[rank
].back() + tXAW
);
815 for(int j
= 0; j
< banksPerRank
; j
++)
816 // next activate must not happen before end of window
817 banks
[rank
][j
].actAllowedAt
=
818 std::max(actTicks
[rank
].back() + tXAW
,
819 banks
[rank
][j
].actAllowedAt
);
822 // at the point when this activate takes place, make sure we
823 // transition to the active power state
824 if (!activateEvent
.scheduled())
825 schedule(activateEvent
, act_tick
);
826 else if (activateEvent
.when() > act_tick
)
827 // move it sooner in time
828 reschedule(activateEvent
, act_tick
);
832 DRAMCtrl::processActivateEvent()
834 // we should transition to the active state as soon as any bank is active
835 if (pwrState
!= PWR_ACT
)
836 // note that at this point numBanksActive could be back at
837 // zero again due to a precharge scheduled in the future
838 schedulePowerEvent(PWR_ACT
, curTick());
842 DRAMCtrl::prechargeBank(Bank
& bank
, Tick pre_at
)
844 // make sure the bank has an open row
845 assert(bank
.openRow
!= Bank::NO_ROW
);
847 // sample the bytes per activate here since we are closing
849 bytesPerActivate
.sample(bank
.bytesAccessed
);
851 bank
.openRow
= Bank::NO_ROW
;
853 // no precharge allowed before this one
854 bank
.preAllowedAt
= pre_at
;
856 Tick pre_done_at
= pre_at
+ tRP
;
858 bank
.actAllowedAt
= std::max(bank
.actAllowedAt
, pre_done_at
);
860 assert(numBanksActive
!= 0);
863 DPRINTF(DRAM
, "Precharging bank at tick %lld, now got %d active\n",
864 pre_at
, numBanksActive
);
866 // if we look at the current number of active banks we might be
867 // tempted to think the DRAM is now idle, however this can be
868 // undone by an activate that is scheduled to happen before we
869 // would have reached the idle state, so schedule an event and
870 // rather check once we actually make it to the point in time when
871 // the (last) precharge takes place
872 if (!prechargeEvent
.scheduled())
873 schedule(prechargeEvent
, pre_done_at
);
874 else if (prechargeEvent
.when() < pre_done_at
)
875 reschedule(prechargeEvent
, pre_done_at
);
879 DRAMCtrl::processPrechargeEvent()
881 // if we reached zero, then special conditions apply as we track
882 // if all banks are precharged for the power models
883 if (numBanksActive
== 0) {
884 // we should transition to the idle state when the last bank
886 schedulePowerEvent(PWR_IDLE
, curTick());
891 DRAMCtrl::doDRAMAccess(DRAMPacket
* dram_pkt
)
893 DPRINTF(DRAM
, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
894 dram_pkt
->addr
, dram_pkt
->rank
, dram_pkt
->bank
, dram_pkt
->row
);
897 Bank
& bank
= dram_pkt
->bankRef
;
899 // for the state we need to track if it is a row hit or not
902 // respect any constraints on the command (e.g. tRCD or tCCD)
903 Tick cmd_at
= std::max(bank
.colAllowedAt
, curTick());
905 // Determine the access latency and update the bank state
906 if (bank
.openRow
== dram_pkt
->row
) {
911 // If there is a page open, precharge it.
912 if (bank
.openRow
!= Bank::NO_ROW
) {
913 prechargeBank(bank
, std::max(bank
.preAllowedAt
, curTick()));
916 // next we need to account for the delay in activating the
918 Tick act_tick
= std::max(bank
.actAllowedAt
, curTick());
920 // Record the activation and deal with all the global timing
921 // constraints caused be a new activation (tRRD and tXAW)
922 activateBank(act_tick
, dram_pkt
->rank
, dram_pkt
->bank
,
923 dram_pkt
->row
, bank
);
925 // issue the command as early as possible
926 cmd_at
= bank
.colAllowedAt
;
929 // we need to wait until the bus is available before we can issue
931 cmd_at
= std::max(cmd_at
, busBusyUntil
- tCL
);
933 // update the packet ready time
934 dram_pkt
->readyTime
= cmd_at
+ tCL
+ tBURST
;
936 // only one burst can use the bus at any one point in time
937 assert(dram_pkt
->readyTime
- busBusyUntil
>= tBURST
);
939 // not strictly necessary, but update the time for the next
940 // read/write (add a max with tCCD here)
941 bank
.colAllowedAt
= cmd_at
+ tBURST
;
943 // If this is a write, we also need to respect the write recovery
944 // time before a precharge, in the case of a read, respect the
945 // read to precharge constraint
946 bank
.preAllowedAt
= std::max(bank
.preAllowedAt
,
947 dram_pkt
->isRead
? cmd_at
+ tRTP
:
948 dram_pkt
->readyTime
+ tWR
);
950 // increment the bytes accessed and the accesses per row
951 bank
.bytesAccessed
+= burstSize
;
954 // if we reached the max, then issue with an auto-precharge
955 bool auto_precharge
= pageMgmt
== Enums::close
||
956 bank
.rowAccesses
== maxAccessesPerRow
;
958 // if we did not hit the limit, we might still want to
960 if (!auto_precharge
&&
961 (pageMgmt
== Enums::open_adaptive
||
962 pageMgmt
== Enums::close_adaptive
)) {
963 // a twist on the open and close page policies:
964 // 1) open_adaptive page policy does not blindly keep the
965 // page open, but close it if there are no row hits, and there
966 // are bank conflicts in the queue
967 // 2) close_adaptive page policy does not blindly close the
968 // page, but closes it only if there are no row hits in the queue.
969 // In this case, only force an auto precharge when there
970 // are no same page hits in the queue
971 bool got_more_hits
= false;
972 bool got_bank_conflict
= false;
974 // either look at the read queue or write queue
975 const deque
<DRAMPacket
*>& queue
= dram_pkt
->isRead
? readQueue
:
977 auto p
= queue
.begin();
978 // make sure we are not considering the packet that we are
979 // currently dealing with (which is the head of the queue)
982 // keep on looking until we have found required condition or
984 while (!(got_more_hits
&&
985 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
)) &&
987 bool same_rank_bank
= (dram_pkt
->rank
== (*p
)->rank
) &&
988 (dram_pkt
->bank
== (*p
)->bank
);
989 bool same_row
= dram_pkt
->row
== (*p
)->row
;
990 got_more_hits
|= same_rank_bank
&& same_row
;
991 got_bank_conflict
|= same_rank_bank
&& !same_row
;
995 // auto pre-charge when either
996 // 1) open_adaptive policy, we have not got any more hits, and
997 // have a bank conflict
998 // 2) close_adaptive policy and we have not got any more hits
999 auto_precharge
= !got_more_hits
&&
1000 (got_bank_conflict
|| pageMgmt
== Enums::close_adaptive
);
1003 // if this access should use auto-precharge, then we are
1005 if (auto_precharge
) {
1006 prechargeBank(bank
, std::max(curTick(), bank
.preAllowedAt
));
1008 DPRINTF(DRAM
, "Auto-precharged bank: %d\n", dram_pkt
->bankId
);
1012 busBusyUntil
= dram_pkt
->readyTime
;
1014 DPRINTF(DRAM
, "Access to %lld, ready at %lld bus busy until %lld.\n",
1015 dram_pkt
->addr
, dram_pkt
->readyTime
, busBusyUntil
);
1017 // Update the minimum timing between the requests, this is a
1018 // conservative estimate of when we have to schedule the next
1019 // request to not introduce any unecessary bubbles. In most cases
1020 // we will wake up sooner than we have to.
1021 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1023 // Update the stats and schedule the next request
1024 if (dram_pkt
->isRead
) {
1028 bytesReadDRAM
+= burstSize
;
1029 perBankRdBursts
[dram_pkt
->bankId
]++;
1031 // Update latency stats
1032 totMemAccLat
+= dram_pkt
->readyTime
- dram_pkt
->entryTime
;
1033 totBusLat
+= tBURST
;
1034 totQLat
+= cmd_at
- dram_pkt
->entryTime
;
1039 bytesWritten
+= burstSize
;
1040 perBankWrBursts
[dram_pkt
->bankId
]++;
1045 DRAMCtrl::processNextReqEvent()
1047 if (busState
== READ_TO_WRITE
) {
1048 DPRINTF(DRAM
, "Switching to writes after %d reads with %d reads "
1049 "waiting\n", readsThisTime
, readQueue
.size());
1051 // sample and reset the read-related stats as we are now
1052 // transitioning to writes, and all reads are done
1053 rdPerTurnAround
.sample(readsThisTime
);
1056 // now proceed to do the actual writes
1058 } else if (busState
== WRITE_TO_READ
) {
1059 DPRINTF(DRAM
, "Switching to reads after %d writes with %d writes "
1060 "waiting\n", writesThisTime
, writeQueue
.size());
1062 wrPerTurnAround
.sample(writesThisTime
);
1068 if (refreshState
!= REF_IDLE
) {
1069 // if a refresh waiting for this event loop to finish, then hand
1070 // over now, and do not schedule a new nextReqEvent
1071 if (refreshState
== REF_DRAIN
) {
1072 DPRINTF(DRAM
, "Refresh drain done, now precharging\n");
1074 refreshState
= REF_PRE
;
1076 // hand control back to the refresh event loop
1077 schedule(refreshEvent
, curTick());
1080 // let the refresh finish before issuing any further requests
1084 // when we get here it is either a read or a write
1085 if (busState
== READ
) {
1087 // track if we should switch or not
1088 bool switch_to_writes
= false;
1090 if (readQueue
.empty()) {
1091 // In the case there is no read request to go next,
1092 // trigger writes if we have passed the low threshold (or
1093 // if we are draining)
1094 if (!writeQueue
.empty() &&
1095 (drainManager
|| writeQueue
.size() > writeLowThreshold
)) {
1097 switch_to_writes
= true;
1099 // check if we are drained
1100 if (respQueue
.empty () && drainManager
) {
1101 drainManager
->signalDrainDone();
1102 drainManager
= NULL
;
1105 // nothing to do, not even any point in scheduling an
1106 // event for the next request
1110 // Figure out which read request goes next, and move it to the
1111 // front of the read queue
1112 chooseNext(readQueue
);
1114 DRAMPacket
* dram_pkt
= readQueue
.front();
1116 doDRAMAccess(dram_pkt
);
1118 // At this point we're done dealing with the request
1119 readQueue
.pop_front();
1122 assert(dram_pkt
->size
<= burstSize
);
1123 assert(dram_pkt
->readyTime
>= curTick());
1125 // Insert into response queue. It will be sent back to the
1126 // requestor at its readyTime
1127 if (respQueue
.empty()) {
1128 assert(!respondEvent
.scheduled());
1129 schedule(respondEvent
, dram_pkt
->readyTime
);
1131 assert(respQueue
.back()->readyTime
<= dram_pkt
->readyTime
);
1132 assert(respondEvent
.scheduled());
1135 respQueue
.push_back(dram_pkt
);
1137 // we have so many writes that we have to transition
1138 if (writeQueue
.size() > writeHighThreshold
) {
1139 switch_to_writes
= true;
1143 // switching to writes, either because the read queue is empty
1144 // and the writes have passed the low threshold (or we are
1145 // draining), or because the writes hit the hight threshold
1146 if (switch_to_writes
) {
1147 // transition to writing
1148 busState
= READ_TO_WRITE
;
1150 // add a bubble to the data bus, as defined by the
1152 busBusyUntil
+= tRTW
;
1154 // update the minimum timing between the requests,
1155 // this shifts us back in time far enough to do any
1157 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1160 chooseNext(writeQueue
);
1161 DRAMPacket
* dram_pkt
= writeQueue
.front();
1163 assert(dram_pkt
->size
<= burstSize
);
1164 doDRAMAccess(dram_pkt
);
1166 writeQueue
.pop_front();
1169 // If we emptied the write queue, or got sufficiently below the
1170 // threshold (using the minWritesPerSwitch as the hysteresis) and
1171 // are not draining, or we have reads waiting and have done enough
1172 // writes, then switch to reads.
1173 if (writeQueue
.empty() ||
1174 (writeQueue
.size() + minWritesPerSwitch
< writeLowThreshold
&&
1176 (!readQueue
.empty() && writesThisTime
>= minWritesPerSwitch
)) {
1177 // turn the bus back around for reads again
1178 busState
= WRITE_TO_READ
;
1180 // note that the we switch back to reads also in the idle
1181 // case, which eventually will check for any draining and
1182 // also pause any further scheduling if there is really
1185 // here we get a bit creative and shift the bus busy time not
1186 // just the tWTR, but also a CAS latency to capture the fact
1187 // that we are allowed to prepare a new bank, but not issue a
1188 // read command until after tWTR, in essence we capture a
1189 // bubble on the data bus that is tWTR + tCL
1190 busBusyUntil
+= tWTR
+ tCL
;
1192 // update the minimum timing between the requests, this shifts
1193 // us back in time far enough to do any bank preparation
1194 nextReqTime
= busBusyUntil
- (tRP
+ tRCD
+ tCL
);
1198 schedule(nextReqEvent
, std::max(nextReqTime
, curTick()));
1200 // If there is space available and we have writes waiting then let
1201 // them retry. This is done here to ensure that the retry does not
1202 // cause a nextReqEvent to be scheduled before we do so as part of
1203 // the next request processing
1204 if (retryWrReq
&& writeQueue
.size() < writeBufferSize
) {
1211 DRAMCtrl::minBankActAt(const deque
<DRAMPacket
*>& queue
) const
1213 uint64_t bank_mask
= 0;
1214 Tick min_act_at
= MaxTick
;
1216 // deterimne if we have queued transactions targetting a
1218 vector
<bool> got_waiting(ranksPerChannel
* banksPerRank
, false);
1219 for (auto p
= queue
.begin(); p
!= queue
.end(); ++p
) {
1220 got_waiting
[(*p
)->bankId
] = true;
1223 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1224 for (int j
= 0; j
< banksPerRank
; j
++) {
1225 uint8_t bank_id
= i
* banksPerRank
+ j
;
1227 // if we have waiting requests for the bank, and it is
1228 // amongst the first available, update the mask
1229 if (got_waiting
[bank_id
]) {
1230 // simplistic approximation of when the bank can issue
1231 // an activate, ignoring any rank-to-rank switching
1233 Tick act_at
= banks
[i
][j
].openRow
== Bank::NO_ROW
?
1234 banks
[i
][j
].actAllowedAt
:
1235 std::max(banks
[i
][j
].preAllowedAt
, curTick()) + tRP
;
1237 if (act_at
<= min_act_at
) {
1238 // reset bank mask if new minimum is found
1239 if (act_at
< min_act_at
)
1241 // set the bit corresponding to the available bank
1242 replaceBits(bank_mask
, bank_id
, bank_id
, 1);
1243 min_act_at
= act_at
;
1253 DRAMCtrl::processRefreshEvent()
1255 // when first preparing the refresh, remember when it was due
1256 if (refreshState
== REF_IDLE
) {
1257 // remember when the refresh is due
1258 refreshDueAt
= curTick();
1261 refreshState
= REF_DRAIN
;
1263 DPRINTF(DRAM
, "Refresh due\n");
1266 // let any scheduled read or write go ahead, after which it will
1267 // hand control back to this event loop
1268 if (refreshState
== REF_DRAIN
) {
1269 if (nextReqEvent
.scheduled()) {
1270 // hand control over to the request loop until it is
1272 DPRINTF(DRAM
, "Refresh awaiting draining\n");
1276 refreshState
= REF_PRE
;
1280 // at this point, ensure that all banks are precharged
1281 if (refreshState
== REF_PRE
) {
1282 // precharge any active bank if we are not already in the idle
1284 if (pwrState
!= PWR_IDLE
) {
1285 // at the moment, we use a precharge all even if there is
1286 // only a single bank open
1287 DPRINTF(DRAM
, "Precharging all\n");
1289 // first determine when we can precharge
1290 Tick pre_at
= curTick();
1291 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1292 for (int j
= 0; j
< banksPerRank
; j
++) {
1293 // respect both causality and any existing bank
1294 // constraints, some banks could already have a
1295 // (auto) precharge scheduled
1296 pre_at
= std::max(banks
[i
][j
].preAllowedAt
, pre_at
);
1300 // make sure all banks are precharged, and for those that
1301 // already are, update their availability
1302 Tick act_allowed_at
= pre_at
+ tRP
;
1304 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1305 for (int j
= 0; j
< banksPerRank
; j
++) {
1306 if (banks
[i
][j
].openRow
!= Bank::NO_ROW
) {
1307 prechargeBank(banks
[i
][j
], pre_at
);
1309 banks
[i
][j
].actAllowedAt
=
1310 std::max(banks
[i
][j
].actAllowedAt
, act_allowed_at
);
1311 banks
[i
][j
].preAllowedAt
=
1312 std::max(banks
[i
][j
].preAllowedAt
, pre_at
);
1317 DPRINTF(DRAM
, "All banks already precharged, starting refresh\n");
1319 // go ahead and kick the power state machine into gear if
1320 // we are already idle
1321 schedulePowerEvent(PWR_REF
, curTick());
1324 refreshState
= REF_RUN
;
1325 assert(numBanksActive
== 0);
1327 // wait for all banks to be precharged, at which point the
1328 // power state machine will transition to the idle state, and
1329 // automatically move to a refresh, at that point it will also
1330 // call this method to get the refresh event loop going again
1334 // last but not least we perform the actual refresh
1335 if (refreshState
== REF_RUN
) {
1336 // should never get here with any banks active
1337 assert(numBanksActive
== 0);
1338 assert(pwrState
== PWR_REF
);
1340 Tick ref_done_at
= curTick() + tRFC
;
1342 for (int i
= 0; i
< ranksPerChannel
; i
++) {
1343 for (int j
= 0; j
< banksPerRank
; j
++) {
1344 banks
[i
][j
].actAllowedAt
= ref_done_at
;
1348 // make sure we did not wait so long that we cannot make up
1350 if (refreshDueAt
+ tREFI
< ref_done_at
) {
1351 fatal("Refresh was delayed so long we cannot catch up\n");
1354 // compensate for the delay in actually performing the refresh
1355 // when scheduling the next one
1356 schedule(refreshEvent
, refreshDueAt
+ tREFI
- tRP
);
1358 assert(!powerEvent
.scheduled());
1360 // move to the idle power state once the refresh is done, this
1361 // will also move the refresh state machine to the refresh
1363 schedulePowerEvent(PWR_IDLE
, ref_done_at
);
1365 DPRINTF(DRAMState
, "Refresh done at %llu and next refresh at %llu\n",
1366 ref_done_at
, refreshDueAt
+ tREFI
);
1371 DRAMCtrl::schedulePowerEvent(PowerState pwr_state
, Tick tick
)
1373 // respect causality
1374 assert(tick
>= curTick());
1376 if (!powerEvent
.scheduled()) {
1377 DPRINTF(DRAMState
, "Scheduling power event at %llu to state %d\n",
1380 // insert the new transition
1381 pwrStateTrans
= pwr_state
;
1383 schedule(powerEvent
, tick
);
1385 panic("Scheduled power event at %llu to state %d, "
1386 "with scheduled event at %llu to %d\n", tick
, pwr_state
,
1387 powerEvent
.when(), pwrStateTrans
);
1392 DRAMCtrl::processPowerEvent()
1394 // remember where we were, and for how long
1395 Tick duration
= curTick() - pwrStateTick
;
1396 PowerState prev_state
= pwrState
;
1398 // update the accounting
1399 pwrStateTime
[prev_state
] += duration
;
1401 pwrState
= pwrStateTrans
;
1402 pwrStateTick
= curTick();
1404 if (pwrState
== PWR_IDLE
) {
1405 DPRINTF(DRAMState
, "All banks precharged\n");
1407 // if we were refreshing, make sure we start scheduling requests again
1408 if (prev_state
== PWR_REF
) {
1409 DPRINTF(DRAMState
, "Was refreshing for %llu ticks\n", duration
);
1410 assert(pwrState
== PWR_IDLE
);
1412 // kick things into action again
1413 refreshState
= REF_IDLE
;
1414 assert(!nextReqEvent
.scheduled());
1415 schedule(nextReqEvent
, curTick());
1417 assert(prev_state
== PWR_ACT
);
1419 // if we have a pending refresh, and are now moving to
1420 // the idle state, direclty transition to a refresh
1421 if (refreshState
== REF_RUN
) {
1422 // there should be nothing waiting at this point
1423 assert(!powerEvent
.scheduled());
1425 // update the state in zero time and proceed below
1431 // we transition to the refresh state, let the refresh state
1432 // machine know of this state update and let it deal with the
1433 // scheduling of the next power state transition as well as the
1434 // following refresh
1435 if (pwrState
== PWR_REF
) {
1436 DPRINTF(DRAMState
, "Refreshing\n");
1437 // kick the refresh event loop into action again, and that
1438 // in turn will schedule a transition to the idle power
1439 // state once the refresh is done
1440 assert(refreshState
== REF_RUN
);
1441 processRefreshEvent();
1446 DRAMCtrl::regStats()
1448 using namespace Stats
;
1450 AbstractMemory::regStats();
1453 .name(name() + ".readReqs")
1454 .desc("Number of read requests accepted");
1457 .name(name() + ".writeReqs")
1458 .desc("Number of write requests accepted");
1461 .name(name() + ".readBursts")
1462 .desc("Number of DRAM read bursts, "
1463 "including those serviced by the write queue");
1466 .name(name() + ".writeBursts")
1467 .desc("Number of DRAM write bursts, "
1468 "including those merged in the write queue");
1471 .name(name() + ".servicedByWrQ")
1472 .desc("Number of DRAM read bursts serviced by the write queue");
1475 .name(name() + ".mergedWrBursts")
1476 .desc("Number of DRAM write bursts merged with an existing one");
1479 .name(name() + ".neitherReadNorWriteReqs")
1480 .desc("Number of requests that are neither read nor write");
1483 .init(banksPerRank
* ranksPerChannel
)
1484 .name(name() + ".perBankRdBursts")
1485 .desc("Per bank write bursts");
1488 .init(banksPerRank
* ranksPerChannel
)
1489 .name(name() + ".perBankWrBursts")
1490 .desc("Per bank write bursts");
1493 .name(name() + ".avgRdQLen")
1494 .desc("Average read queue length when enqueuing")
1498 .name(name() + ".avgWrQLen")
1499 .desc("Average write queue length when enqueuing")
1503 .name(name() + ".totQLat")
1504 .desc("Total ticks spent queuing");
1507 .name(name() + ".totBusLat")
1508 .desc("Total ticks spent in databus transfers");
1511 .name(name() + ".totMemAccLat")
1512 .desc("Total ticks spent from burst creation until serviced "
1516 .name(name() + ".avgQLat")
1517 .desc("Average queueing delay per DRAM burst")
1520 avgQLat
= totQLat
/ (readBursts
- servicedByWrQ
);
1523 .name(name() + ".avgBusLat")
1524 .desc("Average bus latency per DRAM burst")
1527 avgBusLat
= totBusLat
/ (readBursts
- servicedByWrQ
);
1530 .name(name() + ".avgMemAccLat")
1531 .desc("Average memory access latency per DRAM burst")
1534 avgMemAccLat
= totMemAccLat
/ (readBursts
- servicedByWrQ
);
1537 .name(name() + ".numRdRetry")
1538 .desc("Number of times read queue was full causing retry");
1541 .name(name() + ".numWrRetry")
1542 .desc("Number of times write queue was full causing retry");
1545 .name(name() + ".readRowHits")
1546 .desc("Number of row buffer hits during reads");
1549 .name(name() + ".writeRowHits")
1550 .desc("Number of row buffer hits during writes");
1553 .name(name() + ".readRowHitRate")
1554 .desc("Row buffer hit rate for reads")
1557 readRowHitRate
= (readRowHits
/ (readBursts
- servicedByWrQ
)) * 100;
1560 .name(name() + ".writeRowHitRate")
1561 .desc("Row buffer hit rate for writes")
1564 writeRowHitRate
= (writeRowHits
/ (writeBursts
- mergedWrBursts
)) * 100;
1567 .init(ceilLog2(burstSize
) + 1)
1568 .name(name() + ".readPktSize")
1569 .desc("Read request sizes (log2)");
1572 .init(ceilLog2(burstSize
) + 1)
1573 .name(name() + ".writePktSize")
1574 .desc("Write request sizes (log2)");
1577 .init(readBufferSize
)
1578 .name(name() + ".rdQLenPdf")
1579 .desc("What read queue length does an incoming req see");
1582 .init(writeBufferSize
)
1583 .name(name() + ".wrQLenPdf")
1584 .desc("What write queue length does an incoming req see");
1587 .init(maxAccessesPerRow
)
1588 .name(name() + ".bytesPerActivate")
1589 .desc("Bytes accessed per row activation")
1593 .init(readBufferSize
)
1594 .name(name() + ".rdPerTurnAround")
1595 .desc("Reads before turning the bus around for writes")
1599 .init(writeBufferSize
)
1600 .name(name() + ".wrPerTurnAround")
1601 .desc("Writes before turning the bus around for reads")
1605 .name(name() + ".bytesReadDRAM")
1606 .desc("Total number of bytes read from DRAM");
1609 .name(name() + ".bytesReadWrQ")
1610 .desc("Total number of bytes read from write queue");
1613 .name(name() + ".bytesWritten")
1614 .desc("Total number of bytes written to DRAM");
1617 .name(name() + ".bytesReadSys")
1618 .desc("Total read bytes from the system interface side");
1621 .name(name() + ".bytesWrittenSys")
1622 .desc("Total written bytes from the system interface side");
1625 .name(name() + ".avgRdBW")
1626 .desc("Average DRAM read bandwidth in MiByte/s")
1629 avgRdBW
= (bytesReadDRAM
/ 1000000) / simSeconds
;
1632 .name(name() + ".avgWrBW")
1633 .desc("Average achieved write bandwidth in MiByte/s")
1636 avgWrBW
= (bytesWritten
/ 1000000) / simSeconds
;
1639 .name(name() + ".avgRdBWSys")
1640 .desc("Average system read bandwidth in MiByte/s")
1643 avgRdBWSys
= (bytesReadSys
/ 1000000) / simSeconds
;
1646 .name(name() + ".avgWrBWSys")
1647 .desc("Average system write bandwidth in MiByte/s")
1650 avgWrBWSys
= (bytesWrittenSys
/ 1000000) / simSeconds
;
1653 .name(name() + ".peakBW")
1654 .desc("Theoretical peak bandwidth in MiByte/s")
1657 peakBW
= (SimClock::Frequency
/ tBURST
) * burstSize
/ 1000000;
1660 .name(name() + ".busUtil")
1661 .desc("Data bus utilization in percentage")
1664 busUtil
= (avgRdBW
+ avgWrBW
) / peakBW
* 100;
1667 .name(name() + ".totGap")
1668 .desc("Total gap between requests");
1671 .name(name() + ".avgGap")
1672 .desc("Average gap between requests")
1675 avgGap
= totGap
/ (readReqs
+ writeReqs
);
1677 // Stats for DRAM Power calculation based on Micron datasheet
1679 .name(name() + ".busUtilRead")
1680 .desc("Data bus utilization in percentage for reads")
1683 busUtilRead
= avgRdBW
/ peakBW
* 100;
1686 .name(name() + ".busUtilWrite")
1687 .desc("Data bus utilization in percentage for writes")
1690 busUtilWrite
= avgWrBW
/ peakBW
* 100;
1693 .name(name() + ".pageHitRate")
1694 .desc("Row buffer hit rate, read and write combined")
1697 pageHitRate
= (writeRowHits
+ readRowHits
) /
1698 (writeBursts
- mergedWrBursts
+ readBursts
- servicedByWrQ
) * 100;
1702 .name(name() + ".memoryStateTime")
1703 .desc("Time in different power states");
1704 pwrStateTime
.subname(0, "IDLE");
1705 pwrStateTime
.subname(1, "REF");
1706 pwrStateTime
.subname(2, "PRE_PDN");
1707 pwrStateTime
.subname(3, "ACT");
1708 pwrStateTime
.subname(4, "ACT_PDN");
1712 DRAMCtrl::recvFunctional(PacketPtr pkt
)
1714 // rely on the abstract memory
1715 functionalAccess(pkt
);
1719 DRAMCtrl::getSlavePort(const string
&if_name
, PortID idx
)
1721 if (if_name
!= "port") {
1722 return MemObject::getSlavePort(if_name
, idx
);
1729 DRAMCtrl::drain(DrainManager
*dm
)
1731 unsigned int count
= port
.drain(dm
);
1733 // if there is anything in any of our internal queues, keep track
1735 if (!(writeQueue
.empty() && readQueue
.empty() &&
1736 respQueue
.empty())) {
1737 DPRINTF(Drain
, "DRAM controller not drained, write: %d, read: %d,"
1738 " resp: %d\n", writeQueue
.size(), readQueue
.size(),
1743 // the only part that is not drained automatically over time
1744 // is the write queue, thus kick things into action if needed
1745 if (!writeQueue
.empty() && !nextReqEvent
.scheduled()) {
1746 schedule(nextReqEvent
, curTick());
1751 setDrainState(Drainable::Draining
);
1753 setDrainState(Drainable::Drained
);
1757 DRAMCtrl::MemoryPort::MemoryPort(const std::string
& name
, DRAMCtrl
& _memory
)
1758 : QueuedSlavePort(name
, &_memory
, queue
), queue(_memory
, *this),
1763 DRAMCtrl::MemoryPort::getAddrRanges() const
1765 AddrRangeList ranges
;
1766 ranges
.push_back(memory
.getAddrRange());
1771 DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt
)
1773 pkt
->pushLabel(memory
.name());
1775 if (!queue
.checkFunctional(pkt
)) {
1776 // Default implementation of SimpleTimingPort::recvFunctional()
1777 // calls recvAtomic() and throws away the latency; we can save a
1778 // little here by just not calculating the latency.
1779 memory
.recvFunctional(pkt
);
1786 DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt
)
1788 return memory
.recvAtomic(pkt
);
1792 DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt
)
1794 // pass it to the memory controller
1795 return memory
.recvTimingReq(pkt
);
1799 DRAMCtrlParams::create()
1801 return new DRAMCtrl(this);