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14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
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34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
51 * DRAMCtrl declaration
54 #ifndef __MEM_DRAM_CTRL_HH__
55 #define __MEM_DRAM_CTRL_HH__
59 #include <unordered_set>
62 #include "base/callback.hh"
63 #include "base/statistics.hh"
64 #include "enums/AddrMap.hh"
65 #include "enums/MemSched.hh"
66 #include "enums/PageManage.hh"
67 #include "mem/drampower.hh"
68 #include "mem/qos/mem_ctrl.hh"
69 #include "mem/qport.hh"
70 #include "params/DRAMCtrl.hh"
71 #include "sim/eventq.hh"
74 * The DRAM controller is a single-channel memory controller capturing
75 * the most important timing constraints associated with a
76 * contemporary DRAM. For multi-channel memory systems, the controller
77 * is combined with a crossbar model, with the channel address
78 * interleaving taking part in the crossbar.
80 * As a basic design principle, this controller
81 * model is not cycle callable, but instead uses events to: 1) decide
82 * when new decisions can be made, 2) when resources become available,
83 * 3) when things are to be considered done, and 4) when to send
84 * things back. Through these simple principles, the model delivers
85 * high performance, and lots of flexibility, allowing users to
86 * evaluate the system impact of a wide range of memory technologies,
87 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
89 * For more details, please see Hansson et al, "Simulating DRAM
90 * controllers for future system architecture exploration",
91 * Proc. ISPASS, 2014. If you use this model as part of your research
92 * please cite the paper.
94 * The low-power functionality implements a staggered powerdown
95 * similar to that described in "Optimized Active and Power-Down Mode
96 * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
98 class DRAMCtrl : public QoS::MemCtrl
103 // For now, make use of a queued slave port to avoid dealing with
104 // flow control for the responses being sent back
105 class MemoryPort : public QueuedSlavePort
108 RespPacketQueue queue;
113 MemoryPort(const std::string& name, DRAMCtrl& _memory);
117 Tick recvAtomic(PacketPtr pkt);
119 void recvFunctional(PacketPtr pkt);
121 bool recvTimingReq(PacketPtr);
123 virtual AddrRangeList getAddrRanges() const;
128 * Our incoming port, for a multi-ported controller add a crossbar
134 * Remember if the memory system is in timing mode
139 * Remember if we have to retry a request when available.
147 * Simple structure to hold the values needed to keep track of
148 * commands for DRAMPower
151 Data::MemCommand::cmds type;
155 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
157 : type(_type), bank(_bank), timeStamp(time_stamp)
162 * A basic class to track the bank state, i.e. what row is
163 * currently open (if any), when is the bank free to accept a new
164 * column (read/write) command, when can it be precharged, and
165 * when can it be activated.
167 * The bank also keeps track of how many bytes have been accessed
168 * in the open row since it was opened.
175 static const uint32_t NO_ROW = -1;
186 uint32_t rowAccesses;
187 uint32_t bytesAccessed;
190 openRow(NO_ROW), bank(0), bankgr(0),
191 rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
192 rowAccesses(0), bytesAccessed(0)
198 * The power state captures the different operational states of
199 * the DRAM and interacts with the bus read/write state machine,
200 * and the refresh state machine.
202 * PWR_IDLE : The idle state in which all banks are closed
203 * From here can transition to: PWR_REF, PWR_ACT,
206 * PWR_REF : Auto-refresh state. Will transition when refresh is
207 * complete based on power state prior to PWR_REF
208 * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
211 * PWR_SREF : Self-refresh state. Entered after refresh if
212 * previous state was PWR_PRE_PDN
213 * From here can transition to: PWR_IDLE
215 * PWR_PRE_PDN : Precharge power down state
216 * From here can transition to: PWR_REF, PWR_IDLE
218 * PWR_ACT : Activate state in which one or more banks are open
219 * From here can transition to: PWR_IDLE, PWR_ACT_PDN
221 * PWR_ACT_PDN : Activate power down state
222 * From here can transition to: PWR_ACT
234 * The refresh state is used to control the progress of the
235 * refresh scheduling. When normal operation is in progress the
236 * refresh state is idle. Once tREFI has elasped, a refresh event
237 * is triggered to start the following STM transitions which are
238 * used to issue a refresh and return back to normal operation
240 * REF_IDLE : IDLE state used during normal operation
241 * From here can transition to: REF_DRAIN
243 * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
244 * after self-refresh exit completes
245 * From here can transition to: REF_DRAIN
247 * REF_DRAIN : Drain state in which on going accesses complete.
248 * From here can transition to: REF_PD_EXIT
250 * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
251 * Next state dependent on whether banks are open
252 * From here can transition to: REF_PRE, REF_START
254 * REF_PRE : Close (precharge) all open banks
255 * From here can transition to: REF_START
257 * REF_START : Issue refresh command and update DRAMPower stats
258 * From here can transition to: REF_RUN
260 * REF_RUN : Refresh running, waiting for tRFC to expire
261 * From here can transition to: REF_IDLE, REF_SREF_EXIT
274 * Rank class includes a vector of banks. Refresh and Power state
275 * machines are defined per rank. Events required to change the
276 * state of the refresh and power state machine are scheduled per
277 * rank. This class allows the implementation of rank-wise refresh
278 * and rank-wise power-down.
280 class Rank : public EventManager
286 * A reference to the parent DRAMCtrl instance
291 * Since we are taking decisions out of order, we need to keep
292 * track of what power transition is happening at what time
294 PowerState pwrStateTrans;
297 * Previous low-power state, which will be re-entered after refresh.
299 PowerState pwrStatePostRefresh;
302 * Track when we transitioned to the current power state
307 * Keep track of when a refresh is due.
314 Stats::Scalar actEnergy;
315 Stats::Scalar preEnergy;
316 Stats::Scalar readEnergy;
317 Stats::Scalar writeEnergy;
318 Stats::Scalar refreshEnergy;
321 * Active Background Energy
323 Stats::Scalar actBackEnergy;
326 * Precharge Background Energy
328 Stats::Scalar preBackEnergy;
331 * Active Power-Down Energy
333 Stats::Scalar actPowerDownEnergy;
336 * Precharge Power-Down Energy
338 Stats::Scalar prePowerDownEnergy;
341 * self Refresh Energy
343 Stats::Scalar selfRefreshEnergy;
345 Stats::Scalar totalEnergy;
346 Stats::Scalar averagePower;
349 * Stat to track total DRAM idle time
352 Stats::Scalar totalIdleTime;
355 * Track time spent in each power state.
357 Stats::Vector pwrStateTime;
360 * Function to update Power Stats
362 void updatePowerStats();
365 * Schedule a power state transition in the future, and
366 * potentially override an already scheduled transition.
368 * @param pwr_state Power state to transition to
369 * @param tick Tick when transition should take place
371 void schedulePowerEvent(PowerState pwr_state, Tick tick);
376 * Current power state.
381 * current refresh state
383 RefreshState refreshState;
386 * rank is in or transitioning to power-down or self-refresh
388 bool inLowPowerState;
396 * Track number of packets in read queue going to this rank
398 uint32_t readEntries;
401 * Track number of packets in write queue going to this rank
403 uint32_t writeEntries;
406 * Number of ACT, RD, and WR events currently scheduled
407 * Incremented when a refresh event is started as well
408 * Used to determine when a low-power state can be entered
410 uint8_t outstandingEvents;
413 * delay power-down and self-refresh exit until this requirement is met
415 Tick wakeUpAllowedAt;
418 * One DRAMPower instance per rank
423 * List of commands issued, to be sent to DRAMPpower at refresh
424 * and stats dump. Keep commands here since commands to different
425 * banks are added out of order. Will only pass commands up to
426 * curTick() to DRAMPower after sorting.
428 std::vector<Command> cmdList;
431 * Vector of Banks. Each rank is made of several devices which in
432 * term are made from several banks.
434 std::vector<Bank> banks;
437 * To track number of banks which are currently active for
440 unsigned int numBanksActive;
442 /** List to keep track of activate ticks */
443 std::deque<Tick> actTicks;
445 Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank);
447 const std::string name() const
449 return csprintf("%s_%d", memory.name(), rank);
453 * Kick off accounting for power and refresh states and
454 * schedule initial refresh.
456 * @param ref_tick Tick for first refresh
458 void startup(Tick ref_tick);
461 * Stop the refresh events.
466 * Check if there is no refresh and no preparation of refresh ongoing
467 * i.e. the refresh state machine is in idle
469 * @param Return true if the rank is idle from a refresh point of view
471 bool inRefIdleState() const { return refreshState == REF_IDLE; }
474 * Check if the current rank has all banks closed and is not
475 * in a low power state
477 * @param Return true if the rank is idle from a bank
478 * and power point of view
480 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
483 * Trigger a self-refresh exit if there are entries enqueued
484 * Exit if there are any read entries regardless of the bus state.
485 * If we are currently issuing write commands, exit if we have any
486 * write commands enqueued as well.
487 * Could expand this in the future to analyze state of entire queue
490 * @return boolean indicating self-refresh exit should be scheduled
492 bool forceSelfRefreshExit() const {
493 return (readEntries != 0) ||
494 ((memory.busStateNext == WRITE) && (writeEntries != 0));
498 * Check if the command queue of current rank is idle
500 * @param Return true if the there are no commands in Q.
501 * Bus direction determines queue checked.
503 bool isQueueEmpty() const;
506 * Let the rank check if it was waiting for requests to drain
507 * to allow it to transition states.
509 void checkDrainDone();
512 * Push command out of cmdList queue that are scheduled at
513 * or before curTick() to DRAMPower library
514 * All commands before curTick are guaranteed to be complete
515 * and can safely be flushed.
520 * Function to register Stats
525 * Computes stats just prior to dump event
530 * Reset stats on a stats event
535 * Schedule a transition to power-down (sleep)
537 * @param pwr_state Power state to transition to
538 * @param tick Absolute tick when transition should take place
540 void powerDownSleep(PowerState pwr_state, Tick tick);
543 * schedule and event to wake-up from power-down or self-refresh
544 * and update bank timing parameters
546 * @param exit_delay Relative tick defining the delay required between
547 * low-power exit and the next command
549 void scheduleWakeUpEvent(Tick exit_delay);
551 void processWriteDoneEvent();
552 EventFunctionWrapper writeDoneEvent;
554 void processActivateEvent();
555 EventFunctionWrapper activateEvent;
557 void processPrechargeEvent();
558 EventFunctionWrapper prechargeEvent;
560 void processRefreshEvent();
561 EventFunctionWrapper refreshEvent;
563 void processPowerEvent();
564 EventFunctionWrapper powerEvent;
566 void processWakeUpEvent();
567 EventFunctionWrapper wakeUpEvent;
572 * Define the process to compute stats on a stats dump event, e.g. on
573 * simulation exit or intermediate stats dump. This is defined per rank
574 * as the per rank stats are based on state transition and periodically
575 * updated, requiring re-sync at exit.
577 class RankDumpCallback : public Callback
581 RankDumpCallback(Rank *r) : ranks(r) {}
582 virtual void process() { ranks->computeStats(); };
585 /** Define a process to clear power lib counters on a stats reset */
586 class RankResetCallback : public Callback
589 /** Pointer to the rank, thus we instantiate per rank */
593 RankResetCallback(Rank *r) : rank(r) {}
594 virtual void process() { rank->resetStats(); };
597 /** Define a process to store the time on a stats reset */
598 class MemResetCallback : public Callback
601 /** A reference to the DRAMCtrl instance */
605 MemResetCallback(DRAMCtrl *_mem) : mem(_mem) {}
606 virtual void process() { mem->lastStatsResetTick = curTick(); };
610 * A burst helper helps organize and manage a packet that is larger than
611 * the DRAM burst size. A system packet that is larger than the burst size
612 * is split into multiple DRAM packets and all those DRAM packets point to
613 * a single burst helper such that we know when the whole packet is served.
619 /** Number of DRAM bursts requred for a system packet **/
620 const unsigned int burstCount;
622 /** Number of DRAM bursts serviced so far for a system packet **/
623 unsigned int burstsServiced;
625 BurstHelper(unsigned int _burstCount)
626 : burstCount(_burstCount), burstsServiced(0)
631 * A DRAM packet stores packets along with the timestamp of when
632 * the packet entered the queue, and also the decoded address.
638 /** When did request enter the controller */
639 const Tick entryTime;
641 /** When will request leave the controller */
644 /** This comes from the outside world */
647 /** MasterID associated with the packet */
648 const MasterID _masterId;
652 /** Will be populated by address decoder */
658 * Bank id is calculated considering banks in all the ranks
659 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
660 * bankId = 8 --> rank1, bank0
662 const uint16_t bankId;
665 * The starting address of the DRAM packet.
666 * This address could be unaligned to burst size boundaries. The
667 * reason is to keep the address offset so we can accurately check
668 * incoming read packets with packets in the write queue.
673 * The size of this dram packet in bytes
674 * It is always equal or smaller than DRAM burst size
679 * A pointer to the BurstHelper if this DRAMPacket is a split packet
680 * If not a split packet (common case), this is set to NULL
682 BurstHelper* burstHelper;
687 * QoS value of the encapsulated packet read at queuing time
692 * Set the packet QoS value
693 * (interface compatibility with Packet)
695 inline void qosValue(const uint8_t qv) { _qosValue = qv; }
698 * Get the packet QoS value
699 * (interface compatibility with Packet)
701 inline uint8_t qosValue() const { return _qosValue; }
704 * Get the packet MasterID
705 * (interface compatibility with Packet)
707 inline MasterID masterId() const { return _masterId; }
710 * Get the packet size
711 * (interface compatibility with Packet)
713 inline unsigned int getSize() const { return size; }
716 * Get the packet address
717 * (interface compatibility with Packet)
719 inline Addr getAddr() const { return addr; }
722 * Return true if its a read packet
723 * (interface compatibility with Packet)
725 inline bool isRead() const { return read; }
728 * Return true if its a write packet
729 * (interface compatibility with Packet)
731 inline bool isWrite() const { return !read; }
734 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
735 uint32_t _row, uint16_t bank_id, Addr _addr,
736 unsigned int _size, Bank& bank_ref, Rank& rank_ref)
737 : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
738 _masterId(pkt->masterId()),
739 read(is_read), rank(_rank), bank(_bank), row(_row),
740 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
741 bankRef(bank_ref), rankRef(rank_ref), _qosValue(_pkt->qosValue())
746 // The DRAM packets are store in a multiple dequeue structure,
747 // based on their QoS priority
748 typedef std::deque<DRAMPacket*> DRAMPacketQueue;
751 * Bunch of things requires to setup "events" in gem5
752 * When event "respondEvent" occurs for example, the method
753 * processRespondEvent is called; no parameters are allowed
756 void processNextReqEvent();
757 EventFunctionWrapper nextReqEvent;
759 void processRespondEvent();
760 EventFunctionWrapper respondEvent;
763 * Check if the read queue has room for more entries
765 * @param pktCount The number of entries needed in the read queue
766 * @return true if read queue is full, false otherwise
768 bool readQueueFull(unsigned int pktCount) const;
771 * Check if the write queue has room for more entries
773 * @param pktCount The number of entries needed in the write queue
774 * @return true if write queue is full, false otherwise
776 bool writeQueueFull(unsigned int pktCount) const;
779 * When a new read comes in, first check if the write q has a
780 * pending request to the same address.\ If not, decode the
781 * address to populate rank/bank/row, create one or mutliple
782 * "dram_pkt", and push them to the back of the read queue.\
783 * If this is the only
784 * read request in the system, schedule an event to start
787 * @param pkt The request packet from the outside world
788 * @param pktCount The number of DRAM bursts the pkt
789 * translate to. If pkt size is larger then one full burst,
790 * then pktCount is greater than one.
792 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
795 * Decode the incoming pkt, create a dram_pkt and push to the
796 * back of the write queue. \If the write q length is more than
797 * the threshold specified by the user, ie the queue is beginning
798 * to get full, stop reads, and start draining writes.
800 * @param pkt The request packet from the outside world
801 * @param pktCount The number of DRAM bursts the pkt
802 * translate to. If pkt size is larger then one full burst,
803 * then pktCount is greater than one.
805 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
808 * Actually do the DRAM access - figure out the latency it
809 * will take to service the req based on bank state, channel state etc
810 * and then update those states to account for this request.\ Based
811 * on this, update the packet's "readyTime" and move it to the
812 * response q from where it will eventually go back to the outside
815 * @param pkt The DRAM packet created from the outside world pkt
817 void doDRAMAccess(DRAMPacket* dram_pkt);
820 * When a packet reaches its "readyTime" in the response Q,
821 * use the "access()" method in AbstractMemory to actually
822 * create the response packet, and send it back to the outside
825 * @param pkt The packet from the outside world
826 * @param static_latency Static latency to add before sending the packet
828 void accessAndRespond(PacketPtr pkt, Tick static_latency);
831 * Address decoder to figure out physical mapping onto ranks,
832 * banks, and rows. This function is called multiple times on the same
833 * system packet if the pakcet is larger than burst of the memory. The
834 * dramPktAddr is used for the offset within the packet.
836 * @param pkt The packet from the outside world
837 * @param dramPktAddr The starting address of the DRAM packet
838 * @param size The size of the DRAM packet in bytes
839 * @param isRead Is the request for a read or a write to DRAM
840 * @return A DRAMPacket pointer with the decoded information
842 DRAMPacket* decodeAddr(const PacketPtr pkt, Addr dramPktAddr,
843 unsigned int size, bool isRead) const;
846 * The memory schduler/arbiter - picks which request needs to
847 * go next, based on the specified policy such as FCFS or FR-FCFS
848 * and moves it to the head of the queue.
849 * Prioritizes accesses to the same rank as previous burst unless
850 * controller is switching command type.
852 * @param queue Queued requests to consider
853 * @param extra_col_delay Any extra delay due to a read/write switch
854 * @return an iterator to the selected packet, else queue.end()
856 DRAMPacketQueue::iterator chooseNext(DRAMPacketQueue& queue,
857 Tick extra_col_delay);
860 * For FR-FCFS policy reorder the read/write queue depending on row buffer
861 * hits and earliest bursts available in DRAM
863 * @param queue Queued requests to consider
864 * @param extra_col_delay Any extra delay due to a read/write switch
865 * @return an iterator to the selected packet, else queue.end()
867 DRAMPacketQueue::iterator chooseNextFRFCFS(DRAMPacketQueue& queue,
868 Tick extra_col_delay);
871 * Find which are the earliest banks ready to issue an activate
872 * for the enqueued requests. Assumes maximum of 32 banks per rank
873 * Also checks if the bank is already prepped.
875 * @param queue Queued requests to consider
876 * @param min_col_at time of seamless burst command
877 * @return One-hot encoded mask of bank indices
878 * @return boolean indicating burst can issue seamlessly, with no gaps
880 std::pair<std::vector<uint32_t>, bool>
881 minBankPrep(const DRAMPacketQueue& queue, Tick min_col_at) const;
884 * Keep track of when row activations happen, in order to enforce
885 * the maximum number of activations in the activation window. The
886 * method updates the time that the banks become available based
887 * on the current limits.
889 * @param rank_ref Reference to the rank
890 * @param bank_ref Reference to the bank
891 * @param act_tick Time when the activation takes place
892 * @param row Index of the row
894 void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
898 * Precharge a given bank and also update when the precharge is
899 * done. This will also deal with any stats related to the
900 * accesses to the open page.
902 * @param rank_ref The rank to precharge
903 * @param bank_ref The bank to precharge
904 * @param pre_at Time when the precharge takes place
905 * @param trace Is this an auto precharge then do not add to trace
907 void prechargeBank(Rank& rank_ref, Bank& bank_ref,
908 Tick pre_at, bool trace = true);
911 * Used for debugging to observe the contents of the queues.
913 void printQs() const;
916 * Burst-align an address.
918 * @param addr The potentially unaligned address
920 * @return An address aligned to a DRAM burst
922 Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
925 * The controller's main read and write queues, with support for QoS reordering
927 std::vector<DRAMPacketQueue> readQueue;
928 std::vector<DRAMPacketQueue> writeQueue;
931 * To avoid iterating over the write queue to check for
932 * overlapping transactions, maintain a set of burst addresses
933 * that are currently queued. Since we merge writes to the same
934 * location we never have more than one address to the same burst
937 std::unordered_set<Addr> isInWriteQueue;
940 * Response queue where read packets wait after we're done working
941 * with them, but it's not time to send the response yet. The
942 * responses are stored separately mostly to keep the code clean
943 * and help with events scheduling. For all logical purposes such
944 * as sizing the read queue, this and the main read queue need to
947 std::deque<DRAMPacket*> respQueue;
952 std::vector<Rank*> ranks;
955 * The following are basic design parameters of the memory
956 * controller, and are initialized based on parameter values.
957 * The rowsPerBank is determined based on the capacity, number of
958 * ranks and banks, the burst size, and the row buffer size.
960 const uint32_t deviceSize;
961 const uint32_t deviceBusWidth;
962 const uint32_t burstLength;
963 const uint32_t deviceRowBufferSize;
964 const uint32_t devicesPerRank;
965 const uint32_t burstSize;
966 const uint32_t rowBufferSize;
967 const uint32_t columnsPerRowBuffer;
968 const uint32_t columnsPerStripe;
969 const uint32_t ranksPerChannel;
970 const uint32_t bankGroupsPerRank;
971 const bool bankGroupArch;
972 const uint32_t banksPerRank;
973 const uint32_t channels;
974 uint32_t rowsPerBank;
975 const uint32_t readBufferSize;
976 const uint32_t writeBufferSize;
977 const uint32_t writeHighThreshold;
978 const uint32_t writeLowThreshold;
979 const uint32_t minWritesPerSwitch;
980 uint32_t writesThisTime;
981 uint32_t readsThisTime;
984 * Basic memory timing parameters initialized based on parameter
987 const Tick M5_CLASS_VAR_USED tCK;
991 const Tick tCCD_L_WR;
1006 const uint32_t activationLimit;
1007 const Tick rankToRankDly;
1008 const Tick wrToRdDly;
1009 const Tick rdToWrDly;
1012 * Memory controller configuration initialized based on parameter
1015 Enums::MemSched memSchedPolicy;
1016 Enums::AddrMap addrMapping;
1017 Enums::PageManage pageMgmt;
1020 * Max column accesses (read and write) per row, before forcefully
1023 const uint32_t maxAccessesPerRow;
1026 * Pipeline latency of the controller frontend. The frontend
1027 * contribution is added to writes (that complete when they are in
1028 * the write buffer) and reads that are serviced the write buffer.
1030 const Tick frontendLatency;
1033 * Pipeline latency of the backend and PHY. Along with the
1034 * frontend contribution, this latency is added to reads serviced
1037 const Tick backendLatency;
1040 * Till when must we wait before issuing next RD/WR burst?
1047 * The soonest you have to start thinking about the next request
1048 * is the longest access time that can occur before
1049 * nextBurstAt. Assuming you need to precharge, open a new row,
1050 * and access, it is tRP + tRCD + tCL.
1054 // All statistics that the model needs to capture
1055 Stats::Scalar readReqs;
1056 Stats::Scalar writeReqs;
1057 Stats::Scalar readBursts;
1058 Stats::Scalar writeBursts;
1059 Stats::Scalar bytesReadDRAM;
1060 Stats::Scalar bytesReadWrQ;
1061 Stats::Scalar bytesWritten;
1062 Stats::Scalar bytesReadSys;
1063 Stats::Scalar bytesWrittenSys;
1064 Stats::Scalar servicedByWrQ;
1065 Stats::Scalar mergedWrBursts;
1066 Stats::Scalar neitherReadNorWrite;
1067 Stats::Vector perBankRdBursts;
1068 Stats::Vector perBankWrBursts;
1069 Stats::Scalar numRdRetry;
1070 Stats::Scalar numWrRetry;
1071 Stats::Scalar totGap;
1072 Stats::Vector readPktSize;
1073 Stats::Vector writePktSize;
1074 Stats::Vector rdQLenPdf;
1075 Stats::Vector wrQLenPdf;
1076 Stats::Histogram bytesPerActivate;
1077 Stats::Histogram rdPerTurnAround;
1078 Stats::Histogram wrPerTurnAround;
1080 // per-master bytes read and written to memory
1081 Stats::Vector masterReadBytes;
1082 Stats::Vector masterWriteBytes;
1084 // per-master bytes read and written to memory rate
1085 Stats::Formula masterReadRate;
1086 Stats::Formula masterWriteRate;
1088 // per-master read and write serviced memory accesses
1089 Stats::Vector masterReadAccesses;
1090 Stats::Vector masterWriteAccesses;
1092 // per-master read and write total memory access latency
1093 Stats::Vector masterReadTotalLat;
1094 Stats::Vector masterWriteTotalLat;
1096 // per-master raed and write average memory access latency
1097 Stats::Formula masterReadAvgLat;
1098 Stats::Formula masterWriteAvgLat;
1100 // Latencies summed over all requests
1101 Stats::Scalar totQLat;
1102 Stats::Scalar totMemAccLat;
1103 Stats::Scalar totBusLat;
1105 // Average latencies per request
1106 Stats::Formula avgQLat;
1107 Stats::Formula avgBusLat;
1108 Stats::Formula avgMemAccLat;
1110 // Average bandwidth
1111 Stats::Formula avgRdBW;
1112 Stats::Formula avgWrBW;
1113 Stats::Formula avgRdBWSys;
1114 Stats::Formula avgWrBWSys;
1115 Stats::Formula peakBW;
1116 Stats::Formula busUtil;
1117 Stats::Formula busUtilRead;
1118 Stats::Formula busUtilWrite;
1120 // Average queue lengths
1121 Stats::Average avgRdQLen;
1122 Stats::Average avgWrQLen;
1124 // Row hit count and rate
1125 Stats::Scalar readRowHits;
1126 Stats::Scalar writeRowHits;
1127 Stats::Formula readRowHitRate;
1128 Stats::Formula writeRowHitRate;
1129 Stats::Formula avgGap;
1131 // DRAM Power Calculation
1132 Stats::Formula pageHitRate;
1134 // Holds the value of the rank of burst issued
1138 uint64_t timeStampOffset;
1140 /** The time when stats were last reset used to calculate average power */
1141 Tick lastStatsResetTick;
1144 * Upstream caches need this packet until true is returned, so
1145 * hold it for deletion until a subsequent call
1147 std::unique_ptr<Packet> pendingDelete;
1150 * This function increments the energy when called. If stats are
1151 * dumped periodically, note accumulated energy values will
1152 * appear in the stats (even if the stats are reset). This is a
1153 * result of the energy values coming from DRAMPower, and there
1154 * is currently no support for resetting the state.
1156 * @param rank Current rank
1158 void updatePowerStats(Rank& rank_ref);
1161 * Function for sorting Command structures based on timeStamp
1163 * @param a Memory Command
1164 * @param next Memory Command
1165 * @return true if timeStamp of Command 1 < timeStamp of Command 2
1167 static bool sortTime(const Command& cmd, const Command& cmd_next) {
1168 return cmd.timeStamp < cmd_next.timeStamp;
1173 void regStats() override;
1175 DRAMCtrl(const DRAMCtrlParams* p);
1177 DrainState drain() override;
1179 Port &getPort(const std::string &if_name,
1180 PortID idx=InvalidPortID) override;
1182 virtual void init() override;
1183 virtual void startup() override;
1184 virtual void drainResume() override;
1187 * Return true once refresh is complete for all ranks and there are no
1188 * additional commands enqueued. (only evaluated when draining)
1189 * This will ensure that all banks are closed, power state is IDLE, and
1190 * power stats have been updated
1192 * @return true if all ranks have refreshed, with no commands enqueued
1195 bool allRanksDrained() const;
1199 Tick recvAtomic(PacketPtr pkt);
1200 void recvFunctional(PacketPtr pkt);
1201 bool recvTimingReq(PacketPtr pkt);
1205 #endif //__MEM_DRAM_CTRL_HH__