2 * Copyright (c) 2012-2014 ARM Limited
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14 * Copyright (c) 2013 Amin Farmahini-Farahani
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18 * modification, are permitted provided that the following conditions are
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40 * Authors: Andreas Hansson
47 * DRAMCtrl declaration
50 #ifndef __MEM_DRAM_CTRL_HH__
51 #define __MEM_DRAM_CTRL_HH__
55 #include "base/statistics.hh"
56 #include "enums/AddrMap.hh"
57 #include "enums/MemSched.hh"
58 #include "enums/PageManage.hh"
59 #include "mem/abstract_mem.hh"
60 #include "mem/qport.hh"
61 #include "params/DRAMCtrl.hh"
62 #include "sim/eventq.hh"
65 * The DRAM controller is a basic single-channel memory controller
66 * aiming to mimic a high-level DRAM controller and the most important
67 * timing constraints associated with the DRAM. The focus is really on
68 * modelling the impact on the system rather than the DRAM itself,
69 * hence the focus is on the controller model and not on the
70 * memory. By adhering to the correct timing constraints, ultimately
71 * there is no need for a memory model in addition to the controller
74 * As a basic design principle, this controller is not cycle callable,
75 * but instead uses events to decide when new decisions can be made,
76 * when resources become available, when things are to be considered
77 * done, and when to send things back. Through these simple
78 * principles, we achieve a performant model that is not
79 * cycle-accurate, but enables us to evaluate the system impact of a
80 * wide range of memory technologies, and also collect statistics
81 * about the use of the memory.
83 class DRAMCtrl : public AbstractMemory
88 // For now, make use of a queued slave port to avoid dealing with
89 // flow control for the responses being sent back
90 class MemoryPort : public QueuedSlavePort
93 SlavePacketQueue queue;
98 MemoryPort(const std::string& name, DRAMCtrl& _memory);
102 Tick recvAtomic(PacketPtr pkt);
104 void recvFunctional(PacketPtr pkt);
106 bool recvTimingReq(PacketPtr);
108 virtual AddrRangeList getAddrRanges() const;
113 * Our incoming port, for a multi-ported controller add a crossbar
119 * Remember if we have to retry a request when available.
125 * Remember that a row buffer hit occured
130 * Bus state used to control the read/write switching and drive
131 * the scheduling of the next request.
142 /** List to keep track of activate ticks */
143 std::vector<std::deque<Tick>> actTicks;
146 * A basic class to track the bank state indirectly via times
147 * "freeAt" and "tRASDoneAt" and what page is currently open. The
148 * bank also keeps track of how many bytes have been accessed in
149 * the open row since it was opened.
156 static const uint32_t NO_ROW = -1;
164 uint32_t rowAccesses;
165 uint32_t bytesAccessed;
168 openRow(NO_ROW), freeAt(0), tRASDoneAt(0), actAllowedAt(0),
169 rowAccesses(0), bytesAccessed(0)
174 * A burst helper helps organize and manage a packet that is larger than
175 * the DRAM burst size. A system packet that is larger than the burst size
176 * is split into multiple DRAM packets and all those DRAM packets point to
177 * a single burst helper such that we know when the whole packet is served.
183 /** Number of DRAM bursts requred for a system packet **/
184 const unsigned int burstCount;
186 /** Number of DRAM bursts serviced so far for a system packet **/
187 unsigned int burstsServiced;
189 BurstHelper(unsigned int _burstCount)
190 : burstCount(_burstCount), burstsServiced(0)
195 * A DRAM packet stores packets along with the timestamp of when
196 * the packet entered the queue, and also the decoded address.
202 /** When did request enter the controller */
203 const Tick entryTime;
205 /** When will request leave the controller */
208 /** This comes from the outside world */
213 /** Will be populated by address decoder */
219 * Bank id is calculated considering banks in all the ranks
220 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
221 * bankId = 8 --> rank1, bank0
223 const uint16_t bankId;
226 * The starting address of the DRAM packet.
227 * This address could be unaligned to burst size boundaries. The
228 * reason is to keep the address offset so we can accurately check
229 * incoming read packets with packets in the write queue.
234 * The size of this dram packet in bytes
235 * It is always equal or smaller than DRAM burst size
240 * A pointer to the BurstHelper if this DRAMPacket is a split packet
241 * If not a split packet (common case), this is set to NULL
243 BurstHelper* burstHelper;
246 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
247 uint16_t _row, uint16_t bank_id, Addr _addr,
248 unsigned int _size, Bank& bank_ref)
249 : entryTime(curTick()), readyTime(curTick()),
250 pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
251 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
258 * Bunch of things requires to setup "events" in gem5
259 * When event "respondEvent" occurs for example, the method
260 * processRespondEvent is called; no parameters are allowed
263 void processNextReqEvent();
264 EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
266 void processRespondEvent();
267 EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
269 void processActivateEvent();
270 EventWrapper<DRAMCtrl, &DRAMCtrl::processActivateEvent> activateEvent;
272 void processPrechargeEvent();
273 EventWrapper<DRAMCtrl, &DRAMCtrl::processPrechargeEvent> prechargeEvent;
275 void processRefreshEvent();
276 EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent;
278 void processPowerEvent();
279 EventWrapper<DRAMCtrl,&DRAMCtrl::processPowerEvent> powerEvent;
282 * Check if the read queue has room for more entries
284 * @param pktCount The number of entries needed in the read queue
285 * @return true if read queue is full, false otherwise
287 bool readQueueFull(unsigned int pktCount) const;
290 * Check if the write queue has room for more entries
292 * @param pktCount The number of entries needed in the write queue
293 * @return true if write queue is full, false otherwise
295 bool writeQueueFull(unsigned int pktCount) const;
298 * When a new read comes in, first check if the write q has a
299 * pending request to the same address.\ If not, decode the
300 * address to populate rank/bank/row, create one or mutliple
301 * "dram_pkt", and push them to the back of the read queue.\
302 * If this is the only
303 * read request in the system, schedule an event to start
306 * @param pkt The request packet from the outside world
307 * @param pktCount The number of DRAM bursts the pkt
308 * translate to. If pkt size is larger then one full burst,
309 * then pktCount is greater than one.
311 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
314 * Decode the incoming pkt, create a dram_pkt and push to the
315 * back of the write queue. \If the write q length is more than
316 * the threshold specified by the user, ie the queue is beginning
317 * to get full, stop reads, and start draining writes.
319 * @param pkt The request packet from the outside world
320 * @param pktCount The number of DRAM bursts the pkt
321 * translate to. If pkt size is larger then one full burst,
322 * then pktCount is greater than one.
324 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
327 * Actually do the DRAM access - figure out the latency it
328 * will take to service the req based on bank state, channel state etc
329 * and then update those states to account for this request.\ Based
330 * on this, update the packet's "readyTime" and move it to the
331 * response q from where it will eventually go back to the outside
334 * @param pkt The DRAM packet created from the outside world pkt
336 void doDRAMAccess(DRAMPacket* dram_pkt);
339 * When a packet reaches its "readyTime" in the response Q,
340 * use the "access()" method in AbstractMemory to actually
341 * create the response packet, and send it back to the outside
344 * @param pkt The packet from the outside world
345 * @param static_latency Static latency to add before sending the packet
347 void accessAndRespond(PacketPtr pkt, Tick static_latency);
350 * Address decoder to figure out physical mapping onto ranks,
351 * banks, and rows. This function is called multiple times on the same
352 * system packet if the pakcet is larger than burst of the memory. The
353 * dramPktAddr is used for the offset within the packet.
355 * @param pkt The packet from the outside world
356 * @param dramPktAddr The starting address of the DRAM packet
357 * @param size The size of the DRAM packet in bytes
358 * @param isRead Is the request for a read or a write to DRAM
359 * @return A DRAMPacket pointer with the decoded information
361 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
365 * The memory schduler/arbiter - picks which request needs to
366 * go next, based on the specified policy such as FCFS or FR-FCFS
367 * and moves it to the head of the queue.
369 void chooseNext(std::deque<DRAMPacket*>& queue);
372 *Looks at the state of the banks, channels, row buffer hits etc
373 * to estimate how long a request will take to complete.
375 * @param dram_pkt The request for which we want to estimate latency
376 * @param inTime The tick at which you want to probe the memory
378 * @return A pair of ticks, one indicating how many ticks *after*
379 * inTime the request require, and the other indicating how
380 * much of that was just the bank access time, ignoring the
381 * ticks spent simply waiting for resources to become free
383 std::pair<Tick, Tick> estimateLatency(DRAMPacket* dram_pkt, Tick inTime);
386 * Move the request at the head of the read queue to the response
387 * queue, sorting by readyTime.\ If it is the only packet in the
388 * response queue, schedule a respond event to send it back to the
394 * For FR-FCFS policy reorder the read/write queue depending on row buffer
395 * hits and earliest banks available in DRAM
397 void reorderQueue(std::deque<DRAMPacket*>& queue);
400 * Find which are the earliest available banks for the enqueued
401 * requests. Assumes maximum of 64 banks per DIMM
403 * @param Queued requests to consider
404 * @return One-hot encoded mask of bank indices
406 uint64_t minBankFreeAt(const std::deque<DRAMPacket*>& queue) const;
409 * Keep track of when row activations happen, in order to enforce
410 * the maximum number of activations in the activation window. The
411 * method updates the time that the banks become available based
412 * on the current limits.
414 void recordActivate(Tick act_tick, uint8_t rank, uint8_t bank,
418 * Precharge a given bank and also update when the precharge is
419 * done. This will also deal with any stats related to the
420 * accesses to the open page.
422 * @param bank The bank to precharge
423 * @param free_at Time when the precharge is done
425 void prechargeBank(Bank& bank, Tick free_at);
427 void printParams() const;
430 * Used for debugging to observe the contents of the queues.
432 void printQs() const;
435 * The controller's main read and write queues
437 std::deque<DRAMPacket*> readQueue;
438 std::deque<DRAMPacket*> writeQueue;
441 * Response queue where read packets wait after we're done working
442 * with them, but it's not time to send the response yet. The
443 * responses are stored seperately mostly to keep the code clean
444 * and help with events scheduling. For all logical purposes such
445 * as sizing the read queue, this and the main read queue need to
448 std::deque<DRAMPacket*> respQueue;
451 * If we need to drain, keep the drain manager around until we're
454 DrainManager *drainManager;
457 * Multi-dimensional vector of banks, first dimension is ranks,
460 std::vector<std::vector<Bank> > banks;
463 * The following are basic design parameters of the memory
464 * controller, and are initialized based on parameter values.
465 * The rowsPerBank is determined based on the capacity, number of
466 * ranks and banks, the burst size, and the row buffer size.
468 const uint32_t deviceBusWidth;
469 const uint32_t burstLength;
470 const uint32_t deviceRowBufferSize;
471 const uint32_t devicesPerRank;
472 const uint32_t burstSize;
473 const uint32_t rowBufferSize;
474 const uint32_t columnsPerRowBuffer;
475 const uint32_t ranksPerChannel;
476 const uint32_t banksPerRank;
477 const uint32_t channels;
478 uint32_t rowsPerBank;
479 const uint32_t readBufferSize;
480 const uint32_t writeBufferSize;
481 const uint32_t writeHighThreshold;
482 const uint32_t writeLowThreshold;
483 const uint32_t minWritesPerSwitch;
484 uint32_t writesThisTime;
485 uint32_t readsThisTime;
488 * Basic memory timing parameters initialized based on parameter
502 const uint32_t activationLimit;
505 * Memory controller configuration initialized based on parameter
508 Enums::MemSched memSchedPolicy;
509 Enums::AddrMap addrMapping;
510 Enums::PageManage pageMgmt;
513 * Max column accesses (read and write) per row, before forefully
516 const uint32_t maxAccessesPerRow;
519 * Pipeline latency of the controller frontend. The frontend
520 * contribution is added to writes (that complete when they are in
521 * the write buffer) and reads that are serviced the write buffer.
523 const Tick frontendLatency;
526 * Pipeline latency of the backend and PHY. Along with the
527 * frontend contribution, this latency is added to reads serviced
530 const Tick backendLatency;
533 * Till when has the main data bus been spoken for already?
538 * Keep track of when a refresh is due.
543 * The refresh state is used to control the progress of the
544 * refresh scheduling. When normal operation is in progress the
545 * refresh state is idle. From there, it progresses to the refresh
546 * drain state once tREFI has passed. The refresh drain state
547 * captures the DRAM row active state, as it will stay there until
548 * all ongoing accesses complete. Thereafter all banks are
549 * precharged, and lastly, the DRAM is refreshed.
558 RefreshState refreshState;
561 * The power state captures the different operational states of
562 * the DRAM and interacts with the bus read/write state machine,
563 * and the refresh state machine. In the idle state all banks are
564 * precharged. From there we either go to an auto refresh (as
565 * determined by the refresh state machine), or to a precharge
566 * power down mode. From idle the memory can also go to the active
567 * state (with one or more banks active), and in turn from there
568 * to active power down. At the moment we do not capture the deep
569 * power down and self-refresh state.
580 * Since we are taking decisions out of order, we need to keep
581 * track of what power transition is happening at what time, such
582 * that we can go back in time and change history. For example, if
583 * we precharge all banks and schedule going to the idle state, we
584 * might at a later point decide to activate a bank before the
585 * transition to idle would have taken place.
587 PowerState pwrStateTrans;
590 * Current power state.
595 * Schedule a power state transition in the future, and
596 * potentially override an already scheduled transition.
598 * @param pwr_state Power state to transition to
599 * @param tick Tick when transition should take place
601 void schedulePowerEvent(PowerState pwr_state, Tick tick);
606 * The soonest you have to start thinking about the next request
607 * is the longest access time that can occur before
608 * busBusyUntil. Assuming you need to precharge, open a new row,
609 * and access, it is tRP + tRCD + tCL.
613 // All statistics that the model needs to capture
614 Stats::Scalar readReqs;
615 Stats::Scalar writeReqs;
616 Stats::Scalar readBursts;
617 Stats::Scalar writeBursts;
618 Stats::Scalar bytesReadDRAM;
619 Stats::Scalar bytesReadWrQ;
620 Stats::Scalar bytesWritten;
621 Stats::Scalar bytesReadSys;
622 Stats::Scalar bytesWrittenSys;
623 Stats::Scalar servicedByWrQ;
624 Stats::Scalar mergedWrBursts;
625 Stats::Scalar neitherReadNorWrite;
626 Stats::Vector perBankRdBursts;
627 Stats::Vector perBankWrBursts;
628 Stats::Scalar numRdRetry;
629 Stats::Scalar numWrRetry;
630 Stats::Scalar totGap;
631 Stats::Vector readPktSize;
632 Stats::Vector writePktSize;
633 Stats::Vector rdQLenPdf;
634 Stats::Vector wrQLenPdf;
635 Stats::Histogram bytesPerActivate;
636 Stats::Histogram rdPerTurnAround;
637 Stats::Histogram wrPerTurnAround;
639 // Latencies summed over all requests
640 Stats::Scalar totQLat;
641 Stats::Scalar totMemAccLat;
642 Stats::Scalar totBusLat;
643 Stats::Scalar totBankLat;
645 // Average latencies per request
646 Stats::Formula avgQLat;
647 Stats::Formula avgBankLat;
648 Stats::Formula avgBusLat;
649 Stats::Formula avgMemAccLat;
652 Stats::Formula avgRdBW;
653 Stats::Formula avgWrBW;
654 Stats::Formula avgRdBWSys;
655 Stats::Formula avgWrBWSys;
656 Stats::Formula peakBW;
657 Stats::Formula busUtil;
658 Stats::Formula busUtilRead;
659 Stats::Formula busUtilWrite;
661 // Average queue lengths
662 Stats::Average avgRdQLen;
663 Stats::Average avgWrQLen;
665 // Row hit count and rate
666 Stats::Scalar readRowHits;
667 Stats::Scalar writeRowHits;
668 Stats::Formula readRowHitRate;
669 Stats::Formula writeRowHitRate;
670 Stats::Formula avgGap;
672 // DRAM Power Calculation
673 Stats::Formula pageHitRate;
674 Stats::Vector pwrStateTime;
676 // Track when we transitioned to the current power state
679 // To track number of banks which are currently active
680 unsigned int numBanksActive;
682 /** @todo this is a temporary workaround until the 4-phase code is
683 * committed. upstream caches needs this packet until true is returned, so
684 * hold onto it for deletion until a subsequent call
686 std::vector<PacketPtr> pendingDelete;
692 DRAMCtrl(const DRAMCtrlParams* p);
694 unsigned int drain(DrainManager* dm);
696 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
697 PortID idx = InvalidPortID);
700 virtual void startup();
704 Tick recvAtomic(PacketPtr pkt);
705 void recvFunctional(PacketPtr pkt);
706 bool recvTimingReq(PacketPtr pkt);
710 #endif //__MEM_DRAM_CTRL_HH__