2 * Copyright (c) 2012-2014 ARM Limited
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14 * Copyright (c) 2013 Amin Farmahini-Farahani
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40 * Authors: Andreas Hansson
47 * DRAMCtrl declaration
50 #ifndef __MEM_DRAM_CTRL_HH__
51 #define __MEM_DRAM_CTRL_HH__
55 #include "base/statistics.hh"
56 #include "enums/AddrMap.hh"
57 #include "enums/MemSched.hh"
58 #include "enums/PageManage.hh"
59 #include "mem/abstract_mem.hh"
60 #include "mem/qport.hh"
61 #include "params/DRAMCtrl.hh"
62 #include "sim/eventq.hh"
65 * The DRAM controller is a basic single-channel memory controller
66 * aiming to mimic a high-level DRAM controller and the most important
67 * timing constraints associated with the DRAM. The focus is really on
68 * modelling the impact on the system rather than the DRAM itself,
69 * hence the focus is on the controller model and not on the
70 * memory. By adhering to the correct timing constraints, ultimately
71 * there is no need for a memory model in addition to the controller
74 * As a basic design principle, this controller is not cycle callable,
75 * but instead uses events to decide when new decisions can be made,
76 * when resources become available, when things are to be considered
77 * done, and when to send things back. Through these simple
78 * principles, we achieve a performant model that is not
79 * cycle-accurate, but enables us to evaluate the system impact of a
80 * wide range of memory technologies, and also collect statistics
81 * about the use of the memory.
83 class DRAMCtrl : public AbstractMemory
88 // For now, make use of a queued slave port to avoid dealing with
89 // flow control for the responses being sent back
90 class MemoryPort : public QueuedSlavePort
93 SlavePacketQueue queue;
98 MemoryPort(const std::string& name, DRAMCtrl& _memory);
102 Tick recvAtomic(PacketPtr pkt);
104 void recvFunctional(PacketPtr pkt);
106 bool recvTimingReq(PacketPtr);
108 virtual AddrRangeList getAddrRanges() const;
113 * Our incoming port, for a multi-ported controller add a crossbar
119 * Remember if we have to retry a request when available.
125 * Bus state used to control the read/write switching and drive
126 * the scheduling of the next request.
137 /** List to keep track of activate ticks */
138 std::vector<std::deque<Tick>> actTicks;
141 * A basic class to track the bank state, i.e. what row is
142 * currently open (if any), when is the bank free to accept a new
143 * column (read/write) command, when can it be precharged, and
144 * when can it be activated.
146 * The bank also keeps track of how many bytes have been accessed
147 * in the open row since it was opened.
154 static const uint32_t NO_ROW = -1;
162 uint32_t rowAccesses;
163 uint32_t bytesAccessed;
166 openRow(NO_ROW), colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
167 rowAccesses(0), bytesAccessed(0)
172 * A burst helper helps organize and manage a packet that is larger than
173 * the DRAM burst size. A system packet that is larger than the burst size
174 * is split into multiple DRAM packets and all those DRAM packets point to
175 * a single burst helper such that we know when the whole packet is served.
181 /** Number of DRAM bursts requred for a system packet **/
182 const unsigned int burstCount;
184 /** Number of DRAM bursts serviced so far for a system packet **/
185 unsigned int burstsServiced;
187 BurstHelper(unsigned int _burstCount)
188 : burstCount(_burstCount), burstsServiced(0)
193 * A DRAM packet stores packets along with the timestamp of when
194 * the packet entered the queue, and also the decoded address.
200 /** When did request enter the controller */
201 const Tick entryTime;
203 /** When will request leave the controller */
206 /** This comes from the outside world */
211 /** Will be populated by address decoder */
217 * Bank id is calculated considering banks in all the ranks
218 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
219 * bankId = 8 --> rank1, bank0
221 const uint16_t bankId;
224 * The starting address of the DRAM packet.
225 * This address could be unaligned to burst size boundaries. The
226 * reason is to keep the address offset so we can accurately check
227 * incoming read packets with packets in the write queue.
232 * The size of this dram packet in bytes
233 * It is always equal or smaller than DRAM burst size
238 * A pointer to the BurstHelper if this DRAMPacket is a split packet
239 * If not a split packet (common case), this is set to NULL
241 BurstHelper* burstHelper;
244 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
245 uint16_t _row, uint16_t bank_id, Addr _addr,
246 unsigned int _size, Bank& bank_ref)
247 : entryTime(curTick()), readyTime(curTick()),
248 pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
249 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
256 * Bunch of things requires to setup "events" in gem5
257 * When event "respondEvent" occurs for example, the method
258 * processRespondEvent is called; no parameters are allowed
261 void processNextReqEvent();
262 EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
264 void processRespondEvent();
265 EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
267 void processActivateEvent();
268 EventWrapper<DRAMCtrl, &DRAMCtrl::processActivateEvent> activateEvent;
270 void processPrechargeEvent();
271 EventWrapper<DRAMCtrl, &DRAMCtrl::processPrechargeEvent> prechargeEvent;
273 void processRefreshEvent();
274 EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent;
276 void processPowerEvent();
277 EventWrapper<DRAMCtrl,&DRAMCtrl::processPowerEvent> powerEvent;
280 * Check if the read queue has room for more entries
282 * @param pktCount The number of entries needed in the read queue
283 * @return true if read queue is full, false otherwise
285 bool readQueueFull(unsigned int pktCount) const;
288 * Check if the write queue has room for more entries
290 * @param pktCount The number of entries needed in the write queue
291 * @return true if write queue is full, false otherwise
293 bool writeQueueFull(unsigned int pktCount) const;
296 * When a new read comes in, first check if the write q has a
297 * pending request to the same address.\ If not, decode the
298 * address to populate rank/bank/row, create one or mutliple
299 * "dram_pkt", and push them to the back of the read queue.\
300 * If this is the only
301 * read request in the system, schedule an event to start
304 * @param pkt The request packet from the outside world
305 * @param pktCount The number of DRAM bursts the pkt
306 * translate to. If pkt size is larger then one full burst,
307 * then pktCount is greater than one.
309 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
312 * Decode the incoming pkt, create a dram_pkt and push to the
313 * back of the write queue. \If the write q length is more than
314 * the threshold specified by the user, ie the queue is beginning
315 * to get full, stop reads, and start draining writes.
317 * @param pkt The request packet from the outside world
318 * @param pktCount The number of DRAM bursts the pkt
319 * translate to. If pkt size is larger then one full burst,
320 * then pktCount is greater than one.
322 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
325 * Actually do the DRAM access - figure out the latency it
326 * will take to service the req based on bank state, channel state etc
327 * and then update those states to account for this request.\ Based
328 * on this, update the packet's "readyTime" and move it to the
329 * response q from where it will eventually go back to the outside
332 * @param pkt The DRAM packet created from the outside world pkt
334 void doDRAMAccess(DRAMPacket* dram_pkt);
337 * When a packet reaches its "readyTime" in the response Q,
338 * use the "access()" method in AbstractMemory to actually
339 * create the response packet, and send it back to the outside
342 * @param pkt The packet from the outside world
343 * @param static_latency Static latency to add before sending the packet
345 void accessAndRespond(PacketPtr pkt, Tick static_latency);
348 * Address decoder to figure out physical mapping onto ranks,
349 * banks, and rows. This function is called multiple times on the same
350 * system packet if the pakcet is larger than burst of the memory. The
351 * dramPktAddr is used for the offset within the packet.
353 * @param pkt The packet from the outside world
354 * @param dramPktAddr The starting address of the DRAM packet
355 * @param size The size of the DRAM packet in bytes
356 * @param isRead Is the request for a read or a write to DRAM
357 * @return A DRAMPacket pointer with the decoded information
359 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
363 * The memory schduler/arbiter - picks which request needs to
364 * go next, based on the specified policy such as FCFS or FR-FCFS
365 * and moves it to the head of the queue.
367 void chooseNext(std::deque<DRAMPacket*>& queue);
370 * Move the request at the head of the read queue to the response
371 * queue, sorting by readyTime.\ If it is the only packet in the
372 * response queue, schedule a respond event to send it back to the
378 * For FR-FCFS policy reorder the read/write queue depending on row buffer
379 * hits and earliest banks available in DRAM
381 void reorderQueue(std::deque<DRAMPacket*>& queue);
384 * Find which are the earliest banks ready to issue an activate
385 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
387 * @param Queued requests to consider
388 * @return One-hot encoded mask of bank indices
390 uint64_t minBankActAt(const std::deque<DRAMPacket*>& queue) const;
393 * Keep track of when row activations happen, in order to enforce
394 * the maximum number of activations in the activation window. The
395 * method updates the time that the banks become available based
396 * on the current limits.
398 * @param act_tick Time when the activation takes place
399 * @param rank Index of the rank
400 * @param bank Index of the bank
401 * @param row Index of the row
402 * @param bank_ref Reference to the bank
404 void activateBank(Tick act_tick, uint8_t rank, uint8_t bank,
405 uint16_t row, Bank& bank_ref);
408 * Precharge a given bank and also update when the precharge is
409 * done. This will also deal with any stats related to the
410 * accesses to the open page.
412 * @param bank The bank to precharge
413 * @param pre_at Time when the precharge takes place
415 void prechargeBank(Bank& bank, Tick pre_at);
417 void printParams() const;
420 * Used for debugging to observe the contents of the queues.
422 void printQs() const;
425 * The controller's main read and write queues
427 std::deque<DRAMPacket*> readQueue;
428 std::deque<DRAMPacket*> writeQueue;
431 * Response queue where read packets wait after we're done working
432 * with them, but it's not time to send the response yet. The
433 * responses are stored seperately mostly to keep the code clean
434 * and help with events scheduling. For all logical purposes such
435 * as sizing the read queue, this and the main read queue need to
438 std::deque<DRAMPacket*> respQueue;
441 * If we need to drain, keep the drain manager around until we're
444 DrainManager *drainManager;
447 * Multi-dimensional vector of banks, first dimension is ranks,
450 std::vector<std::vector<Bank> > banks;
453 * The following are basic design parameters of the memory
454 * controller, and are initialized based on parameter values.
455 * The rowsPerBank is determined based on the capacity, number of
456 * ranks and banks, the burst size, and the row buffer size.
458 const uint32_t deviceBusWidth;
459 const uint32_t burstLength;
460 const uint32_t deviceRowBufferSize;
461 const uint32_t devicesPerRank;
462 const uint32_t burstSize;
463 const uint32_t rowBufferSize;
464 const uint32_t columnsPerRowBuffer;
465 const uint32_t ranksPerChannel;
466 const uint32_t banksPerRank;
467 const uint32_t channels;
468 uint32_t rowsPerBank;
469 const uint32_t readBufferSize;
470 const uint32_t writeBufferSize;
471 const uint32_t writeHighThreshold;
472 const uint32_t writeLowThreshold;
473 const uint32_t minWritesPerSwitch;
474 uint32_t writesThisTime;
475 uint32_t readsThisTime;
478 * Basic memory timing parameters initialized based on parameter
493 const uint32_t activationLimit;
496 * Memory controller configuration initialized based on parameter
499 Enums::MemSched memSchedPolicy;
500 Enums::AddrMap addrMapping;
501 Enums::PageManage pageMgmt;
504 * Max column accesses (read and write) per row, before forefully
507 const uint32_t maxAccessesPerRow;
510 * Pipeline latency of the controller frontend. The frontend
511 * contribution is added to writes (that complete when they are in
512 * the write buffer) and reads that are serviced the write buffer.
514 const Tick frontendLatency;
517 * Pipeline latency of the backend and PHY. Along with the
518 * frontend contribution, this latency is added to reads serviced
521 const Tick backendLatency;
524 * Till when has the main data bus been spoken for already?
529 * Keep track of when a refresh is due.
534 * The refresh state is used to control the progress of the
535 * refresh scheduling. When normal operation is in progress the
536 * refresh state is idle. From there, it progresses to the refresh
537 * drain state once tREFI has passed. The refresh drain state
538 * captures the DRAM row active state, as it will stay there until
539 * all ongoing accesses complete. Thereafter all banks are
540 * precharged, and lastly, the DRAM is refreshed.
549 RefreshState refreshState;
552 * The power state captures the different operational states of
553 * the DRAM and interacts with the bus read/write state machine,
554 * and the refresh state machine. In the idle state all banks are
555 * precharged. From there we either go to an auto refresh (as
556 * determined by the refresh state machine), or to a precharge
557 * power down mode. From idle the memory can also go to the active
558 * state (with one or more banks active), and in turn from there
559 * to active power down. At the moment we do not capture the deep
560 * power down and self-refresh state.
571 * Since we are taking decisions out of order, we need to keep
572 * track of what power transition is happening at what time, such
573 * that we can go back in time and change history. For example, if
574 * we precharge all banks and schedule going to the idle state, we
575 * might at a later point decide to activate a bank before the
576 * transition to idle would have taken place.
578 PowerState pwrStateTrans;
581 * Current power state.
586 * Schedule a power state transition in the future, and
587 * potentially override an already scheduled transition.
589 * @param pwr_state Power state to transition to
590 * @param tick Tick when transition should take place
592 void schedulePowerEvent(PowerState pwr_state, Tick tick);
597 * The soonest you have to start thinking about the next request
598 * is the longest access time that can occur before
599 * busBusyUntil. Assuming you need to precharge, open a new row,
600 * and access, it is tRP + tRCD + tCL.
604 // All statistics that the model needs to capture
605 Stats::Scalar readReqs;
606 Stats::Scalar writeReqs;
607 Stats::Scalar readBursts;
608 Stats::Scalar writeBursts;
609 Stats::Scalar bytesReadDRAM;
610 Stats::Scalar bytesReadWrQ;
611 Stats::Scalar bytesWritten;
612 Stats::Scalar bytesReadSys;
613 Stats::Scalar bytesWrittenSys;
614 Stats::Scalar servicedByWrQ;
615 Stats::Scalar mergedWrBursts;
616 Stats::Scalar neitherReadNorWrite;
617 Stats::Vector perBankRdBursts;
618 Stats::Vector perBankWrBursts;
619 Stats::Scalar numRdRetry;
620 Stats::Scalar numWrRetry;
621 Stats::Scalar totGap;
622 Stats::Vector readPktSize;
623 Stats::Vector writePktSize;
624 Stats::Vector rdQLenPdf;
625 Stats::Vector wrQLenPdf;
626 Stats::Histogram bytesPerActivate;
627 Stats::Histogram rdPerTurnAround;
628 Stats::Histogram wrPerTurnAround;
630 // Latencies summed over all requests
631 Stats::Scalar totQLat;
632 Stats::Scalar totMemAccLat;
633 Stats::Scalar totBusLat;
635 // Average latencies per request
636 Stats::Formula avgQLat;
637 Stats::Formula avgBusLat;
638 Stats::Formula avgMemAccLat;
641 Stats::Formula avgRdBW;
642 Stats::Formula avgWrBW;
643 Stats::Formula avgRdBWSys;
644 Stats::Formula avgWrBWSys;
645 Stats::Formula peakBW;
646 Stats::Formula busUtil;
647 Stats::Formula busUtilRead;
648 Stats::Formula busUtilWrite;
650 // Average queue lengths
651 Stats::Average avgRdQLen;
652 Stats::Average avgWrQLen;
654 // Row hit count and rate
655 Stats::Scalar readRowHits;
656 Stats::Scalar writeRowHits;
657 Stats::Formula readRowHitRate;
658 Stats::Formula writeRowHitRate;
659 Stats::Formula avgGap;
661 // DRAM Power Calculation
662 Stats::Formula pageHitRate;
663 Stats::Vector pwrStateTime;
665 // Track when we transitioned to the current power state
668 // To track number of banks which are currently active
669 unsigned int numBanksActive;
671 /** @todo this is a temporary workaround until the 4-phase code is
672 * committed. upstream caches needs this packet until true is returned, so
673 * hold onto it for deletion until a subsequent call
675 std::vector<PacketPtr> pendingDelete;
681 DRAMCtrl(const DRAMCtrlParams* p);
683 unsigned int drain(DrainManager* dm);
685 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
686 PortID idx = InvalidPortID);
689 virtual void startup();
693 Tick recvAtomic(PacketPtr pkt);
694 void recvFunctional(PacketPtr pkt);
695 bool recvTimingReq(PacketPtr pkt);
699 #endif //__MEM_DRAM_CTRL_HH__