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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
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26 * this software without specific prior written permission.
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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Andreas Hansson
51 * DRAMCtrl declaration
54 #ifndef __MEM_DRAM_CTRL_HH__
55 #define __MEM_DRAM_CTRL_HH__
59 #include <unordered_set>
61 #include "base/callback.hh"
62 #include "base/statistics.hh"
63 #include "enums/AddrMap.hh"
64 #include "enums/MemSched.hh"
65 #include "enums/PageManage.hh"
66 #include "mem/abstract_mem.hh"
67 #include "mem/qport.hh"
68 #include "params/DRAMCtrl.hh"
69 #include "sim/eventq.hh"
70 #include "mem/drampower.hh"
73 * The DRAM controller is a single-channel memory controller capturing
74 * the most important timing constraints associated with a
75 * contemporary DRAM. For multi-channel memory systems, the controller
76 * is combined with a crossbar model, with the channel address
77 * interleaving taking part in the crossbar.
79 * As a basic design principle, this controller
80 * model is not cycle callable, but instead uses events to: 1) decide
81 * when new decisions can be made, 2) when resources become available,
82 * 3) when things are to be considered done, and 4) when to send
83 * things back. Through these simple principles, the model delivers
84 * high performance, and lots of flexibility, allowing users to
85 * evaluate the system impact of a wide range of memory technologies,
86 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
88 * For more details, please see Hansson et al, "Simulating DRAM
89 * controllers for future system architecture exploration",
90 * Proc. ISPASS, 2014. If you use this model as part of your research
91 * please cite the paper.
93 * The low-power functionality implements a staggered powerdown
94 * similar to that described in "Optimized Active and Power-Down Mode
95 * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
97 class DRAMCtrl : public AbstractMemory
102 // For now, make use of a queued slave port to avoid dealing with
103 // flow control for the responses being sent back
104 class MemoryPort : public QueuedSlavePort
107 RespPacketQueue queue;
112 MemoryPort(const std::string& name, DRAMCtrl& _memory);
116 Tick recvAtomic(PacketPtr pkt);
118 void recvFunctional(PacketPtr pkt);
120 bool recvTimingReq(PacketPtr);
122 virtual AddrRangeList getAddrRanges() const;
127 * Our incoming port, for a multi-ported controller add a crossbar
133 * Remeber if the memory system is in timing mode
138 * Remember if we have to retry a request when available.
144 * Bus state used to control the read/write switching and drive
145 * the scheduling of the next request.
154 /* bus state for next request event triggered */
155 BusState busStateNext;
158 * Simple structure to hold the values needed to keep track of
159 * commands for DRAMPower
162 Data::MemCommand::cmds type;
166 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
168 : type(_type), bank(_bank), timeStamp(time_stamp)
173 * A basic class to track the bank state, i.e. what row is
174 * currently open (if any), when is the bank free to accept a new
175 * column (read/write) command, when can it be precharged, and
176 * when can it be activated.
178 * The bank also keeps track of how many bytes have been accessed
179 * in the open row since it was opened.
186 static const uint32_t NO_ROW = -1;
196 uint32_t rowAccesses;
197 uint32_t bytesAccessed;
200 openRow(NO_ROW), bank(0), bankgr(0),
201 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
202 rowAccesses(0), bytesAccessed(0)
208 * The power state captures the different operational states of
209 * the DRAM and interacts with the bus read/write state machine,
210 * and the refresh state machine.
212 * PWR_IDLE : The idle state in which all banks are closed
213 * From here can transition to: PWR_REF, PWR_ACT,
216 * PWR_REF : Auto-refresh state. Will transition when refresh is
217 * complete based on power state prior to PWR_REF
218 * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
221 * PWR_SREF : Self-refresh state. Entered after refresh if
222 * previous state was PWR_PRE_PDN
223 * From here can transition to: PWR_IDLE
225 * PWR_PRE_PDN : Precharge power down state
226 * From here can transition to: PWR_REF, PWR_IDLE
228 * PWR_ACT : Activate state in which one or more banks are open
229 * From here can transition to: PWR_IDLE, PWR_ACT_PDN
231 * PWR_ACT_PDN : Activate power down state
232 * From here can transition to: PWR_ACT
244 * The refresh state is used to control the progress of the
245 * refresh scheduling. When normal operation is in progress the
246 * refresh state is idle. Once tREFI has elasped, a refresh event
247 * is triggered to start the following STM transitions which are
248 * used to issue a refresh and return back to normal operation
250 * REF_IDLE : IDLE state used during normal operation
251 * From here can transition to: REF_DRAIN
253 * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
254 * after self-refresh exit completes
255 * From here can transition to: REF_DRAIN
257 * REF_DRAIN : Drain state in which on going accesses complete.
258 * From here can transition to: REF_PD_EXIT
260 * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
261 * Next state dependent on whether banks are open
262 * From here can transition to: REF_PRE, REF_START
264 * REF_PRE : Close (precharge) all open banks
265 * From here can transition to: REF_START
267 * REF_START : Issue refresh command and update DRAMPower stats
268 * From here can transition to: REF_RUN
270 * REF_RUN : Refresh running, waiting for tRFC to expire
271 * From here can transition to: REF_IDLE, REF_SREF_EXIT
284 * Rank class includes a vector of banks. Refresh and Power state
285 * machines are defined per rank. Events required to change the
286 * state of the refresh and power state machine are scheduled per
287 * rank. This class allows the implementation of rank-wise refresh
288 * and rank-wise power-down.
290 class Rank : public EventManager
296 * A reference to the parent DRAMCtrl instance
301 * Since we are taking decisions out of order, we need to keep
302 * track of what power transition is happening at what time
304 PowerState pwrStateTrans;
307 * Previous low-power state, which will be re-entered after refresh.
309 PowerState pwrStatePostRefresh;
312 * Track when we transitioned to the current power state
317 * Keep track of when a refresh is due.
324 Stats::Scalar actEnergy;
325 Stats::Scalar preEnergy;
326 Stats::Scalar readEnergy;
327 Stats::Scalar writeEnergy;
328 Stats::Scalar refreshEnergy;
331 * Active Background Energy
333 Stats::Scalar actBackEnergy;
336 * Precharge Background Energy
338 Stats::Scalar preBackEnergy;
341 * Active Power-Down Energy
343 Stats::Scalar actPowerDownEnergy;
346 * Precharge Power-Down Energy
348 Stats::Scalar prePowerDownEnergy;
351 * self Refresh Energy
353 Stats::Scalar selfRefreshEnergy;
355 Stats::Scalar totalEnergy;
356 Stats::Scalar averagePower;
359 * Stat to track total DRAM idle time
362 Stats::Scalar totalIdleTime;
365 * Track time spent in each power state.
367 Stats::Vector pwrStateTime;
370 * Function to update Power Stats
372 void updatePowerStats();
375 * Schedule a power state transition in the future, and
376 * potentially override an already scheduled transition.
378 * @param pwr_state Power state to transition to
379 * @param tick Tick when transition should take place
381 void schedulePowerEvent(PowerState pwr_state, Tick tick);
386 * Current power state.
391 * current refresh state
393 RefreshState refreshState;
396 * rank is in or transitioning to power-down or self-refresh
398 bool inLowPowerState;
406 * Track number of packets in read queue going to this rank
408 uint32_t readEntries;
411 * Track number of packets in write queue going to this rank
413 uint32_t writeEntries;
416 * Number of ACT, RD, and WR events currently scheduled
417 * Incremented when a refresh event is started as well
418 * Used to determine when a low-power state can be entered
420 uint8_t outstandingEvents;
423 * delay power-down and self-refresh exit until this requirement is met
425 Tick wakeUpAllowedAt;
428 * One DRAMPower instance per rank
433 * List of comamnds issued, to be sent to DRAMPpower at refresh
434 * and stats dump. Keep commands here since commands to different
435 * banks are added out of order. Will only pass commands up to
436 * curTick() to DRAMPower after sorting.
438 std::vector<Command> cmdList;
441 * Vector of Banks. Each rank is made of several devices which in
442 * term are made from several banks.
444 std::vector<Bank> banks;
447 * To track number of banks which are currently active for
450 unsigned int numBanksActive;
452 /** List to keep track of activate ticks */
453 std::deque<Tick> actTicks;
455 Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank);
457 const std::string name() const
459 return csprintf("%s_%d", memory.name(), rank);
463 * Kick off accounting for power and refresh states and
464 * schedule initial refresh.
466 * @param ref_tick Tick for first refresh
468 void startup(Tick ref_tick);
471 * Stop the refresh events.
476 * Check if there is no refresh and no preparation of refresh ongoing
477 * i.e. the refresh state machine is in idle
479 * @param Return true if the rank is idle from a refresh point of view
481 bool inRefIdleState() const { return refreshState == REF_IDLE; }
484 * Check if the current rank has all banks closed and is not
485 * in a low power state
487 * @param Return true if the rank is idle from a bank
488 * and power point of view
490 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
493 * Trigger a self-refresh exit if there are entries enqueued
494 * Exit if there are any read entries regardless of the bus state.
495 * If we are currently issuing write commands, exit if we have any
496 * write commands enqueued as well.
497 * Could expand this in the future to analyze state of entire queue
500 * @return boolean indicating self-refresh exit should be scheduled
502 bool forceSelfRefreshExit() const {
503 return (readEntries != 0) ||
504 ((memory.busStateNext == WRITE) && (writeEntries != 0));
508 * Check if the command queue of current rank is idle
510 * @param Return true if the there are no commands in Q.
511 * Bus direction determines queue checked.
513 bool isQueueEmpty() const;
516 * Let the rank check if it was waiting for requests to drain
517 * to allow it to transition states.
519 void checkDrainDone();
522 * Push command out of cmdList queue that are scheduled at
523 * or before curTick() to DRAMPower library
524 * All commands before curTick are guaranteed to be complete
525 * and can safely be flushed.
530 * Function to register Stats
535 * Computes stats just prior to dump event
540 * Reset stats on a stats event
545 * Schedule a transition to power-down (sleep)
547 * @param pwr_state Power state to transition to
548 * @param tick Absolute tick when transition should take place
550 void powerDownSleep(PowerState pwr_state, Tick tick);
553 * schedule and event to wake-up from power-down or self-refresh
554 * and update bank timing parameters
556 * @param exit_delay Relative tick defining the delay required between
557 * low-power exit and the next command
559 void scheduleWakeUpEvent(Tick exit_delay);
561 void processWriteDoneEvent();
562 EventFunctionWrapper writeDoneEvent;
564 void processActivateEvent();
565 EventFunctionWrapper activateEvent;
567 void processPrechargeEvent();
568 EventFunctionWrapper prechargeEvent;
570 void processRefreshEvent();
571 EventFunctionWrapper refreshEvent;
573 void processPowerEvent();
574 EventFunctionWrapper powerEvent;
576 void processWakeUpEvent();
577 EventFunctionWrapper wakeUpEvent;
582 * Define the process to compute stats on a stats dump event, e.g. on
583 * simulation exit or intermediate stats dump. This is defined per rank
584 * as the per rank stats are based on state transition and periodically
585 * updated, requiring re-sync at exit.
587 class RankDumpCallback : public Callback
591 RankDumpCallback(Rank *r) : ranks(r) {}
592 virtual void process() { ranks->computeStats(); };
595 /** Define a process to clear power lib counters on a stats reset */
596 class RankResetCallback : public Callback
599 /** Pointer to the rank, thus we instantiate per rank */
603 RankResetCallback(Rank *r) : rank(r) {}
604 virtual void process() { rank->resetStats(); };
607 /** Define a process to store the time on a stats reset */
608 class MemResetCallback : public Callback
611 /** A reference to the DRAMCtrl instance */
615 MemResetCallback(DRAMCtrl *_mem) : mem(_mem) {}
616 virtual void process() { mem->lastStatsResetTick = curTick(); };
620 * A burst helper helps organize and manage a packet that is larger than
621 * the DRAM burst size. A system packet that is larger than the burst size
622 * is split into multiple DRAM packets and all those DRAM packets point to
623 * a single burst helper such that we know when the whole packet is served.
629 /** Number of DRAM bursts requred for a system packet **/
630 const unsigned int burstCount;
632 /** Number of DRAM bursts serviced so far for a system packet **/
633 unsigned int burstsServiced;
635 BurstHelper(unsigned int _burstCount)
636 : burstCount(_burstCount), burstsServiced(0)
641 * A DRAM packet stores packets along with the timestamp of when
642 * the packet entered the queue, and also the decoded address.
648 /** When did request enter the controller */
649 const Tick entryTime;
651 /** When will request leave the controller */
654 /** This comes from the outside world */
659 /** Will be populated by address decoder */
665 * Bank id is calculated considering banks in all the ranks
666 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
667 * bankId = 8 --> rank1, bank0
669 const uint16_t bankId;
672 * The starting address of the DRAM packet.
673 * This address could be unaligned to burst size boundaries. The
674 * reason is to keep the address offset so we can accurately check
675 * incoming read packets with packets in the write queue.
680 * The size of this dram packet in bytes
681 * It is always equal or smaller than DRAM burst size
686 * A pointer to the BurstHelper if this DRAMPacket is a split packet
687 * If not a split packet (common case), this is set to NULL
689 BurstHelper* burstHelper;
693 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
694 uint32_t _row, uint16_t bank_id, Addr _addr,
695 unsigned int _size, Bank& bank_ref, Rank& rank_ref)
696 : entryTime(curTick()), readyTime(curTick()),
697 pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
698 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
699 bankRef(bank_ref), rankRef(rank_ref)
705 * Bunch of things requires to setup "events" in gem5
706 * When event "respondEvent" occurs for example, the method
707 * processRespondEvent is called; no parameters are allowed
710 void processNextReqEvent();
711 EventFunctionWrapper nextReqEvent;
713 void processRespondEvent();
714 EventFunctionWrapper respondEvent;
717 * Check if the read queue has room for more entries
719 * @param pktCount The number of entries needed in the read queue
720 * @return true if read queue is full, false otherwise
722 bool readQueueFull(unsigned int pktCount) const;
725 * Check if the write queue has room for more entries
727 * @param pktCount The number of entries needed in the write queue
728 * @return true if write queue is full, false otherwise
730 bool writeQueueFull(unsigned int pktCount) const;
733 * When a new read comes in, first check if the write q has a
734 * pending request to the same address.\ If not, decode the
735 * address to populate rank/bank/row, create one or mutliple
736 * "dram_pkt", and push them to the back of the read queue.\
737 * If this is the only
738 * read request in the system, schedule an event to start
741 * @param pkt The request packet from the outside world
742 * @param pktCount The number of DRAM bursts the pkt
743 * translate to. If pkt size is larger then one full burst,
744 * then pktCount is greater than one.
746 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
749 * Decode the incoming pkt, create a dram_pkt and push to the
750 * back of the write queue. \If the write q length is more than
751 * the threshold specified by the user, ie the queue is beginning
752 * to get full, stop reads, and start draining writes.
754 * @param pkt The request packet from the outside world
755 * @param pktCount The number of DRAM bursts the pkt
756 * translate to. If pkt size is larger then one full burst,
757 * then pktCount is greater than one.
759 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
762 * Actually do the DRAM access - figure out the latency it
763 * will take to service the req based on bank state, channel state etc
764 * and then update those states to account for this request.\ Based
765 * on this, update the packet's "readyTime" and move it to the
766 * response q from where it will eventually go back to the outside
769 * @param pkt The DRAM packet created from the outside world pkt
771 void doDRAMAccess(DRAMPacket* dram_pkt);
774 * When a packet reaches its "readyTime" in the response Q,
775 * use the "access()" method in AbstractMemory to actually
776 * create the response packet, and send it back to the outside
779 * @param pkt The packet from the outside world
780 * @param static_latency Static latency to add before sending the packet
782 void accessAndRespond(PacketPtr pkt, Tick static_latency);
785 * Address decoder to figure out physical mapping onto ranks,
786 * banks, and rows. This function is called multiple times on the same
787 * system packet if the pakcet is larger than burst of the memory. The
788 * dramPktAddr is used for the offset within the packet.
790 * @param pkt The packet from the outside world
791 * @param dramPktAddr The starting address of the DRAM packet
792 * @param size The size of the DRAM packet in bytes
793 * @param isRead Is the request for a read or a write to DRAM
794 * @return A DRAMPacket pointer with the decoded information
796 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
800 * The memory schduler/arbiter - picks which request needs to
801 * go next, based on the specified policy such as FCFS or FR-FCFS
802 * and moves it to the head of the queue.
803 * Prioritizes accesses to the same rank as previous burst unless
804 * controller is switching command type.
806 * @param queue Queued requests to consider
807 * @param extra_col_delay Any extra delay due to a read/write switch
808 * @return true if a packet is scheduled to a rank which is available else
811 bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
814 * For FR-FCFS policy reorder the read/write queue depending on row buffer
815 * hits and earliest bursts available in DRAM
817 * @param queue Queued requests to consider
818 * @param extra_col_delay Any extra delay due to a read/write switch
819 * @return true if a packet is scheduled to a rank which is available else
822 bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
825 * Find which are the earliest banks ready to issue an activate
826 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
827 * Also checks if the bank is already prepped.
829 * @param queue Queued requests to consider
830 * @param time of seamless burst command
831 * @return One-hot encoded mask of bank indices
832 * @return boolean indicating burst can issue seamlessly, with no gaps
834 std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue,
835 Tick min_col_at) const;
838 * Keep track of when row activations happen, in order to enforce
839 * the maximum number of activations in the activation window. The
840 * method updates the time that the banks become available based
841 * on the current limits.
843 * @param rank_ref Reference to the rank
844 * @param bank_ref Reference to the bank
845 * @param act_tick Time when the activation takes place
846 * @param row Index of the row
848 void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
852 * Precharge a given bank and also update when the precharge is
853 * done. This will also deal with any stats related to the
854 * accesses to the open page.
856 * @param rank_ref The rank to precharge
857 * @param bank_ref The bank to precharge
858 * @param pre_at Time when the precharge takes place
859 * @param trace Is this an auto precharge then do not add to trace
861 void prechargeBank(Rank& rank_ref, Bank& bank_ref,
862 Tick pre_at, bool trace = true);
865 * Used for debugging to observe the contents of the queues.
867 void printQs() const;
870 * Burst-align an address.
872 * @param addr The potentially unaligned address
874 * @return An address aligned to a DRAM burst
876 Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
879 * The controller's main read and write queues
881 std::deque<DRAMPacket*> readQueue;
882 std::deque<DRAMPacket*> writeQueue;
885 * To avoid iterating over the write queue to check for
886 * overlapping transactions, maintain a set of burst addresses
887 * that are currently queued. Since we merge writes to the same
888 * location we never have more than one address to the same burst
891 std::unordered_set<Addr> isInWriteQueue;
894 * Response queue where read packets wait after we're done working
895 * with them, but it's not time to send the response yet. The
896 * responses are stored seperately mostly to keep the code clean
897 * and help with events scheduling. For all logical purposes such
898 * as sizing the read queue, this and the main read queue need to
901 std::deque<DRAMPacket*> respQueue;
906 std::vector<Rank*> ranks;
909 * The following are basic design parameters of the memory
910 * controller, and are initialized based on parameter values.
911 * The rowsPerBank is determined based on the capacity, number of
912 * ranks and banks, the burst size, and the row buffer size.
914 const uint32_t deviceSize;
915 const uint32_t deviceBusWidth;
916 const uint32_t burstLength;
917 const uint32_t deviceRowBufferSize;
918 const uint32_t devicesPerRank;
919 const uint32_t burstSize;
920 const uint32_t rowBufferSize;
921 const uint32_t columnsPerRowBuffer;
922 const uint32_t columnsPerStripe;
923 const uint32_t ranksPerChannel;
924 const uint32_t bankGroupsPerRank;
925 const bool bankGroupArch;
926 const uint32_t banksPerRank;
927 const uint32_t channels;
928 uint32_t rowsPerBank;
929 const uint32_t readBufferSize;
930 const uint32_t writeBufferSize;
931 const uint32_t writeHighThreshold;
932 const uint32_t writeLowThreshold;
933 const uint32_t minWritesPerSwitch;
934 uint32_t writesThisTime;
935 uint32_t readsThisTime;
938 * Basic memory timing parameters initialized based on parameter
941 const Tick M5_CLASS_VAR_USED tCK;
960 const uint32_t activationLimit;
963 * Memory controller configuration initialized based on parameter
966 Enums::MemSched memSchedPolicy;
967 Enums::AddrMap addrMapping;
968 Enums::PageManage pageMgmt;
971 * Max column accesses (read and write) per row, before forefully
974 const uint32_t maxAccessesPerRow;
977 * Pipeline latency of the controller frontend. The frontend
978 * contribution is added to writes (that complete when they are in
979 * the write buffer) and reads that are serviced the write buffer.
981 const Tick frontendLatency;
984 * Pipeline latency of the backend and PHY. Along with the
985 * frontend contribution, this latency is added to reads serviced
988 const Tick backendLatency;
991 * Till when has the main data bus been spoken for already?
998 * The soonest you have to start thinking about the next request
999 * is the longest access time that can occur before
1000 * busBusyUntil. Assuming you need to precharge, open a new row,
1001 * and access, it is tRP + tRCD + tCL.
1005 // All statistics that the model needs to capture
1006 Stats::Scalar readReqs;
1007 Stats::Scalar writeReqs;
1008 Stats::Scalar readBursts;
1009 Stats::Scalar writeBursts;
1010 Stats::Scalar bytesReadDRAM;
1011 Stats::Scalar bytesReadWrQ;
1012 Stats::Scalar bytesWritten;
1013 Stats::Scalar bytesReadSys;
1014 Stats::Scalar bytesWrittenSys;
1015 Stats::Scalar servicedByWrQ;
1016 Stats::Scalar mergedWrBursts;
1017 Stats::Scalar neitherReadNorWrite;
1018 Stats::Vector perBankRdBursts;
1019 Stats::Vector perBankWrBursts;
1020 Stats::Scalar numRdRetry;
1021 Stats::Scalar numWrRetry;
1022 Stats::Scalar totGap;
1023 Stats::Vector readPktSize;
1024 Stats::Vector writePktSize;
1025 Stats::Vector rdQLenPdf;
1026 Stats::Vector wrQLenPdf;
1027 Stats::Histogram bytesPerActivate;
1028 Stats::Histogram rdPerTurnAround;
1029 Stats::Histogram wrPerTurnAround;
1031 // Latencies summed over all requests
1032 Stats::Scalar totQLat;
1033 Stats::Scalar totMemAccLat;
1034 Stats::Scalar totBusLat;
1036 // Average latencies per request
1037 Stats::Formula avgQLat;
1038 Stats::Formula avgBusLat;
1039 Stats::Formula avgMemAccLat;
1041 // Average bandwidth
1042 Stats::Formula avgRdBW;
1043 Stats::Formula avgWrBW;
1044 Stats::Formula avgRdBWSys;
1045 Stats::Formula avgWrBWSys;
1046 Stats::Formula peakBW;
1047 Stats::Formula busUtil;
1048 Stats::Formula busUtilRead;
1049 Stats::Formula busUtilWrite;
1051 // Average queue lengths
1052 Stats::Average avgRdQLen;
1053 Stats::Average avgWrQLen;
1055 // Row hit count and rate
1056 Stats::Scalar readRowHits;
1057 Stats::Scalar writeRowHits;
1058 Stats::Formula readRowHitRate;
1059 Stats::Formula writeRowHitRate;
1060 Stats::Formula avgGap;
1062 // DRAM Power Calculation
1063 Stats::Formula pageHitRate;
1065 // Holds the value of the rank of burst issued
1069 uint64_t timeStampOffset;
1071 /** The time when stats were last reset used to calculate average power */
1072 Tick lastStatsResetTick;
1075 * Upstream caches need this packet until true is returned, so
1076 * hold it for deletion until a subsequent call
1078 std::unique_ptr<Packet> pendingDelete;
1081 * This function increments the energy when called. If stats are
1082 * dumped periodically, note accumulated energy values will
1083 * appear in the stats (even if the stats are reset). This is a
1084 * result of the energy values coming from DRAMPower, and there
1085 * is currently no support for resetting the state.
1087 * @param rank Currrent rank
1089 void updatePowerStats(Rank& rank_ref);
1092 * Function for sorting Command structures based on timeStamp
1094 * @param a Memory Command
1095 * @param next Memory Command
1096 * @return true if timeStamp of Command 1 < timeStamp of Command 2
1098 static bool sortTime(const Command& cmd, const Command& cmd_next) {
1099 return cmd.timeStamp < cmd_next.timeStamp;
1104 void regStats() override;
1106 DRAMCtrl(const DRAMCtrlParams* p);
1108 DrainState drain() override;
1110 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
1111 PortID idx = InvalidPortID) override;
1113 virtual void init() override;
1114 virtual void startup() override;
1115 virtual void drainResume() override;
1118 * Return true once refresh is complete for all ranks and there are no
1119 * additional commands enqueued. (only evaluated when draining)
1120 * This will ensure that all banks are closed, power state is IDLE, and
1121 * power stats have been updated
1123 * @return true if all ranks have refreshed, with no commands enqueued
1126 bool allRanksDrained() const;
1130 Tick recvAtomic(PacketPtr pkt);
1131 void recvFunctional(PacketPtr pkt);
1132 bool recvTimingReq(PacketPtr pkt);
1136 #endif //__MEM_DRAM_CTRL_HH__