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14 * Copyright (c) 2013 Amin Farmahini-Farahani
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18 * modification, are permitted provided that the following conditions are
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40 * Authors: Andreas Hansson
49 * DRAMCtrl declaration
52 #ifndef __MEM_DRAM_CTRL_HH__
53 #define __MEM_DRAM_CTRL_HH__
57 #include <unordered_set>
59 #include "base/callback.hh"
60 #include "base/statistics.hh"
61 #include "enums/AddrMap.hh"
62 #include "enums/MemSched.hh"
63 #include "enums/PageManage.hh"
64 #include "mem/abstract_mem.hh"
65 #include "mem/qport.hh"
66 #include "params/DRAMCtrl.hh"
67 #include "sim/eventq.hh"
68 #include "mem/drampower.hh"
71 * The DRAM controller is a single-channel memory controller capturing
72 * the most important timing constraints associated with a
73 * contemporary DRAM. For multi-channel memory systems, the controller
74 * is combined with a crossbar model, with the channel address
75 * interleaving taking part in the crossbar.
77 * As a basic design principle, this controller
78 * model is not cycle callable, but instead uses events to: 1) decide
79 * when new decisions can be made, 2) when resources become available,
80 * 3) when things are to be considered done, and 4) when to send
81 * things back. Through these simple principles, the model delivers
82 * high performance, and lots of flexibility, allowing users to
83 * evaluate the system impact of a wide range of memory technologies,
84 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
86 * For more details, please see Hansson et al, "Simulating DRAM
87 * controllers for future system architecture exploration",
88 * Proc. ISPASS, 2014. If you use this model as part of your research
89 * please cite the paper.
91 class DRAMCtrl : public AbstractMemory
96 // For now, make use of a queued slave port to avoid dealing with
97 // flow control for the responses being sent back
98 class MemoryPort : public QueuedSlavePort
101 RespPacketQueue queue;
106 MemoryPort(const std::string& name, DRAMCtrl& _memory);
110 Tick recvAtomic(PacketPtr pkt);
112 void recvFunctional(PacketPtr pkt);
114 bool recvTimingReq(PacketPtr);
116 virtual AddrRangeList getAddrRanges() const;
121 * Our incoming port, for a multi-ported controller add a crossbar
127 * Remeber if the memory system is in timing mode
132 * Remember if we have to retry a request when available.
138 * Bus state used to control the read/write switching and drive
139 * the scheduling of the next request.
151 * Simple structure to hold the values needed to keep track of
152 * commands for DRAMPower
155 Data::MemCommand::cmds type;
159 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
161 : type(_type), bank(_bank), timeStamp(time_stamp)
166 * A basic class to track the bank state, i.e. what row is
167 * currently open (if any), when is the bank free to accept a new
168 * column (read/write) command, when can it be precharged, and
169 * when can it be activated.
171 * The bank also keeps track of how many bytes have been accessed
172 * in the open row since it was opened.
179 static const uint32_t NO_ROW = -1;
189 uint32_t rowAccesses;
190 uint32_t bytesAccessed;
193 openRow(NO_ROW), bank(0), bankgr(0),
194 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
195 rowAccesses(0), bytesAccessed(0)
201 * Rank class includes a vector of banks. Refresh and Power state
202 * machines are defined per rank. Events required to change the
203 * state of the refresh and power state machine are scheduled per
204 * rank. This class allows the implementation of rank-wise refresh
205 * and rank-wise power-down.
207 class Rank : public EventManager
213 * The power state captures the different operational states of
214 * the DRAM and interacts with the bus read/write state machine,
215 * and the refresh state machine. In the idle state all banks are
216 * precharged. From there we either go to an auto refresh (as
217 * determined by the refresh state machine), or to a precharge
218 * power down mode. From idle the memory can also go to the active
219 * state (with one or more banks active), and in turn from there
220 * to active power down. At the moment we do not capture the deep
221 * power down and self-refresh state.
232 * The refresh state is used to control the progress of the
233 * refresh scheduling. When normal operation is in progress the
234 * refresh state is idle. From there, it progresses to the refresh
235 * drain state once tREFI has passed. The refresh drain state
236 * captures the DRAM row active state, as it will stay there until
237 * all ongoing accesses complete. Thereafter all banks are
238 * precharged, and lastly, the DRAM is refreshed.
248 * A reference to the parent DRAMCtrl instance
253 * Since we are taking decisions out of order, we need to keep
254 * track of what power transition is happening at what time, such
255 * that we can go back in time and change history. For example, if
256 * we precharge all banks and schedule going to the idle state, we
257 * might at a later point decide to activate a bank before the
258 * transition to idle would have taken place.
260 PowerState pwrStateTrans;
263 * Current power state.
268 * Track when we transitioned to the current power state
273 * current refresh state
275 RefreshState refreshState;
278 * Keep track of when a refresh is due.
285 Stats::Scalar actEnergy;
286 Stats::Scalar preEnergy;
287 Stats::Scalar readEnergy;
288 Stats::Scalar writeEnergy;
289 Stats::Scalar refreshEnergy;
292 * Active Background Energy
294 Stats::Scalar actBackEnergy;
297 * Precharge Background Energy
299 Stats::Scalar preBackEnergy;
301 Stats::Scalar totalEnergy;
302 Stats::Scalar averagePower;
305 * Track time spent in each power state.
307 Stats::Vector pwrStateTime;
310 * Function to update Power Stats
312 void updatePowerStats();
315 * Schedule a power state transition in the future, and
316 * potentially override an already scheduled transition.
318 * @param pwr_state Power state to transition to
319 * @param tick Tick when transition should take place
321 void schedulePowerEvent(PowerState pwr_state, Tick tick);
331 * One DRAMPower instance per rank
336 * List of comamnds issued, to be sent to DRAMPpower at refresh
337 * and stats dump. Keep commands here since commands to different
338 * banks are added out of order. Will only pass commands up to
339 * curTick() to DRAMPower after sorting.
341 std::vector<Command> cmdList;
344 * Vector of Banks. Each rank is made of several devices which in
345 * term are made from several banks.
347 std::vector<Bank> banks;
350 * To track number of banks which are currently active for
353 unsigned int numBanksActive;
355 /** List to keep track of activate ticks */
356 std::deque<Tick> actTicks;
358 Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p);
360 const std::string name() const
362 return csprintf("%s_%d", memory.name(), rank);
366 * Kick off accounting for power and refresh states and
367 * schedule initial refresh.
369 * @param ref_tick Tick for first refresh
371 void startup(Tick ref_tick);
374 * Stop the refresh events.
379 * Check if the current rank is available for scheduling.
381 * @param Return true if the rank is idle from a refresh point of view
383 bool isAvailable() const { return refreshState == REF_IDLE; }
386 * Check if the current rank has all banks closed and is not
387 * in a low power state
389 * @param Return true if the rank is idle from a bank
390 * and power point of view
392 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
395 * Let the rank check if it was waiting for requests to drain
396 * to allow it to transition states.
398 void checkDrainDone();
401 * Push command out of cmdList queue that are scheduled at
402 * or before curTick() to DRAMPower library
403 * All commands before curTick are guaranteed to be complete
404 * and can safely be flushed.
409 * Function to register Stats
414 * Computes stats just prior to dump event
418 void processActivateEvent();
419 EventWrapper<Rank, &Rank::processActivateEvent>
422 void processPrechargeEvent();
423 EventWrapper<Rank, &Rank::processPrechargeEvent>
426 void processRefreshEvent();
427 EventWrapper<Rank, &Rank::processRefreshEvent>
430 void processPowerEvent();
431 EventWrapper<Rank, &Rank::processPowerEvent>
436 // define the process to compute stats on simulation exit
437 // defined per rank as the per rank stats are based on state
438 // transition and periodically updated, requiring re-sync at
440 class RankDumpCallback : public Callback
444 RankDumpCallback(Rank *r) : ranks(r) {}
445 virtual void process() { ranks->computeStats(); };
449 * A burst helper helps organize and manage a packet that is larger than
450 * the DRAM burst size. A system packet that is larger than the burst size
451 * is split into multiple DRAM packets and all those DRAM packets point to
452 * a single burst helper such that we know when the whole packet is served.
458 /** Number of DRAM bursts requred for a system packet **/
459 const unsigned int burstCount;
461 /** Number of DRAM bursts serviced so far for a system packet **/
462 unsigned int burstsServiced;
464 BurstHelper(unsigned int _burstCount)
465 : burstCount(_burstCount), burstsServiced(0)
470 * A DRAM packet stores packets along with the timestamp of when
471 * the packet entered the queue, and also the decoded address.
477 /** When did request enter the controller */
478 const Tick entryTime;
480 /** When will request leave the controller */
483 /** This comes from the outside world */
488 /** Will be populated by address decoder */
494 * Bank id is calculated considering banks in all the ranks
495 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
496 * bankId = 8 --> rank1, bank0
498 const uint16_t bankId;
501 * The starting address of the DRAM packet.
502 * This address could be unaligned to burst size boundaries. The
503 * reason is to keep the address offset so we can accurately check
504 * incoming read packets with packets in the write queue.
509 * The size of this dram packet in bytes
510 * It is always equal or smaller than DRAM burst size
515 * A pointer to the BurstHelper if this DRAMPacket is a split packet
516 * If not a split packet (common case), this is set to NULL
518 BurstHelper* burstHelper;
522 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
523 uint32_t _row, uint16_t bank_id, Addr _addr,
524 unsigned int _size, Bank& bank_ref, Rank& rank_ref)
525 : entryTime(curTick()), readyTime(curTick()),
526 pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
527 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
528 bankRef(bank_ref), rankRef(rank_ref)
534 * Bunch of things requires to setup "events" in gem5
535 * When event "respondEvent" occurs for example, the method
536 * processRespondEvent is called; no parameters are allowed
539 void processNextReqEvent();
540 EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
542 void processRespondEvent();
543 EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
546 * Check if the read queue has room for more entries
548 * @param pktCount The number of entries needed in the read queue
549 * @return true if read queue is full, false otherwise
551 bool readQueueFull(unsigned int pktCount) const;
554 * Check if the write queue has room for more entries
556 * @param pktCount The number of entries needed in the write queue
557 * @return true if write queue is full, false otherwise
559 bool writeQueueFull(unsigned int pktCount) const;
562 * When a new read comes in, first check if the write q has a
563 * pending request to the same address.\ If not, decode the
564 * address to populate rank/bank/row, create one or mutliple
565 * "dram_pkt", and push them to the back of the read queue.\
566 * If this is the only
567 * read request in the system, schedule an event to start
570 * @param pkt The request packet from the outside world
571 * @param pktCount The number of DRAM bursts the pkt
572 * translate to. If pkt size is larger then one full burst,
573 * then pktCount is greater than one.
575 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
578 * Decode the incoming pkt, create a dram_pkt and push to the
579 * back of the write queue. \If the write q length is more than
580 * the threshold specified by the user, ie the queue is beginning
581 * to get full, stop reads, and start draining writes.
583 * @param pkt The request packet from the outside world
584 * @param pktCount The number of DRAM bursts the pkt
585 * translate to. If pkt size is larger then one full burst,
586 * then pktCount is greater than one.
588 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
591 * Actually do the DRAM access - figure out the latency it
592 * will take to service the req based on bank state, channel state etc
593 * and then update those states to account for this request.\ Based
594 * on this, update the packet's "readyTime" and move it to the
595 * response q from where it will eventually go back to the outside
598 * @param pkt The DRAM packet created from the outside world pkt
600 void doDRAMAccess(DRAMPacket* dram_pkt);
603 * When a packet reaches its "readyTime" in the response Q,
604 * use the "access()" method in AbstractMemory to actually
605 * create the response packet, and send it back to the outside
608 * @param pkt The packet from the outside world
609 * @param static_latency Static latency to add before sending the packet
611 void accessAndRespond(PacketPtr pkt, Tick static_latency);
614 * Address decoder to figure out physical mapping onto ranks,
615 * banks, and rows. This function is called multiple times on the same
616 * system packet if the pakcet is larger than burst of the memory. The
617 * dramPktAddr is used for the offset within the packet.
619 * @param pkt The packet from the outside world
620 * @param dramPktAddr The starting address of the DRAM packet
621 * @param size The size of the DRAM packet in bytes
622 * @param isRead Is the request for a read or a write to DRAM
623 * @return A DRAMPacket pointer with the decoded information
625 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
629 * The memory schduler/arbiter - picks which request needs to
630 * go next, based on the specified policy such as FCFS or FR-FCFS
631 * and moves it to the head of the queue.
632 * Prioritizes accesses to the same rank as previous burst unless
633 * controller is switching command type.
635 * @param queue Queued requests to consider
636 * @param extra_col_delay Any extra delay due to a read/write switch
637 * @return true if a packet is scheduled to a rank which is available else
640 bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
643 * For FR-FCFS policy reorder the read/write queue depending on row buffer
644 * hits and earliest bursts available in DRAM
646 * @param queue Queued requests to consider
647 * @param extra_col_delay Any extra delay due to a read/write switch
648 * @return true if a packet is scheduled to a rank which is available else
651 bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
654 * Find which are the earliest banks ready to issue an activate
655 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
656 * Also checks if the bank is already prepped.
658 * @param queue Queued requests to consider
659 * @param time of seamless burst command
660 * @return One-hot encoded mask of bank indices
661 * @return boolean indicating burst can issue seamlessly, with no gaps
663 std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue,
664 Tick min_col_at) const;
667 * Keep track of when row activations happen, in order to enforce
668 * the maximum number of activations in the activation window. The
669 * method updates the time that the banks become available based
670 * on the current limits.
672 * @param rank_ref Reference to the rank
673 * @param bank_ref Reference to the bank
674 * @param act_tick Time when the activation takes place
675 * @param row Index of the row
677 void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
681 * Precharge a given bank and also update when the precharge is
682 * done. This will also deal with any stats related to the
683 * accesses to the open page.
685 * @param rank_ref The rank to precharge
686 * @param bank_ref The bank to precharge
687 * @param pre_at Time when the precharge takes place
688 * @param trace Is this an auto precharge then do not add to trace
690 void prechargeBank(Rank& rank_ref, Bank& bank_ref,
691 Tick pre_at, bool trace = true);
694 * Used for debugging to observe the contents of the queues.
696 void printQs() const;
699 * Burst-align an address.
701 * @param addr The potentially unaligned address
703 * @return An address aligned to a DRAM burst
705 Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
708 * The controller's main read and write queues
710 std::deque<DRAMPacket*> readQueue;
711 std::deque<DRAMPacket*> writeQueue;
714 * To avoid iterating over the write queue to check for
715 * overlapping transactions, maintain a set of burst addresses
716 * that are currently queued. Since we merge writes to the same
717 * location we never have more than one address to the same burst
720 std::unordered_set<Addr> isInWriteQueue;
723 * Response queue where read packets wait after we're done working
724 * with them, but it's not time to send the response yet. The
725 * responses are stored seperately mostly to keep the code clean
726 * and help with events scheduling. For all logical purposes such
727 * as sizing the read queue, this and the main read queue need to
730 std::deque<DRAMPacket*> respQueue;
735 std::vector<Rank*> ranks;
738 * The following are basic design parameters of the memory
739 * controller, and are initialized based on parameter values.
740 * The rowsPerBank is determined based on the capacity, number of
741 * ranks and banks, the burst size, and the row buffer size.
743 const uint32_t deviceSize;
744 const uint32_t deviceBusWidth;
745 const uint32_t burstLength;
746 const uint32_t deviceRowBufferSize;
747 const uint32_t devicesPerRank;
748 const uint32_t burstSize;
749 const uint32_t rowBufferSize;
750 const uint32_t columnsPerRowBuffer;
751 const uint32_t columnsPerStripe;
752 const uint32_t ranksPerChannel;
753 const uint32_t bankGroupsPerRank;
754 const bool bankGroupArch;
755 const uint32_t banksPerRank;
756 const uint32_t channels;
757 uint32_t rowsPerBank;
758 const uint32_t readBufferSize;
759 const uint32_t writeBufferSize;
760 const uint32_t writeHighThreshold;
761 const uint32_t writeLowThreshold;
762 const uint32_t minWritesPerSwitch;
763 uint32_t writesThisTime;
764 uint32_t readsThisTime;
767 * Basic memory timing parameters initialized based on parameter
770 const Tick M5_CLASS_VAR_USED tCK;
789 const uint32_t activationLimit;
792 * Memory controller configuration initialized based on parameter
795 Enums::MemSched memSchedPolicy;
796 Enums::AddrMap addrMapping;
797 Enums::PageManage pageMgmt;
800 * Max column accesses (read and write) per row, before forefully
803 const uint32_t maxAccessesPerRow;
806 * Pipeline latency of the controller frontend. The frontend
807 * contribution is added to writes (that complete when they are in
808 * the write buffer) and reads that are serviced the write buffer.
810 const Tick frontendLatency;
813 * Pipeline latency of the backend and PHY. Along with the
814 * frontend contribution, this latency is added to reads serviced
817 const Tick backendLatency;
820 * Till when has the main data bus been spoken for already?
827 * The soonest you have to start thinking about the next request
828 * is the longest access time that can occur before
829 * busBusyUntil. Assuming you need to precharge, open a new row,
830 * and access, it is tRP + tRCD + tCL.
834 // All statistics that the model needs to capture
835 Stats::Scalar readReqs;
836 Stats::Scalar writeReqs;
837 Stats::Scalar readBursts;
838 Stats::Scalar writeBursts;
839 Stats::Scalar bytesReadDRAM;
840 Stats::Scalar bytesReadWrQ;
841 Stats::Scalar bytesWritten;
842 Stats::Scalar bytesReadSys;
843 Stats::Scalar bytesWrittenSys;
844 Stats::Scalar servicedByWrQ;
845 Stats::Scalar mergedWrBursts;
846 Stats::Scalar neitherReadNorWrite;
847 Stats::Vector perBankRdBursts;
848 Stats::Vector perBankWrBursts;
849 Stats::Scalar numRdRetry;
850 Stats::Scalar numWrRetry;
851 Stats::Scalar totGap;
852 Stats::Vector readPktSize;
853 Stats::Vector writePktSize;
854 Stats::Vector rdQLenPdf;
855 Stats::Vector wrQLenPdf;
856 Stats::Histogram bytesPerActivate;
857 Stats::Histogram rdPerTurnAround;
858 Stats::Histogram wrPerTurnAround;
860 // Latencies summed over all requests
861 Stats::Scalar totQLat;
862 Stats::Scalar totMemAccLat;
863 Stats::Scalar totBusLat;
865 // Average latencies per request
866 Stats::Formula avgQLat;
867 Stats::Formula avgBusLat;
868 Stats::Formula avgMemAccLat;
871 Stats::Formula avgRdBW;
872 Stats::Formula avgWrBW;
873 Stats::Formula avgRdBWSys;
874 Stats::Formula avgWrBWSys;
875 Stats::Formula peakBW;
876 Stats::Formula busUtil;
877 Stats::Formula busUtilRead;
878 Stats::Formula busUtilWrite;
880 // Average queue lengths
881 Stats::Average avgRdQLen;
882 Stats::Average avgWrQLen;
884 // Row hit count and rate
885 Stats::Scalar readRowHits;
886 Stats::Scalar writeRowHits;
887 Stats::Formula readRowHitRate;
888 Stats::Formula writeRowHitRate;
889 Stats::Formula avgGap;
891 // DRAM Power Calculation
892 Stats::Formula pageHitRate;
894 // Holds the value of the rank of burst issued
898 uint64_t timeStampOffset;
901 * Upstream caches need this packet until true is returned, so
902 * hold it for deletion until a subsequent call
904 std::unique_ptr<Packet> pendingDelete;
907 * This function increments the energy when called. If stats are
908 * dumped periodically, note accumulated energy values will
909 * appear in the stats (even if the stats are reset). This is a
910 * result of the energy values coming from DRAMPower, and there
911 * is currently no support for resetting the state.
913 * @param rank Currrent rank
915 void updatePowerStats(Rank& rank_ref);
918 * Function for sorting Command structures based on timeStamp
920 * @param a Memory Command
921 * @param next Memory Command
922 * @return true if timeStamp of Command 1 < timeStamp of Command 2
924 static bool sortTime(const Command& cmd, const Command& cmd_next) {
925 return cmd.timeStamp < cmd_next.timeStamp;
930 void regStats() override;
932 DRAMCtrl(const DRAMCtrlParams* p);
934 DrainState drain() override;
936 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
937 PortID idx = InvalidPortID) override;
939 virtual void init() override;
940 virtual void startup() override;
941 virtual void drainResume() override;
944 * Return true once refresh is complete for all ranks and there are no
945 * additional commands enqueued. (only evaluated when draining)
946 * This will ensure that all banks are closed, power state is IDLE, and
947 * power stats have been updated
949 * @return true if all ranks have refreshed, with no commands enqueued
952 bool allRanksDrained() const;
956 Tick recvAtomic(PacketPtr pkt);
957 void recvFunctional(PacketPtr pkt);
958 bool recvTimingReq(PacketPtr pkt);
962 #endif //__MEM_DRAM_CTRL_HH__