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40 #include "mem/drampower.hh"
42 #include "base/intmath.hh"
43 #include "sim/core.hh"
45 DRAMPower::DRAMPower(const DRAMCtrlParams
* p
, bool include_io
) :
46 powerlib(libDRAMPower(getMemSpec(p
), include_io
))
50 Data::MemArchitectureSpec
51 DRAMPower::getArchParams(const DRAMCtrlParams
* p
)
53 Data::MemArchitectureSpec archSpec
;
54 archSpec
.burstLength
= p
->burst_length
;
55 archSpec
.nbrOfBanks
= p
->banks_per_rank
;
56 // One DRAMPower instance per rank, hence set this to 1
57 archSpec
.nbrOfRanks
= 1;
58 archSpec
.dataRate
= getDataRate(p
);
59 // For now we can ignore the number of columns and rows as they
60 // are not used in the power calculation.
61 archSpec
.nbrOfColumns
= 0;
62 archSpec
.nbrOfRows
= 0;
63 archSpec
.width
= p
->device_bus_width
;
64 archSpec
.nbrOfBankGroups
= p
->bank_groups_per_rank
;
65 archSpec
.dll
= p
->dll
;
66 archSpec
.twoVoltageDomains
= hasTwoVDD(p
);
67 // Keep this disabled for now until the model is firmed up.
68 archSpec
.termination
= false;
73 DRAMPower::getTimingParams(const DRAMCtrlParams
* p
)
75 // Set the values that are used for power calculations and ignore
76 // the ones only used by the controller functionality in DRAMPower
78 // All DRAMPower timings are in clock cycles
79 Data::MemTimingSpec timingSpec
;
80 timingSpec
.RC
= divCeil((p
->tRAS
+ p
->tRP
), p
->tCK
);
81 timingSpec
.RCD
= divCeil(p
->tRCD
, p
->tCK
);
82 timingSpec
.RL
= divCeil(p
->tCL
, p
->tCK
);
83 timingSpec
.RP
= divCeil(p
->tRP
, p
->tCK
);
84 timingSpec
.RFC
= divCeil(p
->tRFC
, p
->tCK
);
85 timingSpec
.RAS
= divCeil(p
->tRAS
, p
->tCK
);
86 // Write latency is read latency - 1 cycle
87 // Source: B.Jacob Memory Systems Cache, DRAM, Disk
88 timingSpec
.WL
= timingSpec
.RL
- 1;
89 timingSpec
.DQSCK
= 0; // ignore for now
90 timingSpec
.RTP
= divCeil(p
->tRTP
, p
->tCK
);
91 timingSpec
.WR
= divCeil(p
->tWR
, p
->tCK
);
92 timingSpec
.XP
= divCeil(p
->tXP
, p
->tCK
);
93 timingSpec
.XPDLL
= divCeil(p
->tXPDLL
, p
->tCK
);
94 timingSpec
.XS
= divCeil(p
->tXS
, p
->tCK
);
95 timingSpec
.XSDLL
= divCeil(p
->tXSDLL
, p
->tCK
);
98 timingSpec
.clkPeriod
= (p
->tCK
/ (double)(SimClock::Int::ns
));
99 assert(timingSpec
.clkPeriod
!= 0);
100 timingSpec
.clkMhz
= (1 / timingSpec
.clkPeriod
) * 1000;
105 DRAMPower::getPowerParams(const DRAMCtrlParams
* p
)
107 // All DRAMPower currents are in mA
108 Data::MemPowerSpec powerSpec
;
109 powerSpec
.idd0
= p
->IDD0
* 1000;
110 powerSpec
.idd02
= p
->IDD02
* 1000;
111 powerSpec
.idd2p0
= p
->IDD2P0
* 1000;
112 powerSpec
.idd2p02
= p
->IDD2P02
* 1000;
113 powerSpec
.idd2p1
= p
->IDD2P1
* 1000;
114 powerSpec
.idd2p12
= p
->IDD2P12
* 1000;
115 powerSpec
.idd2n
= p
->IDD2N
* 1000;
116 powerSpec
.idd2n2
= p
->IDD2N2
* 1000;
117 powerSpec
.idd3p0
= p
->IDD3P0
* 1000;
118 powerSpec
.idd3p02
= p
->IDD3P02
* 1000;
119 powerSpec
.idd3p1
= p
->IDD3P1
* 1000;
120 powerSpec
.idd3p12
= p
->IDD3P12
* 1000;
121 powerSpec
.idd3n
= p
->IDD3N
* 1000;
122 powerSpec
.idd3n2
= p
->IDD3N2
* 1000;
123 powerSpec
.idd4r
= p
->IDD4R
* 1000;
124 powerSpec
.idd4r2
= p
->IDD4R2
* 1000;
125 powerSpec
.idd4w
= p
->IDD4W
* 1000;
126 powerSpec
.idd4w2
= p
->IDD4W2
* 1000;
127 powerSpec
.idd5
= p
->IDD5
* 1000;
128 powerSpec
.idd52
= p
->IDD52
* 1000;
129 powerSpec
.idd6
= p
->IDD6
* 1000;
130 powerSpec
.idd62
= p
->IDD62
* 1000;
131 powerSpec
.vdd
= p
->VDD
;
132 powerSpec
.vdd2
= p
->VDD2
;
136 Data::MemorySpecification
137 DRAMPower::getMemSpec(const DRAMCtrlParams
* p
)
139 Data::MemorySpecification memSpec
;
140 memSpec
.memArchSpec
= getArchParams(p
);
141 memSpec
.memTimingSpec
= getTimingParams(p
);
142 memSpec
.memPowerSpec
= getPowerParams(p
);
147 DRAMPower::hasTwoVDD(const DRAMCtrlParams
* p
)
149 return p
->VDD2
== 0 ? false : true;
153 DRAMPower::getDataRate(const DRAMCtrlParams
* p
)
155 uint32_t burst_cycles
= divCeil(p
->tBURST
, p
->tCK
);
156 uint8_t data_rate
= p
->burst_length
/ burst_cycles
;
158 if (data_rate
!= 1 && data_rate
!= 2 && data_rate
!= 4)
159 fatal("Got unexpected data rate %d, should be 1 or 2 or 4\n");