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38 #include "mem/drampower.hh"
40 #include "base/intmath.hh"
41 #include "sim/core.hh"
43 DRAMPower::DRAMPower(const DRAMInterfaceParams
&p
, bool include_io
) :
44 powerlib(libDRAMPower(getMemSpec(p
), include_io
))
48 Data::MemArchitectureSpec
49 DRAMPower::getArchParams(const DRAMInterfaceParams
&p
)
51 Data::MemArchitectureSpec archSpec
;
52 archSpec
.burstLength
= p
.burst_length
;
53 archSpec
.nbrOfBanks
= p
.banks_per_rank
;
54 // One DRAMPower instance per rank, hence set this to 1
55 archSpec
.nbrOfRanks
= 1;
56 archSpec
.dataRate
= p
.beats_per_clock
;
57 // For now we can ignore the number of columns and rows as they
58 // are not used in the power calculation.
59 archSpec
.nbrOfColumns
= 0;
60 archSpec
.nbrOfRows
= 0;
61 archSpec
.width
= p
.device_bus_width
;
62 archSpec
.nbrOfBankGroups
= p
.bank_groups_per_rank
;
64 archSpec
.twoVoltageDomains
= hasTwoVDD(p
);
65 // Keep this disabled for now until the model is firmed up.
66 archSpec
.termination
= false;
71 DRAMPower::getTimingParams(const DRAMInterfaceParams
&p
)
73 // Set the values that are used for power calculations and ignore
74 // the ones only used by the controller functionality in DRAMPower
76 // All DRAMPower timings are in clock cycles
77 Data::MemTimingSpec timingSpec
;
78 timingSpec
.RC
= divCeil((p
.tRAS
+ p
.tRP
), p
.tCK
);
79 timingSpec
.RCD
= divCeil(p
.tRCD
, p
.tCK
);
80 timingSpec
.RL
= divCeil(p
.tCL
, p
.tCK
);
81 timingSpec
.RP
= divCeil(p
.tRP
, p
.tCK
);
82 timingSpec
.RFC
= divCeil(p
.tRFC
, p
.tCK
);
83 timingSpec
.RAS
= divCeil(p
.tRAS
, p
.tCK
);
84 // Write latency is read latency - 1 cycle
85 // Source: B.Jacob Memory Systems Cache, DRAM, Disk
86 timingSpec
.WL
= timingSpec
.RL
- 1;
87 timingSpec
.DQSCK
= 0; // ignore for now
88 timingSpec
.RTP
= divCeil(p
.tRTP
, p
.tCK
);
89 timingSpec
.WR
= divCeil(p
.tWR
, p
.tCK
);
90 timingSpec
.XP
= divCeil(p
.tXP
, p
.tCK
);
91 timingSpec
.XPDLL
= divCeil(p
.tXPDLL
, p
.tCK
);
92 timingSpec
.XS
= divCeil(p
.tXS
, p
.tCK
);
93 timingSpec
.XSDLL
= divCeil(p
.tXSDLL
, p
.tCK
);
96 timingSpec
.clkPeriod
= (p
.tCK
/ (double)(SimClock::Int::ns
));
97 assert(timingSpec
.clkPeriod
!= 0);
98 timingSpec
.clkMhz
= (1 / timingSpec
.clkPeriod
) * 1000;
103 DRAMPower::getPowerParams(const DRAMInterfaceParams
&p
)
105 // All DRAMPower currents are in mA
106 Data::MemPowerSpec powerSpec
;
107 powerSpec
.idd0
= p
.IDD0
* 1000;
108 powerSpec
.idd02
= p
.IDD02
* 1000;
109 powerSpec
.idd2p0
= p
.IDD2P0
* 1000;
110 powerSpec
.idd2p02
= p
.IDD2P02
* 1000;
111 powerSpec
.idd2p1
= p
.IDD2P1
* 1000;
112 powerSpec
.idd2p12
= p
.IDD2P12
* 1000;
113 powerSpec
.idd2n
= p
.IDD2N
* 1000;
114 powerSpec
.idd2n2
= p
.IDD2N2
* 1000;
115 powerSpec
.idd3p0
= p
.IDD3P0
* 1000;
116 powerSpec
.idd3p02
= p
.IDD3P02
* 1000;
117 powerSpec
.idd3p1
= p
.IDD3P1
* 1000;
118 powerSpec
.idd3p12
= p
.IDD3P12
* 1000;
119 powerSpec
.idd3n
= p
.IDD3N
* 1000;
120 powerSpec
.idd3n2
= p
.IDD3N2
* 1000;
121 powerSpec
.idd4r
= p
.IDD4R
* 1000;
122 powerSpec
.idd4r2
= p
.IDD4R2
* 1000;
123 powerSpec
.idd4w
= p
.IDD4W
* 1000;
124 powerSpec
.idd4w2
= p
.IDD4W2
* 1000;
125 powerSpec
.idd5
= p
.IDD5
* 1000;
126 powerSpec
.idd52
= p
.IDD52
* 1000;
127 powerSpec
.idd6
= p
.IDD6
* 1000;
128 powerSpec
.idd62
= p
.IDD62
* 1000;
129 powerSpec
.vdd
= p
.VDD
;
130 powerSpec
.vdd2
= p
.VDD2
;
134 Data::MemorySpecification
135 DRAMPower::getMemSpec(const DRAMInterfaceParams
&p
)
137 Data::MemorySpecification memSpec
;
138 memSpec
.memArchSpec
= getArchParams(p
);
139 memSpec
.memTimingSpec
= getTimingParams(p
);
140 memSpec
.memPowerSpec
= getPowerParams(p
);
145 DRAMPower::hasTwoVDD(const DRAMInterfaceParams
&p
)
147 return p
.VDD2
== 0 ? false : true;
151 DRAMPower::getDataRate(const DRAMInterfaceParams
&p
)
153 uint32_t burst_cycles
= divCeil(p
.tBURST_MAX
, p
.tCK
);
154 uint8_t data_rate
= p
.burst_length
/ burst_cycles
;
156 if (data_rate
!= 1 && data_rate
!= 2 && data_rate
!= 4 && data_rate
!= 8)
157 fatal("Got unexpected data rate %d, should be 1 or 2 or 4 or 8\n");