2 * Copyright (c) 2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andreas Hansson
40 #include "mem/dramsim2.hh"
42 #include "DRAMSim2/Callback.h"
43 #include "base/callback.hh"
44 #include "base/trace.hh"
45 #include "debug/DRAMSim2.hh"
46 #include "debug/Drain.hh"
47 #include "sim/system.hh"
49 DRAMSim2::DRAMSim2(const Params
* p
) :
51 port(name() + ".port", *this),
52 wrapper(p
->deviceConfigFile
, p
->systemConfigFile
, p
->filePath
,
53 p
->traceFile
, p
->range
.size() / 1024 / 1024, p
->enableDebug
),
54 retryReq(false), retryResp(false), startTick(0),
55 nbrOutstandingReads(0), nbrOutstandingWrites(0),
56 sendResponseEvent([this]{ sendResponse(); }, name()),
57 tickEvent([this]{ tick(); }, name())
60 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
61 wrapper
.clockPeriod(), wrapper
.queueSize());
63 DRAMSim::TransactionCompleteCB
* read_cb
=
64 new DRAMSim::Callback
<DRAMSim2
, void, unsigned, uint64_t, uint64_t>(
65 this, &DRAMSim2::readComplete
);
66 DRAMSim::TransactionCompleteCB
* write_cb
=
67 new DRAMSim::Callback
<DRAMSim2
, void, unsigned, uint64_t, uint64_t>(
68 this, &DRAMSim2::writeComplete
);
69 wrapper
.setCallbacks(read_cb
, write_cb
);
71 // Register a callback to compensate for the destructor not
72 // being called. The callback prints the DRAMSim2 stats.
73 Callback
* cb
= new MakeCallback
<DRAMSim2Wrapper
,
74 &DRAMSim2Wrapper::printStats
>(wrapper
);
75 registerExitCallback(cb
);
81 AbstractMemory::init();
83 if (!port
.isConnected()) {
84 fatal("DRAMSim2 %s is unconnected!\n", name());
86 port
.sendRangeChange();
89 if (system()->cacheLineSize() != wrapper
.burstSize())
90 fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
91 wrapper
.burstSize(), system()->cacheLineSize());
97 startTick
= curTick();
99 // kick off the clock ticks
100 schedule(tickEvent
, clockEdge());
104 DRAMSim2::sendResponse()
107 assert(!responseQueue
.empty());
109 DPRINTF(DRAMSim2
, "Attempting to send response\n");
111 bool success
= port
.sendTimingResp(responseQueue
.front());
113 responseQueue
.pop_front();
115 DPRINTF(DRAMSim2
, "Have %d read, %d write, %d responses outstanding\n",
116 nbrOutstandingReads
, nbrOutstandingWrites
,
117 responseQueue
.size());
119 if (!responseQueue
.empty() && !sendResponseEvent
.scheduled())
120 schedule(sendResponseEvent
, curTick());
122 if (nbrOutstanding() == 0)
127 DPRINTF(DRAMSim2
, "Waiting for response retry\n");
129 assert(!sendResponseEvent
.scheduled());
134 DRAMSim2::nbrOutstanding() const
136 return nbrOutstandingReads
+ nbrOutstandingWrites
+ responseQueue
.size();
144 // is the connected port waiting for a retry, if so check the
145 // state and send a retry if conditions have changed
146 if (retryReq
&& nbrOutstanding() < wrapper
.queueSize()) {
151 schedule(tickEvent
, curTick() + wrapper
.clockPeriod() * SimClock::Int::ns
);
155 DRAMSim2::recvAtomic(PacketPtr pkt
)
159 // 50 ns is just an arbitrary value at this point
160 return pkt
->cacheResponding() ? 0 : 50000;
164 DRAMSim2::recvFunctional(PacketPtr pkt
)
166 pkt
->pushLabel(name());
168 functionalAccess(pkt
);
170 // potentially update the packets in our response queue as well
171 for (auto i
= responseQueue
.begin(); i
!= responseQueue
.end(); ++i
)
172 pkt
->trySatisfyFunctional(*i
);
178 DRAMSim2::recvTimingReq(PacketPtr pkt
)
180 // if a cache is responding, sink the packet without further action
181 if (pkt
->cacheResponding()) {
182 pendingDelete
.reset(pkt
);
186 // we should not get a new request after committing to retry the
187 // current one, but unfortunately the CPU violates this rule, so
188 // simply ignore it for now
192 // if we cannot accept we need to send a retry once progress can
194 bool can_accept
= nbrOutstanding() < wrapper
.queueSize();
196 // keep track of the transaction
199 outstandingReads
[pkt
->getAddr()].push(pkt
);
201 // we count a transaction as outstanding until it has left the
202 // queue in the controller, and the response has been sent
203 // back, note that this will differ for reads and writes
204 ++nbrOutstandingReads
;
206 } else if (pkt
->isWrite()) {
208 outstandingWrites
[pkt
->getAddr()].push(pkt
);
210 ++nbrOutstandingWrites
;
212 // perform the access for writes
213 accessAndRespond(pkt
);
216 // keep it simple and just respond if necessary
217 accessAndRespond(pkt
);
222 // we should never have a situation when we think there is space,
224 assert(wrapper
.canAccept());
226 DPRINTF(DRAMSim2
, "Enqueueing address %lld\n", pkt
->getAddr());
228 // @todo what about the granularity here, implicit assumption that
229 // a transaction matches the burst size of the memory (which we
230 // cannot determine without parsing the ini file ourselves)
231 wrapper
.enqueue(pkt
->isWrite(), pkt
->getAddr());
241 DRAMSim2::recvRespRetry()
243 DPRINTF(DRAMSim2
, "Retrying\n");
251 DRAMSim2::accessAndRespond(PacketPtr pkt
)
253 DPRINTF(DRAMSim2
, "Access for address %lld\n", pkt
->getAddr());
255 bool needsResponse
= pkt
->needsResponse();
257 // do the actual memory access which also turns the packet into a
261 // turn packet around to go back to requester if response expected
263 // access already turned the packet into a response
264 assert(pkt
->isResponse());
265 // Here we pay for xbar additional delay and to process the payload
267 Tick time
= curTick() + pkt
->headerDelay
+ pkt
->payloadDelay
;
268 // Reset the timings of the packet
269 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
271 DPRINTF(DRAMSim2
, "Queuing response for address %lld\n",
274 // queue it to be sent back
275 responseQueue
.push_back(pkt
);
277 // if we are not already waiting for a retry, or are scheduled
278 // to send a response, schedule an event
279 if (!retryResp
&& !sendResponseEvent
.scheduled())
280 schedule(sendResponseEvent
, time
);
282 // queue the packet for deletion
283 pendingDelete
.reset(pkt
);
287 void DRAMSim2::readComplete(unsigned id
, uint64_t addr
, uint64_t cycle
)
289 assert(cycle
== divCeil(curTick() - startTick
,
290 wrapper
.clockPeriod() * SimClock::Int::ns
));
292 DPRINTF(DRAMSim2
, "Read to address %lld complete\n", addr
);
294 // get the outstanding reads for the address in question
295 auto p
= outstandingReads
.find(addr
);
296 assert(p
!= outstandingReads
.end());
298 // first in first out, which is not necessarily true, but it is
299 // the best we can do at this point
300 PacketPtr pkt
= p
->second
.front();
303 if (p
->second
.empty())
304 outstandingReads
.erase(p
);
306 // no need to check for drain here as the next call will add a
307 // response to the response queue straight away
308 assert(nbrOutstandingReads
!= 0);
309 --nbrOutstandingReads
;
311 // perform the actual memory access
312 accessAndRespond(pkt
);
315 void DRAMSim2::writeComplete(unsigned id
, uint64_t addr
, uint64_t cycle
)
317 assert(cycle
== divCeil(curTick() - startTick
,
318 wrapper
.clockPeriod() * SimClock::Int::ns
));
320 DPRINTF(DRAMSim2
, "Write to address %lld complete\n", addr
);
322 // get the outstanding reads for the address in question
323 auto p
= outstandingWrites
.find(addr
);
324 assert(p
!= outstandingWrites
.end());
326 // we have already responded, and this is only to keep track of
327 // what is outstanding
329 if (p
->second
.empty())
330 outstandingWrites
.erase(p
);
332 assert(nbrOutstandingWrites
!= 0);
333 --nbrOutstandingWrites
;
335 if (nbrOutstanding() == 0)
340 DRAMSim2::getPort(const std::string
&if_name
, PortID idx
)
342 if (if_name
!= "port") {
343 return AbstractMemory::getPort(if_name
, idx
);
352 // check our outstanding reads and writes and if any they need to
354 return nbrOutstanding() != 0 ? DrainState::Draining
: DrainState::Drained
;
357 DRAMSim2::MemoryPort::MemoryPort(const std::string
& _name
,
359 : SlavePort(_name
, &_memory
), memory(_memory
)
363 DRAMSim2::MemoryPort::getAddrRanges() const
365 AddrRangeList ranges
;
366 ranges
.push_back(memory
.getAddrRange());
371 DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt
)
373 return memory
.recvAtomic(pkt
);
377 DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt
)
379 memory
.recvFunctional(pkt
);
383 DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt
)
385 // pass it to the memory controller
386 return memory
.recvTimingReq(pkt
);
390 DRAMSim2::MemoryPort::recvRespRetry()
392 memory
.recvRespRetry();
396 DRAMSim2Params::create()
398 return new DRAMSim2(this);