2 * Copyright (c) 2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include "mem/dramsim2.hh"
40 #include "DRAMSim2/Callback.h"
41 #include "base/callback.hh"
42 #include "base/trace.hh"
43 #include "debug/DRAMSim2.hh"
44 #include "debug/Drain.hh"
45 #include "sim/system.hh"
47 DRAMSim2::DRAMSim2(const Params
&p
) :
49 port(name() + ".port", *this),
50 wrapper(p
.deviceConfigFile
, p
.systemConfigFile
, p
.filePath
,
51 p
.traceFile
, p
.range
.size() / 1024 / 1024, p
.enableDebug
),
52 retryReq(false), retryResp(false), startTick(0),
53 nbrOutstandingReads(0), nbrOutstandingWrites(0),
54 sendResponseEvent([this]{ sendResponse(); }, name()),
55 tickEvent([this]{ tick(); }, name())
58 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
59 wrapper
.clockPeriod(), wrapper
.queueSize());
61 DRAMSim::TransactionCompleteCB
* read_cb
=
62 new DRAMSim::Callback
<DRAMSim2
, void, unsigned, uint64_t, uint64_t>(
63 this, &DRAMSim2::readComplete
);
64 DRAMSim::TransactionCompleteCB
* write_cb
=
65 new DRAMSim::Callback
<DRAMSim2
, void, unsigned, uint64_t, uint64_t>(
66 this, &DRAMSim2::writeComplete
);
67 wrapper
.setCallbacks(read_cb
, write_cb
);
69 // Register a callback to compensate for the destructor not
70 // being called. The callback prints the DRAMSim2 stats.
71 registerExitCallback([this]() { wrapper
.printStats(); });
77 AbstractMemory::init();
79 if (!port
.isConnected()) {
80 fatal("DRAMSim2 %s is unconnected!\n", name());
82 port
.sendRangeChange();
85 if (system()->cacheLineSize() != wrapper
.burstSize())
86 fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
87 wrapper
.burstSize(), system()->cacheLineSize());
93 startTick
= curTick();
95 // kick off the clock ticks
96 schedule(tickEvent
, clockEdge());
100 DRAMSim2::sendResponse()
103 assert(!responseQueue
.empty());
105 DPRINTF(DRAMSim2
, "Attempting to send response\n");
107 bool success
= port
.sendTimingResp(responseQueue
.front());
109 responseQueue
.pop_front();
111 DPRINTF(DRAMSim2
, "Have %d read, %d write, %d responses outstanding\n",
112 nbrOutstandingReads
, nbrOutstandingWrites
,
113 responseQueue
.size());
115 if (!responseQueue
.empty() && !sendResponseEvent
.scheduled())
116 schedule(sendResponseEvent
, curTick());
118 if (nbrOutstanding() == 0)
123 DPRINTF(DRAMSim2
, "Waiting for response retry\n");
125 assert(!sendResponseEvent
.scheduled());
130 DRAMSim2::nbrOutstanding() const
132 return nbrOutstandingReads
+ nbrOutstandingWrites
+ responseQueue
.size();
140 // is the connected port waiting for a retry, if so check the
141 // state and send a retry if conditions have changed
142 if (retryReq
&& nbrOutstanding() < wrapper
.queueSize()) {
147 schedule(tickEvent
, curTick() + wrapper
.clockPeriod() * SimClock::Int::ns
);
151 DRAMSim2::recvAtomic(PacketPtr pkt
)
155 // 50 ns is just an arbitrary value at this point
156 return pkt
->cacheResponding() ? 0 : 50000;
160 DRAMSim2::recvFunctional(PacketPtr pkt
)
162 pkt
->pushLabel(name());
164 functionalAccess(pkt
);
166 // potentially update the packets in our response queue as well
167 for (auto i
= responseQueue
.begin(); i
!= responseQueue
.end(); ++i
)
168 pkt
->trySatisfyFunctional(*i
);
174 DRAMSim2::recvTimingReq(PacketPtr pkt
)
176 // if a cache is responding, sink the packet without further action
177 if (pkt
->cacheResponding()) {
178 pendingDelete
.reset(pkt
);
182 // we should not get a new request after committing to retry the
183 // current one, but unfortunately the CPU violates this rule, so
184 // simply ignore it for now
188 // if we cannot accept we need to send a retry once progress can
190 bool can_accept
= nbrOutstanding() < wrapper
.queueSize();
192 // keep track of the transaction
195 outstandingReads
[pkt
->getAddr()].push(pkt
);
197 // we count a transaction as outstanding until it has left the
198 // queue in the controller, and the response has been sent
199 // back, note that this will differ for reads and writes
200 ++nbrOutstandingReads
;
202 } else if (pkt
->isWrite()) {
204 outstandingWrites
[pkt
->getAddr()].push(pkt
);
206 ++nbrOutstandingWrites
;
208 // perform the access for writes
209 accessAndRespond(pkt
);
212 // keep it simple and just respond if necessary
213 accessAndRespond(pkt
);
218 // we should never have a situation when we think there is space,
220 assert(wrapper
.canAccept());
222 DPRINTF(DRAMSim2
, "Enqueueing address %lld\n", pkt
->getAddr());
224 // @todo what about the granularity here, implicit assumption that
225 // a transaction matches the burst size of the memory (which we
226 // cannot determine without parsing the ini file ourselves)
227 wrapper
.enqueue(pkt
->isWrite(), pkt
->getAddr());
237 DRAMSim2::recvRespRetry()
239 DPRINTF(DRAMSim2
, "Retrying\n");
247 DRAMSim2::accessAndRespond(PacketPtr pkt
)
249 DPRINTF(DRAMSim2
, "Access for address %lld\n", pkt
->getAddr());
251 bool needsResponse
= pkt
->needsResponse();
253 // do the actual memory access which also turns the packet into a
257 // turn packet around to go back to requestor if response expected
259 // access already turned the packet into a response
260 assert(pkt
->isResponse());
261 // Here we pay for xbar additional delay and to process the payload
263 Tick time
= curTick() + pkt
->headerDelay
+ pkt
->payloadDelay
;
264 // Reset the timings of the packet
265 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
267 DPRINTF(DRAMSim2
, "Queuing response for address %lld\n",
270 // queue it to be sent back
271 responseQueue
.push_back(pkt
);
273 // if we are not already waiting for a retry, or are scheduled
274 // to send a response, schedule an event
275 if (!retryResp
&& !sendResponseEvent
.scheduled())
276 schedule(sendResponseEvent
, time
);
278 // queue the packet for deletion
279 pendingDelete
.reset(pkt
);
283 void DRAMSim2::readComplete(unsigned id
, uint64_t addr
, uint64_t cycle
)
285 assert(cycle
== divCeil(curTick() - startTick
,
286 wrapper
.clockPeriod() * SimClock::Int::ns
));
288 DPRINTF(DRAMSim2
, "Read to address %lld complete\n", addr
);
290 // get the outstanding reads for the address in question
291 auto p
= outstandingReads
.find(addr
);
292 assert(p
!= outstandingReads
.end());
294 // first in first out, which is not necessarily true, but it is
295 // the best we can do at this point
296 PacketPtr pkt
= p
->second
.front();
299 if (p
->second
.empty())
300 outstandingReads
.erase(p
);
302 // no need to check for drain here as the next call will add a
303 // response to the response queue straight away
304 assert(nbrOutstandingReads
!= 0);
305 --nbrOutstandingReads
;
307 // perform the actual memory access
308 accessAndRespond(pkt
);
311 void DRAMSim2::writeComplete(unsigned id
, uint64_t addr
, uint64_t cycle
)
313 assert(cycle
== divCeil(curTick() - startTick
,
314 wrapper
.clockPeriod() * SimClock::Int::ns
));
316 DPRINTF(DRAMSim2
, "Write to address %lld complete\n", addr
);
318 // get the outstanding reads for the address in question
319 auto p
= outstandingWrites
.find(addr
);
320 assert(p
!= outstandingWrites
.end());
322 // we have already responded, and this is only to keep track of
323 // what is outstanding
325 if (p
->second
.empty())
326 outstandingWrites
.erase(p
);
328 assert(nbrOutstandingWrites
!= 0);
329 --nbrOutstandingWrites
;
331 if (nbrOutstanding() == 0)
336 DRAMSim2::getPort(const std::string
&if_name
, PortID idx
)
338 if (if_name
!= "port") {
339 return AbstractMemory::getPort(if_name
, idx
);
348 // check our outstanding reads and writes and if any they need to
350 return nbrOutstanding() != 0 ? DrainState::Draining
: DrainState::Drained
;
353 DRAMSim2::MemoryPort::MemoryPort(const std::string
& _name
,
355 : ResponsePort(_name
, &_memory
), memory(_memory
)
359 DRAMSim2::MemoryPort::getAddrRanges() const
361 AddrRangeList ranges
;
362 ranges
.push_back(memory
.getAddrRange());
367 DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt
)
369 return memory
.recvAtomic(pkt
);
373 DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt
)
375 memory
.recvFunctional(pkt
);
379 DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt
)
381 // pass it to the memory controller
382 return memory
.recvTimingReq(pkt
);
386 DRAMSim2::MemoryPort::recvRespRetry()
388 memory
.recvRespRetry();