2 * Copyright (c) 2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andreas Hansson
40 #include "DRAMSim2/Callback.h"
41 #include "base/callback.hh"
42 #include "base/trace.hh"
43 #include "debug/DRAMSim2.hh"
44 #include "debug/Drain.hh"
45 #include "mem/dramsim2.hh"
46 #include "sim/system.hh"
48 DRAMSim2::DRAMSim2(const Params
* p
) :
50 port(name() + ".port", *this),
51 wrapper(p
->deviceConfigFile
, p
->systemConfigFile
, p
->filePath
,
52 p
->traceFile
, p
->range
.size() / 1024 / 1024, p
->enableDebug
),
53 retryReq(false), retryResp(false), startTick(0),
54 nbrOutstandingReads(0), nbrOutstandingWrites(0),
55 sendResponseEvent(this), tickEvent(this)
58 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
59 wrapper
.clockPeriod(), wrapper
.queueSize());
61 DRAMSim::TransactionCompleteCB
* read_cb
=
62 new DRAMSim::Callback
<DRAMSim2
, void, unsigned, uint64_t, uint64_t>(
63 this, &DRAMSim2::readComplete
);
64 DRAMSim::TransactionCompleteCB
* write_cb
=
65 new DRAMSim::Callback
<DRAMSim2
, void, unsigned, uint64_t, uint64_t>(
66 this, &DRAMSim2::writeComplete
);
67 wrapper
.setCallbacks(read_cb
, write_cb
);
69 // Register a callback to compensate for the destructor not
70 // being called. The callback prints the DRAMSim2 stats.
71 Callback
* cb
= new MakeCallback
<DRAMSim2Wrapper
,
72 &DRAMSim2Wrapper::printStats
>(wrapper
);
73 registerExitCallback(cb
);
79 AbstractMemory::init();
81 if (!port
.isConnected()) {
82 fatal("DRAMSim2 %s is unconnected!\n", name());
84 port
.sendRangeChange();
87 if (system()->cacheLineSize() != wrapper
.burstSize())
88 fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
89 wrapper
.burstSize(), system()->cacheLineSize());
95 startTick
= curTick();
97 // kick off the clock ticks
98 schedule(tickEvent
, clockEdge());
102 DRAMSim2::sendResponse()
105 assert(!responseQueue
.empty());
107 DPRINTF(DRAMSim2
, "Attempting to send response\n");
109 bool success
= port
.sendTimingResp(responseQueue
.front());
111 responseQueue
.pop_front();
113 DPRINTF(DRAMSim2
, "Have %d read, %d write, %d responses outstanding\n",
114 nbrOutstandingReads
, nbrOutstandingWrites
,
115 responseQueue
.size());
117 if (!responseQueue
.empty() && !sendResponseEvent
.scheduled())
118 schedule(sendResponseEvent
, curTick());
120 if (nbrOutstanding() == 0)
125 DPRINTF(DRAMSim2
, "Waiting for response retry\n");
127 assert(!sendResponseEvent
.scheduled());
132 DRAMSim2::nbrOutstanding() const
134 return nbrOutstandingReads
+ nbrOutstandingWrites
+ responseQueue
.size();
142 // is the connected port waiting for a retry, if so check the
143 // state and send a retry if conditions have changed
144 if (retryReq
&& nbrOutstanding() < wrapper
.queueSize()) {
149 schedule(tickEvent
, curTick() + wrapper
.clockPeriod() * SimClock::Int::ns
);
153 DRAMSim2::recvAtomic(PacketPtr pkt
)
157 // 50 ns is just an arbitrary value at this point
158 return pkt
->cacheResponding() ? 0 : 50000;
162 DRAMSim2::recvFunctional(PacketPtr pkt
)
164 pkt
->pushLabel(name());
166 functionalAccess(pkt
);
168 // potentially update the packets in our response queue as well
169 for (auto i
= responseQueue
.begin(); i
!= responseQueue
.end(); ++i
)
170 pkt
->checkFunctional(*i
);
176 DRAMSim2::recvTimingReq(PacketPtr pkt
)
178 // if a cache is responding, sink the packet without further action
179 if (pkt
->cacheResponding()) {
180 pendingDelete
.reset(pkt
);
184 // we should not get a new request after committing to retry the
185 // current one, but unfortunately the CPU violates this rule, so
186 // simply ignore it for now
190 // if we cannot accept we need to send a retry once progress can
192 bool can_accept
= nbrOutstanding() < wrapper
.queueSize();
194 // keep track of the transaction
197 outstandingReads
[pkt
->getAddr()].push(pkt
);
199 // we count a transaction as outstanding until it has left the
200 // queue in the controller, and the response has been sent
201 // back, note that this will differ for reads and writes
202 ++nbrOutstandingReads
;
204 } else if (pkt
->isWrite()) {
206 outstandingWrites
[pkt
->getAddr()].push(pkt
);
208 ++nbrOutstandingWrites
;
210 // perform the access for writes
211 accessAndRespond(pkt
);
214 // keep it simple and just respond if necessary
215 accessAndRespond(pkt
);
220 // we should never have a situation when we think there is space,
222 assert(wrapper
.canAccept());
224 DPRINTF(DRAMSim2
, "Enqueueing address %lld\n", pkt
->getAddr());
226 // @todo what about the granularity here, implicit assumption that
227 // a transaction matches the burst size of the memory (which we
228 // cannot determine without parsing the ini file ourselves)
229 wrapper
.enqueue(pkt
->isWrite(), pkt
->getAddr());
239 DRAMSim2::recvRespRetry()
241 DPRINTF(DRAMSim2
, "Retrying\n");
249 DRAMSim2::accessAndRespond(PacketPtr pkt
)
251 DPRINTF(DRAMSim2
, "Access for address %lld\n", pkt
->getAddr());
253 bool needsResponse
= pkt
->needsResponse();
255 // do the actual memory access which also turns the packet into a
259 // turn packet around to go back to requester if response expected
261 // access already turned the packet into a response
262 assert(pkt
->isResponse());
263 // Here we pay for xbar additional delay and to process the payload
265 Tick time
= curTick() + pkt
->headerDelay
+ pkt
->payloadDelay
;
266 // Reset the timings of the packet
267 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
269 DPRINTF(DRAMSim2
, "Queuing response for address %lld\n",
272 // queue it to be sent back
273 responseQueue
.push_back(pkt
);
275 // if we are not already waiting for a retry, or are scheduled
276 // to send a response, schedule an event
277 if (!retryResp
&& !sendResponseEvent
.scheduled())
278 schedule(sendResponseEvent
, time
);
280 // queue the packet for deletion
281 pendingDelete
.reset(pkt
);
285 void DRAMSim2::readComplete(unsigned id
, uint64_t addr
, uint64_t cycle
)
287 assert(cycle
== divCeil(curTick() - startTick
,
288 wrapper
.clockPeriod() * SimClock::Int::ns
));
290 DPRINTF(DRAMSim2
, "Read to address %lld complete\n", addr
);
292 // get the outstanding reads for the address in question
293 auto p
= outstandingReads
.find(addr
);
294 assert(p
!= outstandingReads
.end());
296 // first in first out, which is not necessarily true, but it is
297 // the best we can do at this point
298 PacketPtr pkt
= p
->second
.front();
301 if (p
->second
.empty())
302 outstandingReads
.erase(p
);
304 // no need to check for drain here as the next call will add a
305 // response to the response queue straight away
306 assert(nbrOutstandingReads
!= 0);
307 --nbrOutstandingReads
;
309 // perform the actual memory access
310 accessAndRespond(pkt
);
313 void DRAMSim2::writeComplete(unsigned id
, uint64_t addr
, uint64_t cycle
)
315 assert(cycle
== divCeil(curTick() - startTick
,
316 wrapper
.clockPeriod() * SimClock::Int::ns
));
318 DPRINTF(DRAMSim2
, "Write to address %lld complete\n", addr
);
320 // get the outstanding reads for the address in question
321 auto p
= outstandingWrites
.find(addr
);
322 assert(p
!= outstandingWrites
.end());
324 // we have already responded, and this is only to keep track of
325 // what is outstanding
327 if (p
->second
.empty())
328 outstandingWrites
.erase(p
);
330 assert(nbrOutstandingWrites
!= 0);
331 --nbrOutstandingWrites
;
333 if (nbrOutstanding() == 0)
338 DRAMSim2::getSlavePort(const std::string
&if_name
, PortID idx
)
340 if (if_name
!= "port") {
341 return MemObject::getSlavePort(if_name
, idx
);
350 // check our outstanding reads and writes and if any they need to
352 return nbrOutstanding() != 0 ? DrainState::Draining
: DrainState::Drained
;
355 DRAMSim2::MemoryPort::MemoryPort(const std::string
& _name
,
357 : SlavePort(_name
, &_memory
), memory(_memory
)
361 DRAMSim2::MemoryPort::getAddrRanges() const
363 AddrRangeList ranges
;
364 ranges
.push_back(memory
.getAddrRange());
369 DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt
)
371 return memory
.recvAtomic(pkt
);
375 DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt
)
377 memory
.recvFunctional(pkt
);
381 DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt
)
383 // pass it to the memory controller
384 return memory
.recvTimingReq(pkt
);
388 DRAMSim2::MemoryPort::recvRespRetry()
390 memory
.recvRespRetry();
394 DRAMSim2Params::create()
396 return new DRAMSim2(this);