2 * Copyright (c) 2013 ARM Limited
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25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andreas Hansson
44 #ifndef __MEM_DRAMSIM2_HH__
45 #define __MEM_DRAMSIM2_HH__
48 #include <unordered_map>
50 #include "mem/abstract_mem.hh"
51 #include "mem/dramsim2_wrapper.hh"
52 #include "mem/qport.hh"
53 #include "params/DRAMSim2.hh"
55 class DRAMSim2 : public AbstractMemory
60 * The memory port has to deal with its own flow control to avoid
61 * having unbounded storage that is implicitly created in the port
64 class MemoryPort : public SlavePort
73 MemoryPort(const std::string& _name, DRAMSim2& _memory);
77 Tick recvAtomic(PacketPtr pkt);
79 void recvFunctional(PacketPtr pkt);
81 bool recvTimingReq(PacketPtr pkt);
85 AddrRangeList getAddrRanges() const;
92 * The actual DRAMSim2 wrapper
94 DRAMSim2Wrapper wrapper;
97 * Is the connected port waiting for a retry from us
102 * Are we waiting for a retry for sending a response.
107 * Keep track of when the wrapper is started.
112 * Keep track of what packets are outstanding per
113 * address, and do so separately for reads and writes. This is
114 * done so that we can return the right packet on completion from
117 std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
118 std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
121 * Count the number of outstanding transactions so that we can
122 * block any further requests until there is space in DRAMSim2 and
123 * the sending queue we need to buffer the response packets.
125 unsigned int nbrOutstandingReads;
126 unsigned int nbrOutstandingWrites;
129 * Queue to hold response packets until we can send them
130 * back. This is needed as DRAMSim2 unconditionally passes
131 * responses back without any flow control.
133 std::deque<PacketPtr> responseQueue;
135 unsigned int nbrOutstanding() const;
138 * When a packet is ready, use the "access()" method in
139 * AbstractMemory to actually create the response packet, and send
140 * it back to the outside world requestor.
142 * @param pkt The packet from the outside world
144 void accessAndRespond(PacketPtr pkt);
149 * Event to schedule sending of responses
151 EventFunctionWrapper sendResponseEvent;
154 * Progress the controller one clock cycle.
159 * Event to schedule clock ticks
161 EventFunctionWrapper tickEvent;
164 * Upstream caches need this packet until true is returned, so
165 * hold it for deletion until a subsequent call
167 std::unique_ptr<Packet> pendingDelete;
171 typedef DRAMSim2Params Params;
172 DRAMSim2(const Params *p);
175 * Read completion callback.
177 * @param id Channel id of the responder
178 * @param addr Address of the request
179 * @param cycle Internal cycle count of DRAMSim2
181 void readComplete(unsigned id, uint64_t addr, uint64_t cycle);
184 * Write completion callback.
186 * @param id Channel id of the responder
187 * @param addr Address of the request
188 * @param cycle Internal cycle count of DRAMSim2
190 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
192 DrainState drain() override;
194 Port &getPort(const std::string &if_name,
195 PortID idx=InvalidPortID) override;
197 void init() override;
198 void startup() override;
202 Tick recvAtomic(PacketPtr pkt);
203 void recvFunctional(PacketPtr pkt);
204 bool recvTimingReq(PacketPtr pkt);
205 void recvRespRetry();
209 #endif // __MEM_DRAMSIM2_HH__