src/mem/dramsim2.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /**
  39  * @file
  40  * DRAMSim2
  41  */
  42 #ifndef __MEM_DRAMSIM2_HH__
  43 #define __MEM_DRAMSIM2_HH__
  44
  45 #include <queue>
  46 #include <unordered_map>
  47
  48 #include "mem/abstract_mem.hh"
  49 #include "mem/dramsim2_wrapper.hh"
  50 #include "mem/qport.hh"
  51 #include "params/DRAMSim2.hh"
  52
  53 class DRAMSim2 : public AbstractMemory
  54 {
  55   private:
  56
  57     /**
  58      * The memory port has to deal with its own flow control to avoid
  59      * having unbounded storage that is implicitly created in the port
  60      * itself.
  61      */
  62     class MemoryPort : public ResponsePort
  63     {
  64
  65       private:
  66
  67         DRAMSim2& memory;
  68
  69       public:
  70
  71         MemoryPort(const std::string& _name, DRAMSim2& _memory);
  72
  73       protected:
  74
  75         Tick recvAtomic(PacketPtr pkt);
  76
  77         void recvFunctional(PacketPtr pkt);
  78
  79         bool recvTimingReq(PacketPtr pkt);
  80
  81         void recvRespRetry();
  82
  83         AddrRangeList getAddrRanges() const;
  84
  85     };
  86
  87     MemoryPort port;
  88
  89     /**
  90      * The actual DRAMSim2 wrapper
  91      */
  92     DRAMSim2Wrapper wrapper;
  93
  94     /**
  95      * Is the connected port waiting for a retry from us
  96      */
  97     bool retryReq;
  98
  99     /**
 100      * Are we waiting for a retry for sending a response.
 101      */
 102     bool retryResp;
 103
 104     /**
 105      * Keep track of when the wrapper is started.
 106      */
 107     Tick startTick;
 108
 109     /**
 110      * Keep track of what packets are outstanding per
 111      * address, and do so separately for reads and writes. This is
 112      * done so that we can return the right packet on completion from
 113      * DRAMSim.
 114      */
 115     std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
 116     std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
 117
 118     /**
 119      * Count the number of outstanding transactions so that we can
 120      * block any further requests until there is space in DRAMSim2 and
 121      * the sending queue we need to buffer the response packets.
 122      */
 123     unsigned int nbrOutstandingReads;
 124     unsigned int nbrOutstandingWrites;
 125
 126     /**
 127      * Queue to hold response packets until we can send them
 128      * back. This is needed as DRAMSim2 unconditionally passes
 129      * responses back without any flow control.
 130      */
 131     std::deque<PacketPtr> responseQueue;
 132
 133     unsigned int nbrOutstanding() const;
 134
 135     /**
 136      * When a packet is ready, use the "access()" method in
 137      * AbstractMemory to actually create the response packet, and send
 138      * it back to the outside world requestor.
 139      *
 140      * @param pkt The packet from the outside world
 141      */
 142     void accessAndRespond(PacketPtr pkt);
 143
 144     void sendResponse();
 145
 146     /**
 147      * Event to schedule sending of responses
 148      */
 149     EventFunctionWrapper sendResponseEvent;
 150
 151     /**
 152      * Progress the controller one clock cycle.
 153      */
 154     void tick();
 155
 156     /**
 157      * Event to schedule clock ticks
 158      */
 159     EventFunctionWrapper tickEvent;
 160
 161     /**
 162      * Upstream caches need this packet until true is returned, so
 163      * hold it for deletion until a subsequent call
 164      */
 165     std::unique_ptr<Packet> pendingDelete;
 166
 167   public:
 168
 169     typedef DRAMSim2Params Params;
 170     DRAMSim2(const Params &p);
 171
 172     /**
 173      * Read completion callback.
 174      *
 175      * @param id Channel id of the responder
 176      * @param addr Address of the request
 177      * @param cycle Internal cycle count of DRAMSim2
 178      */
 179     void readComplete(unsigned id, uint64_t addr, uint64_t cycle);
 180
 181     /**
 182      * Write completion callback.
 183      *
 184      * @param id Channel id of the responder
 185      * @param addr Address of the request
 186      * @param cycle Internal cycle count of DRAMSim2
 187      */
 188     void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
 189
 190     DrainState drain() override;
 191
 192     Port &getPort(const std::string &if_name,
 193                   PortID idx=InvalidPortID) override;
 194
 195     void init() override;
 196     void startup() override;
 197
 198   protected:
 199
 200     Tick recvAtomic(PacketPtr pkt);
 201     void recvFunctional(PacketPtr pkt);
 202     bool recvTimingReq(PacketPtr pkt);
 203     void recvRespRetry();
 204
 205 };
 206
 207 #endif // __MEM_DRAMSIM2_HH__