src/mem/dramsim2.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Andreas Hansson
  38  */
  39
  40 /**
  41  * @file
  42  * DRAMSim2
  43  */
  44 #ifndef __MEM_DRAMSIM2_HH__
  45 #define __MEM_DRAMSIM2_HH__
  46
  47 #include <queue>
  48 #include <unordered_map>
  49
  50 #include "mem/abstract_mem.hh"
  51 #include "mem/dramsim2_wrapper.hh"
  52 #include "mem/qport.hh"
  53 #include "params/DRAMSim2.hh"
  54
  55 class DRAMSim2 : public AbstractMemory
  56 {
  57   private:
  58
  59     /**
  60      * The memory port has to deal with its own flow control to avoid
  61      * having unbounded storage that is implicitly created in the port
  62      * itself.
  63      */
  64     class MemoryPort : public SlavePort
  65     {
  66
  67       private:
  68
  69         DRAMSim2& memory;
  70
  71       public:
  72
  73         MemoryPort(const std::string& _name, DRAMSim2& _memory);
  74
  75       protected:
  76
  77         Tick recvAtomic(PacketPtr pkt);
  78
  79         void recvFunctional(PacketPtr pkt);
  80
  81         bool recvTimingReq(PacketPtr pkt);
  82
  83         void recvRespRetry();
  84
  85         AddrRangeList getAddrRanges() const;
  86
  87     };
  88
  89     MemoryPort port;
  90
  91     /**
  92      * The actual DRAMSim2 wrapper
  93      */
  94     DRAMSim2Wrapper wrapper;
  95
  96     /**
  97      * Is the connected port waiting for a retry from us
  98      */
  99     bool retryReq;
 100
 101     /**
 102      * Are we waiting for a retry for sending a response.
 103      */
 104     bool retryResp;
 105
 106     /**
 107      * Keep track of when the wrapper is started.
 108      */
 109     Tick startTick;
 110
 111     /**
 112      * Keep track of what packets are outstanding per
 113      * address, and do so separately for reads and writes. This is
 114      * done so that we can return the right packet on completion from
 115      * DRAMSim.
 116      */
 117     std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
 118     std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
 119
 120     /**
 121      * Count the number of outstanding transactions so that we can
 122      * block any further requests until there is space in DRAMSim2 and
 123      * the sending queue we need to buffer the response packets.
 124      */
 125     unsigned int nbrOutstandingReads;
 126     unsigned int nbrOutstandingWrites;
 127
 128     /**
 129      * Queue to hold response packets until we can send them
 130      * back. This is needed as DRAMSim2 unconditionally passes
 131      * responses back without any flow control.
 132      */
 133     std::deque<PacketPtr> responseQueue;
 134
 135     unsigned int nbrOutstanding() const;
 136
 137     /**
 138      * When a packet is ready, use the "access()" method in
 139      * AbstractMemory to actually create the response packet, and send
 140      * it back to the outside world requestor.
 141      *
 142      * @param pkt The packet from the outside world
 143      */
 144     void accessAndRespond(PacketPtr pkt);
 145
 146     void sendResponse();
 147
 148     /**
 149      * Event to schedule sending of responses
 150      */
 151     EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
 152
 153     /**
 154      * Progress the controller one clock cycle.
 155      */
 156     void tick();
 157
 158     /**
 159      * Event to schedule clock ticks
 160      */
 161     EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
 162
 163     /**
 164      * Upstream caches need this packet until true is returned, so
 165      * hold it for deletion until a subsequent call
 166      */
 167     std::unique_ptr<Packet> pendingDelete;
 168
 169   public:
 170
 171     typedef DRAMSim2Params Params;
 172     DRAMSim2(const Params *p);
 173
 174     /**
 175      * Read completion callback.
 176      *
 177      * @param id Channel id of the responder
 178      * @param addr Address of the request
 179      * @param cycle Internal cycle count of DRAMSim2
 180      */
 181     void readComplete(unsigned id, uint64_t addr, uint64_t cycle);
 182
 183     /**
 184      * Write completion callback.
 185      *
 186      * @param id Channel id of the responder
 187      * @param addr Address of the request
 188      * @param cycle Internal cycle count of DRAMSim2
 189      */
 190     void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
 191
 192     DrainState drain() override;
 193
 194     virtual BaseSlavePort& getSlavePort(const std::string& if_name,
 195                                         PortID idx = InvalidPortID) override;
 196
 197     void init() override;
 198     void startup() override;
 199
 200   protected:
 201
 202     Tick recvAtomic(PacketPtr pkt);
 203     void recvFunctional(PacketPtr pkt);
 204     bool recvTimingReq(PacketPtr pkt);
 205     void recvRespRetry();
 206
 207 };
 208
 209 #endif // __MEM_DRAMSIM2_HH__