2 * Copyright (c) 2013 ARM Limited
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25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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37 * Authors: Andreas Hansson
44 #ifndef __MEM_DRAMSIM2_HH__
45 #define __MEM_DRAMSIM2_HH__
49 #include "base/hashmap.hh"
50 #include "mem/abstract_mem.hh"
51 #include "mem/dramsim2_wrapper.hh"
52 #include "mem/qport.hh"
53 #include "params/DRAMSim2.hh"
55 class DRAMSim2 : public AbstractMemory
60 * The memory port has to deal with its own flow control to avoid
61 * having unbounded storage that is implicitly created in the port
64 class MemoryPort : public SlavePort
73 MemoryPort(const std::string& _name, DRAMSim2& _memory);
77 Tick recvAtomic(PacketPtr pkt);
79 void recvFunctional(PacketPtr pkt);
81 bool recvTimingReq(PacketPtr pkt);
85 AddrRangeList getAddrRanges() const;
92 * The actual DRAMSim2 wrapper
94 DRAMSim2Wrapper wrapper;
97 * Is the connected port waiting for a retry from us
102 * Are we waiting for a retry for sending a response.
107 * Keep track of when the wrapper is started.
112 * Keep track of what packets are outstanding per
113 * address, and do so separately for reads and writes. This is
114 * done so that we can return the right packet on completion from
117 m5::hash_map<Addr, std::queue<PacketPtr> > outstandingReads;
118 m5::hash_map<Addr, std::queue<PacketPtr> > outstandingWrites;
121 * Count the number of outstanding transactions so that we can
122 * block any further requests until there is space in DRAMSim2 and
123 * the sending queue we need to buffer the response packets.
125 unsigned int nbrOutstandingReads;
126 unsigned int nbrOutstandingWrites;
129 * Queue to hold response packets until we can send them
130 * back. This is needed as DRAMSim2 unconditionally passes
131 * responses back without any flow control.
133 std::deque<PacketPtr> responseQueue;
136 * If we need to drain, keep the drain manager around until we're
139 DrainManager *drainManager;
141 unsigned int nbrOutstanding() const;
144 * When a packet is ready, use the "access()" method in
145 * AbstractMemory to actually create the response packet, and send
146 * it back to the outside world requestor.
148 * @param pkt The packet from the outside world
150 void accessAndRespond(PacketPtr pkt);
155 * Event to schedule sending of responses
157 EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
160 * Progress the controller one clock cycle.
165 * Event to schedule clock ticks
167 EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
169 /** @todo this is a temporary workaround until the 4-phase code is
170 * committed. upstream caches needs this packet until true is returned, so
171 * hold onto it for deletion until a subsequent call
173 std::vector<PacketPtr> pendingDelete;
177 typedef DRAMSim2Params Params;
178 DRAMSim2(const Params *p);
181 * Read completion callback.
183 * @param id Channel id of the responder
184 * @param addr Address of the request
185 * @param cycle Internal cycle count of DRAMSim2
187 void readComplete(unsigned id, uint64_t addr, uint64_t cycle);
190 * Write completion callback.
192 * @param id Channel id of the responder
193 * @param addr Address of the request
194 * @param cycle Internal cycle count of DRAMSim2
196 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
198 unsigned int drain(DrainManager* dm);
200 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
201 PortID idx = InvalidPortID);
204 virtual void startup();
208 Tick recvAtomic(PacketPtr pkt);
209 void recvFunctional(PacketPtr pkt);
210 bool recvTimingReq(PacketPtr pkt);
211 void recvRespRetry();
215 #endif // __MEM_DRAMSIM2_HH__