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42 #ifndef __MEM_DRAMSIM2_HH__
43 #define __MEM_DRAMSIM2_HH__
46 #include <unordered_map>
48 #include "mem/abstract_mem.hh"
49 #include "mem/dramsim2_wrapper.hh"
50 #include "mem/qport.hh"
51 #include "params/DRAMSim2.hh"
53 class DRAMSim2 : public AbstractMemory
58 * The memory port has to deal with its own flow control to avoid
59 * having unbounded storage that is implicitly created in the port
62 class MemoryPort : public ResponsePort
71 MemoryPort(const std::string& _name, DRAMSim2& _memory);
75 Tick recvAtomic(PacketPtr pkt);
77 void recvFunctional(PacketPtr pkt);
79 bool recvTimingReq(PacketPtr pkt);
83 AddrRangeList getAddrRanges() const;
90 * The actual DRAMSim2 wrapper
92 DRAMSim2Wrapper wrapper;
95 * Is the connected port waiting for a retry from us
100 * Are we waiting for a retry for sending a response.
105 * Keep track of when the wrapper is started.
110 * Keep track of what packets are outstanding per
111 * address, and do so separately for reads and writes. This is
112 * done so that we can return the right packet on completion from
115 std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
116 std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
119 * Count the number of outstanding transactions so that we can
120 * block any further requests until there is space in DRAMSim2 and
121 * the sending queue we need to buffer the response packets.
123 unsigned int nbrOutstandingReads;
124 unsigned int nbrOutstandingWrites;
127 * Queue to hold response packets until we can send them
128 * back. This is needed as DRAMSim2 unconditionally passes
129 * responses back without any flow control.
131 std::deque<PacketPtr> responseQueue;
133 unsigned int nbrOutstanding() const;
136 * When a packet is ready, use the "access()" method in
137 * AbstractMemory to actually create the response packet, and send
138 * it back to the outside world requestor.
140 * @param pkt The packet from the outside world
142 void accessAndRespond(PacketPtr pkt);
147 * Event to schedule sending of responses
149 EventFunctionWrapper sendResponseEvent;
152 * Progress the controller one clock cycle.
157 * Event to schedule clock ticks
159 EventFunctionWrapper tickEvent;
162 * Upstream caches need this packet until true is returned, so
163 * hold it for deletion until a subsequent call
165 std::unique_ptr<Packet> pendingDelete;
169 typedef DRAMSim2Params Params;
170 DRAMSim2(const Params &p);
173 * Read completion callback.
175 * @param id Channel id of the responder
176 * @param addr Address of the request
177 * @param cycle Internal cycle count of DRAMSim2
179 void readComplete(unsigned id, uint64_t addr, uint64_t cycle);
182 * Write completion callback.
184 * @param id Channel id of the responder
185 * @param addr Address of the request
186 * @param cycle Internal cycle count of DRAMSim2
188 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
190 DrainState drain() override;
192 Port &getPort(const std::string &if_name,
193 PortID idx=InvalidPortID) override;
195 void init() override;
196 void startup() override;
200 Tick recvAtomic(PacketPtr pkt);
201 void recvFunctional(PacketPtr pkt);
202 bool recvTimingReq(PacketPtr pkt);
203 void recvRespRetry();
207 #endif // __MEM_DRAMSIM2_HH__