src/mem/dramsim3.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
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  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  */
  38
  39 /**
  40  * @file
  41  * DRAMsim3
  42  */
  43 #ifndef __MEM_DRAMSIM3_HH__
  44 #define __MEM_DRAMSIM3_HH__
  45
  46 #include <functional>
  47 #include <queue>
  48 #include <unordered_map>
  49
  50 #include "mem/abstract_mem.hh"
  51 #include "mem/dramsim3_wrapper.hh"
  52 #include "mem/qport.hh"
  53 #include "params/DRAMsim3.hh"
  54
  55 class DRAMsim3 : public AbstractMemory
  56 {
  57   private:
  58
  59     /**
  60      * The memory port has to deal with its own flow control to avoid
  61      * having unbounded storage that is implicitly created in the port
  62      * itself.
  63      */
  64     class MemoryPort : public ResponsePort
  65     {
  66
  67       private:
  68
  69         DRAMsim3& memory;
  70
  71       public:
  72
  73         MemoryPort(const std::string& _name, DRAMsim3& _memory);
  74
  75       protected:
  76
  77         Tick recvAtomic(PacketPtr pkt);
  78
  79         void recvFunctional(PacketPtr pkt);
  80
  81         bool recvTimingReq(PacketPtr pkt);
  82
  83         void recvRespRetry();
  84
  85         AddrRangeList getAddrRanges() const;
  86
  87     };
  88
  89     MemoryPort port;
  90
  91     /**
  92      * Callback functions
  93      */
  94     std::function<void(uint64_t)> read_cb;
  95     std::function<void(uint64_t)> write_cb;
  96
  97     /**
  98      * The actual DRAMsim3 wrapper
  99      */
 100     DRAMsim3Wrapper wrapper;
 101
 102     /**
 103      * Is the connected port waiting for a retry from us
 104      */
 105     bool retryReq;
 106
 107     /**
 108      * Are we waiting for a retry for sending a response.
 109      */
 110     bool retryResp;
 111
 112     /**
 113      * Keep track of when the wrapper is started.
 114      */
 115     Tick startTick;
 116
 117     /**
 118      * Keep track of what packets are outstanding per
 119      * address, and do so separately for reads and writes. This is
 120      * done so that we can return the right packet on completion from
 121      * DRAMSim.
 122      */
 123     std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
 124     std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
 125
 126     /**
 127      * Count the number of outstanding transactions so that we can
 128      * block any further requests until there is space in DRAMsim3 and
 129      * the sending queue we need to buffer the response packets.
 130      */
 131     unsigned int nbrOutstandingReads;
 132     unsigned int nbrOutstandingWrites;
 133
 134     /**
 135      * Queue to hold response packets until we can send them
 136      * back. This is needed as DRAMsim3 unconditionally passes
 137      * responses back without any flow control.
 138      */
 139     std::deque<PacketPtr> responseQueue;
 140
 141
 142     unsigned int nbrOutstanding() const;
 143
 144     /**
 145      * When a packet is ready, use the "access()" method in
 146      * AbstractMemory to actually create the response packet, and send
 147      * it back to the outside world requestor.
 148      *
 149      * @param pkt The packet from the outside world
 150      */
 151     void accessAndRespond(PacketPtr pkt);
 152
 153     void sendResponse();
 154
 155     /**
 156      * Event to schedule sending of responses
 157      */
 158     EventFunctionWrapper sendResponseEvent;
 159
 160     /**
 161      * Progress the controller one clock cycle.
 162      */
 163     void tick();
 164
 165     /**
 166      * Event to schedule clock ticks
 167      */
 168     EventFunctionWrapper tickEvent;
 169
 170     /**
 171      * Upstream caches need this packet until true is returned, so
 172      * hold it for deletion until a subsequent call
 173      */
 174     std::unique_ptr<Packet> pendingDelete;
 175
 176   public:
 177
 178     typedef DRAMsim3Params Params;
 179     DRAMsim3(const Params &p);
 180
 181     /**
 182      * Read completion callback.
 183      *
 184      * @param id Channel id of the responder
 185      * @param addr Address of the request
 186      * @param cycle Internal cycle count of DRAMsim3
 187      */
 188     void readComplete(unsigned id, uint64_t addr);
 189
 190     /**
 191      * Write completion callback.
 192      *
 193      * @param id Channel id of the responder
 194      * @param addr Address of the request
 195      * @param cycle Internal cycle count of DRAMsim3
 196      */
 197     void writeComplete(unsigned id, uint64_t addr);
 198
 199     DrainState drain() override;
 200
 201     virtual Port& getPort(const std::string& if_name,
 202                           PortID idx = InvalidPortID) override;
 203
 204     void init() override;
 205     void startup() override;
 206
 207     void resetStats() override;
 208
 209   protected:
 210
 211     Tick recvAtomic(PacketPtr pkt);
 212     void recvFunctional(PacketPtr pkt);
 213     bool recvTimingReq(PacketPtr pkt);
 214     void recvRespRetry();
 215
 216 };
 217
 218 #endif // __MEM_DRAMSIM3_HH__