src/mem/dramsim3_wrapper.cc

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  */
  38
  39 #include <cassert>
  40
  41 /**
  42  * When building the debug binary, we need to undo the command-line
  43  * definition of DEBUG not to clash with DRAMsim3 print macros that
  44  * are included for no obvious reason.
  45  */
  46 #ifdef DEBUG
  47 #undef DEBUG
  48 #endif
  49
  50 #include "mem/dramsim3_wrapper.hh"
  51
  52 #include <fstream>
  53
  54 #include "DRAMsim3/src/dramsim3.h"
  55 #include "base/compiler.hh"
  56 #include "base/logging.hh"
  57
  58 DRAMsim3Wrapper::DRAMsim3Wrapper(const std::string& config_file,
  59                                  const std::string& working_dir,
  60                                  std::function<void(uint64_t)> read_cb,
  61                                  std::function<void(uint64_t)> write_cb) :
  62     dramsim(dramsim3::GetMemorySystem(config_file, working_dir,
  63                                        read_cb, write_cb)),
  64     _clockPeriod(0.0), _queueSize(0), _burstSize(0)
  65 {
  66     // there is no way of getting DRAMsim3 to tell us what frequency
  67     // it is assuming, so we have to extract it ourselves
  68     _clockPeriod = dramsim->GetTCK();
  69
  70     if (!_clockPeriod)
  71         fatal("DRAMsim3 wrapper failed to get clock\n");
  72
  73     // we also need to know what transaction queue size DRAMsim3 is
  74     // using so we can stall when responses are blocked
  75     _queueSize = dramsim->GetQueueSize();
  76
  77     if (!_queueSize)
  78         fatal("DRAMsim3 wrapper failed to get queue size\n");
  79
  80
  81    // finally, get the data bus bits and burst length so we can add a
  82    // sanity check for the burst size
  83    unsigned int dataBusBits = dramsim->GetBusBits();
  84    unsigned int burstLength = dramsim->GetBurstLength();
  85
  86    if (!dataBusBits || !burstLength)
  87        fatal("DRAMsim3 wrapper failed to get burst size\n");
  88
  89    _burstSize = dataBusBits * burstLength / 8;
  90 }
  91
  92 DRAMsim3Wrapper::~DRAMsim3Wrapper()
  93 {
  94     delete dramsim;
  95 }
  96
  97
  98 void
  99 DRAMsim3Wrapper::printStats()
 100 {
 101     dramsim->PrintStats();
 102 }
 103
 104 void
 105 DRAMsim3Wrapper::resetStats()
 106 {
 107     dramsim->ResetStats();
 108 }
 109
 110 void
 111 DRAMsim3Wrapper::setCallbacks(std::function<void(uint64_t)> read_complete,
 112                               std::function<void(uint64_t)> write_complete)
 113 {
 114     dramsim->RegisterCallbacks(read_complete, write_complete);
 115 }
 116
 117 bool
 118 DRAMsim3Wrapper::canAccept(uint64_t addr, bool is_write) const
 119 {
 120     return dramsim->WillAcceptTransaction(addr, is_write);
 121 }
 122
 123 void
 124 DRAMsim3Wrapper::enqueue(uint64_t addr, bool is_write)
 125 {
 126     M5_VAR_USED bool success = dramsim->AddTransaction(addr, is_write);
 127     assert(success);
 128 }
 129
 130 double
 131 DRAMsim3Wrapper::clockPeriod() const
 132 {
 133     return _clockPeriod;
 134 }
 135
 136 unsigned int
 137 DRAMsim3Wrapper::queueSize() const
 138 {
 139     return _queueSize;
 140 }
 141
 142 unsigned int
 143 DRAMsim3Wrapper::burstSize() const
 144 {
 145     return _burstSize;
 146 }
 147
 148 void
 149 DRAMsim3Wrapper::tick()
 150 {
 151     dramsim->ClockTick();
 152 }
 153