src/mem/dramsim3_wrapper.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  */
  38
  39 /**
  40  * @file
  41  * DRAMsim3Wrapper declaration
  42  */
  43
  44 #ifndef __MEM_DRAMSIM3_WRAPPER_HH__
  45 #define __MEM_DRAMSIM3_WRAPPER_HH__
  46
  47 #include <functional>
  48 #include <string>
  49
  50 /**
  51  * Forward declaration to avoid includes
  52  */
  53 namespace dramsim3 {
  54
  55 class MemorySystem;
  56
  57 }
  58
  59 /**
  60  * Wrapper class to avoid having DRAMsim3 names like ClockDomain etc
  61  * clashing with the normal gem5 world. Many of the DRAMsim3 headers
  62  * do not make use of namespaces, and quite a few also open up
  63  * std. The only thing that needs to be exposed externally are the
  64  * callbacks. This wrapper effectively avoids clashes by not including
  65  * any of the conventional gem5 headers (e.g. Packet or SimObject).
  66  */
  67 class DRAMsim3Wrapper
  68 {
  69
  70   private:
  71
  72     dramsim3::MemorySystem* dramsim;
  73
  74     double _clockPeriod;
  75
  76     unsigned int _queueSize;
  77
  78     unsigned int _burstSize;
  79
  80     template <typename T>
  81     T extractConfig(const std::string& field_name,
  82                     const std::string& file_name) const;
  83
  84   public:
  85
  86     /**
  87      * Create an instance of the DRAMsim3 multi-channel memory
  88      * controller using a specific config and system description.
  89      *
  90      * @param config_file Memory config file
  91      * @param working_dir Path pre-pended to config files
  92      */
  93     DRAMsim3Wrapper(const std::string& config_file,
  94                     const std::string& working_dir,
  95                     std::function<void(uint64_t)> read_cb,
  96                     std::function<void(uint64_t)> write_cb);
  97     ~DRAMsim3Wrapper();
  98
  99     /**
 100      * Print the stats gathered in DRAMsim3.
 101      */
 102     void printStats();
 103
 104     /**
 105      * Reset stats (useful for fastforwarding switch)
 106      */
 107     void resetStats();
 108
 109     /**
 110      * Set the callbacks to use for read and write completion.
 111      *
 112      * @param read_callback Callback used for read completions
 113      * @param write_callback Callback used for write completions
 114      */
 115     void setCallbacks(std::function<void(uint64_t)> read_complete,
 116                       std::function<void(uint64_t)> write_complete);
 117
 118     /**
 119      * Determine if the controller can accept a new packet or not.
 120      *
 121      * @return true if the controller can accept transactions
 122      */
 123     bool canAccept(uint64_t addr, bool is_write) const;
 124
 125     /**
 126      * Enqueue a packet. This assumes that canAccept has returned true.
 127      *
 128      * @param pkt Packet to turn into a DRAMsim3 transaction
 129      */
 130     void enqueue(uint64_t addr, bool is_write);
 131
 132     /**
 133      * Get the internal clock period used by DRAMsim3, specified in
 134      * ns.
 135      *
 136      * @return The clock period of the DRAM interface in ns
 137      */
 138     double clockPeriod() const;
 139
 140     /**
 141      * Get the transaction queue size used by DRAMsim3.
 142      *
 143      * @return The queue size counted in number of transactions
 144      */
 145     unsigned int queueSize() const;
 146
 147     /**
 148      * Get the burst size in bytes used by DRAMsim3.
 149      *
 150      * @return The burst size in bytes (data width * burst length)
 151      */
 152     unsigned int burstSize() const;
 153
 154     /**
 155      * Progress the memory controller one cycle
 156      */
 157     void tick();
 158 };
 159
 160 #endif //__MEM_DRAMSIM3_WRAPPER_HH__