src/mem/external_master.hh

   1 /*
   2  * Copyright (c) 2012-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Andrew Bardsley
  38  *          Curtis Dunham
  39  */
  40
  41 /**
  42  * @file
  43  *
  44  * ExternalMaster is a memory object representing a binding from
  45  * a gem5 slave to a master port in a system external to gem5.
  46  *
  47  * During initialisation, a `handler' for the port type specified in the
  48  * port's port_type parameter is found from the registered port handlers
  49  * provided with registerHandler.  Once a handler is found, it is passed the
  50  * port_data parameter of the port which can be used to identify the external
  51  * port which is to be bound to.  A port handler will usually construct a
  52  * bridge object in the external system to accomodate the port-to-port
  53  * mapping but this bridge is not exposed to gem5 other than be the
  54  * presentation of the MasterPort which can be bound.
  55  *
  56  * The external port must provide a gem5 MasterPort interface.
  57  */
  58
  59 #ifndef __MEM_EXTERNAL_MASTER__
  60 #define __MEM_EXTERNAL_MASTER__
  61
  62 #include "mem/mem_object.hh"
  63 #include "params/ExternalMaster.hh"
  64
  65 class ExternalMaster : public MemObject
  66 {
  67   public:
  68     /** Derive from this class to create an external port interface */
  69     class Port : public MasterPort
  70     {
  71       protected:
  72         ExternalMaster &owner;
  73
  74       public:
  75         Port(const std::string &name_,
  76             ExternalMaster &owner_) :
  77             MasterPort(name_, &owner_), owner(owner_)
  78         { }
  79
  80         ~Port() { }
  81
  82         /** Any or all of recv... can be overloaded to provide the port's
  83          *  functionality */
  84     };
  85
  86     /* Handlers are specific to *types* of port not specific port
  87      * instantiations.  A handler will typically build a bridge to the
  88      * external port from gem5 and provide gem5 with a MasterPort that can be
  89      * bound to for each call to Handler::getExternalPort.*/
  90     class Handler
  91     {
  92       public:
  93         /** Create or find an external port which can be bound.  Returns
  94          *  NULL on failure */
  95         virtual Port *getExternalPort(
  96             const std::string &name, ExternalMaster &owner,
  97             const std::string &port_data) = 0;
  98     };
  99
 100   protected:
 101     /** The peer port for the gem5 port "port" */
 102     Port *externalPort;
 103
 104     /** Name of the bound port.  This will be name() + ".port" */
 105     std::string portName;
 106
 107     /** Key to select a port handler */
 108     std::string portType;
 109
 110     /** Handler-specific port configuration */
 111     std::string portData;
 112
 113     /** Registered handlers.  Handlers are chosen using the port_type
 114      *  parameter on ExternalMasters.  port_types form a global namespace
 115      *  across the simulation and so handlers are registered into a global
 116      *  structure */
 117     static std::map<std::string, Handler *> portHandlers;
 118
 119   public:
 120     ExternalMaster(ExternalMasterParams *params);
 121
 122     /** MasterPort interface.  Responds only to port "port" */
 123     BaseMasterPort &getMasterPort(const std::string &if_name,
 124         PortID idx = InvalidPortID);
 125
 126     /** Register a handler which can provide ports with port_type ==
 127      *  handler_name */
 128     static void registerHandler(const std::string &handler_name,
 129         Handler *handler);
 130
 131     void init();
 132 };
 133
 134
 135 #endif // __MEM_EXTERNAL_MASTER__