cpu: fix bug when TrafficGen deschedules event
[gem5.git] / src / mem / fs_translating_port_proxy.cc
1 /*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Andreas Hansson
42 */
43
44 /**
45 * @file
46 * Port object definitions.
47 */
48
49 #include "arch/vtophys.hh"
50 #include "base/chunk_generator.hh"
51 #include "cpu/base.hh"
52 #include "cpu/thread_context.hh"
53 #include "mem/fs_translating_port_proxy.hh"
54 #include "sim/system.hh"
55
56 using namespace TheISA;
57
58 FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc)
59 : PortProxy(tc->getCpuPtr()->getDataPort(),
60 tc->getSystemPtr()->cacheLineSize()), _tc(tc)
61 {
62 }
63
64 FSTranslatingPortProxy::FSTranslatingPortProxy(MasterPort &port,
65 unsigned int cacheLineSize)
66 : PortProxy(port, cacheLineSize), _tc(NULL)
67 {
68 }
69
70 FSTranslatingPortProxy::~FSTranslatingPortProxy()
71 {
72 }
73
74 void
75 FSTranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size) const
76 {
77 Addr paddr;
78 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
79 gen.next())
80 {
81 if (_tc)
82 paddr = TheISA::vtophys(_tc,gen.addr());
83 else
84 paddr = TheISA::vtophys(gen.addr());
85
86 PortProxy::readBlob(paddr, p, gen.size());
87 p += gen.size();
88 }
89 }
90
91 void
92 FSTranslatingPortProxy::writeBlob(Addr addr, uint8_t *p, int size) const
93 {
94 Addr paddr;
95 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
96 gen.next())
97 {
98 if (_tc)
99 paddr = TheISA::vtophys(_tc,gen.addr());
100 else
101 paddr = TheISA::vtophys(gen.addr());
102
103 PortProxy::writeBlob(paddr, p, gen.size());
104 p += gen.size();
105 }
106 }
107
108 void
109 FSTranslatingPortProxy::memsetBlob(Addr address, uint8_t v, int size) const
110 {
111 Addr paddr;
112 for (ChunkGenerator gen(address, size, TheISA::PageBytes); !gen.done();
113 gen.next())
114 {
115 if (_tc)
116 paddr = TheISA::vtophys(_tc,gen.addr());
117 else
118 paddr = TheISA::vtophys(gen.addr());
119
120 PortProxy::memsetBlob(paddr, v, gen.size());
121 }
122 }
123
124 void
125 CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
126 {
127 uint8_t *dst = (uint8_t *)dest;
128 tc->getVirtProxy().readBlob(src, dst, cplen);
129 }
130
131 void
132 CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
133 {
134 uint8_t *src = (uint8_t *)source;
135 tc->getVirtProxy().writeBlob(dest, src, cplen);
136 }
137
138 void
139 CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
140 {
141 char *start = dst;
142 FSTranslatingPortProxy &vp = tc->getVirtProxy();
143
144 bool foundNull = false;
145 while ((dst - start + 1) < maxlen && !foundNull) {
146 vp.readBlob(vaddr++, (uint8_t*)dst, 1);
147 if (*dst == '\0')
148 foundNull = true;
149 dst++;
150 }
151
152 if (!foundNull)
153 *dst = '\0';
154 }
155
156 void
157 CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
158 {
159 FSTranslatingPortProxy &vp = tc->getVirtProxy();
160 for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done();
161 gen.next())
162 {
163 vp.writeBlob(gen.addr(), (uint8_t*)src, gen.size());
164 src += gen.size();
165 }
166 }