src/mem/hmc_controller.hh

   1 /*
   2  * Copyright (c) 2011-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2015 The University of Bologna
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41
  42 /**
  43  * @file
  44  * HMCController declaration
  45  */
  46
  47 #ifndef __MEM_HMC_CONTROLLER_HH__
  48 #define __MEM_HMC_CONTROLLER_HH__
  49
  50 #include "mem/noncoherent_xbar.hh"
  51 #include "mem/port.hh"
  52 #include "params/HMCController.hh"
  53
  54 /**
  55  * HMC Controller, in general, is responsible for translating the host
  56  * protocol (AXI for example) to serial links protocol. Plus, it should have
  57  * large internal buffers to hide the access latency of the cube. It is also
  58  * inferred from the standard [1] and the literature [2] that serial links
  59  * share the same address range and packets can travel over any of them, so a
  60  * load distribution mechanism is required.
  61  * This model simply queues the incoming transactions (using a Bridge) and
  62  * schedules them to the serial links using a simple round robin mechanism to
  63  * balance the load among them. More advanced global scheduling policies and
  64  * reordering and steering of transactions can be added to this model if
  65  * required [3].
  66  * [1] http://www.hybridmemorycube.org/specification-download/
  67  * [2] Low-Power Hybrid Memory Cubes With Link Power Manageme and Two-Level
  68  * Prefetching (J. Ahn et. al)
  69  * [3] The Open-Silicon HMC Controller IP
  70  * http://www.open-silicon.com/open-silicon-ips/hmc/
  71  */
  72
  73 class HMCController : public NoncoherentXBar
  74 {
  75 public:
  76
  77     HMCController(const HMCControllerParams &p);
  78
  79 private:
  80
  81     // Receive range change only on one of the ports (because they all have
  82     //  the same range)
  83     virtual void recvRangeChange(PortID mem_side_port_id);
  84
  85     // Receive a request and distribute it among response ports
  86     //  Simply forwards the packet to the next serial link based on a
  87     //  Round-robin counter
  88     virtual bool recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id);
  89
  90     int numMemSidePorts;
  91
  92     // The round-robin counter
  93     int rr_counter;
  94     /**
  95      * Function for rotating the round robin counter
  96      * @return the next value of the counter
  97      */
  98     int rotate_counter();
  99 };
 100
 101 #endif //__MEM_HMC_CONTROLLER_HH__