2 * Copyright (c) 2012-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Thomas Grass
42 #include "mem/mem_checker_monitor.hh"
46 #include "base/logging.hh"
47 #include "base/output.hh"
48 #include "base/trace.hh"
49 #include "debug/MemCheckerMonitor.hh"
51 MemCheckerMonitor::MemCheckerMonitor(Params
* params
)
53 masterPort(name() + "-master", *this),
54 slavePort(name() + "-slave", *this),
55 warnOnly(params
->warn_only
),
56 memchecker(params
->memchecker
)
59 MemCheckerMonitor::~MemCheckerMonitor()
63 MemCheckerMonitorParams::create()
65 return new MemCheckerMonitor(this);
69 MemCheckerMonitor::init()
71 // make sure both sides of the monitor are connected
72 if (!slavePort
.isConnected() || !masterPort
.isConnected())
73 fatal("Communication monitor is not connected on both sides.\n");
77 MemCheckerMonitor::getMasterPort(const std::string
& if_name
, PortID idx
)
79 if (if_name
== "master" || if_name
== "mem_side") {
82 return MemObject::getMasterPort(if_name
, idx
);
87 MemCheckerMonitor::getSlavePort(const std::string
& if_name
, PortID idx
)
89 if (if_name
== "slave" || if_name
== "cpu_side") {
92 return MemObject::getSlavePort(if_name
, idx
);
97 MemCheckerMonitor::recvFunctional(PacketPtr pkt
)
99 Addr addr
= pkt
->getAddr();
100 unsigned size
= pkt
->getSize();
102 // Conservatively reset this address-range. Alternatively we could try to
103 // update the values seen by the memchecker, however, there may be other
104 // reads/writes to these location from other devices we do not see.
105 memchecker
->reset(addr
, size
);
107 masterPort
.sendFunctional(pkt
);
109 DPRINTF(MemCheckerMonitor
,
110 "Forwarded functional access: addr = %#llx, size = %d\n",
115 MemCheckerMonitor::recvFunctionalSnoop(PacketPtr pkt
)
117 Addr addr
= pkt
->getAddr();
118 unsigned size
= pkt
->getSize();
121 memchecker
->reset(addr
, size
);
123 slavePort
.sendFunctionalSnoop(pkt
);
125 DPRINTF(MemCheckerMonitor
,
126 "Received functional snoop: addr = %#llx, size = %d\n",
131 MemCheckerMonitor::recvAtomic(PacketPtr pkt
)
133 panic("Atomic not supported");
137 MemCheckerMonitor::recvAtomicSnoop(PacketPtr pkt
)
139 panic("Atomic not supported");
143 MemCheckerMonitor::recvTimingReq(PacketPtr pkt
)
145 // should always see a request
146 assert(pkt
->isRequest());
148 // Store relevant fields of packet, because packet may be modified
149 // or even deleted when sendTiming() is called.
151 // For reads we are only interested in real reads, and not prefetches, as
152 // it is not guaranteed that the prefetch returns any useful data.
153 bool is_read
= pkt
->isRead() && !pkt
->req
->isPrefetch();
154 bool is_write
= pkt
->isWrite();
155 unsigned size
= pkt
->getSize();
156 Addr addr
= pkt
->getAddr();
157 bool expects_response
= pkt
->needsResponse() && !pkt
->cacheResponding();
158 std::unique_ptr
<uint8_t[]> pkt_data
;
159 MemCheckerMonitorSenderState
* state
= NULL
;
161 if (expects_response
&& is_write
) {
162 // On receipt of a request, only need to allocate pkt_data if this is a
163 // write. For reads, we have no data yet, so it doesn't make sense to
165 pkt_data
.reset(new uint8_t[size
]);
166 pkt
->writeData(pkt_data
.get());
169 // If a cache miss is served by a cache, a monitor near the memory
170 // would see a request which needs a response, but this response
171 // would not come back from the memory. Therefore
172 // we additionally have to check the inhibit flag.
173 if (expects_response
&& (is_read
|| is_write
)) {
174 state
= new MemCheckerMonitorSenderState(0);
175 pkt
->pushSenderState(state
);
178 // Attempt to send the packet
179 bool successful
= masterPort
.sendTimingReq(pkt
);
181 // If not successful, restore the sender state
182 if (!successful
&& expects_response
&& (is_read
|| is_write
)) {
183 delete pkt
->popSenderState();
186 if (successful
&& expects_response
) {
188 MemChecker::Serial serial
= memchecker
->startRead(curTick(),
192 // At the time where we push the sender-state, we do not yet know
193 // the serial the MemChecker class will assign to this request. We
194 // cannot call startRead at the time we push the sender-state, as
195 // the masterPort may not be successful in executing sendTimingReq,
196 // and in case of a failure, we must not modify the state of the
199 // Once we know that sendTimingReq was successful, we can set the
200 // serial of the newly constructed sender-state. This is legal, as
201 // we know that nobody else will touch nor is responsible for
202 // deletion of our sender-state.
203 state
->serial
= serial
;
205 DPRINTF(MemCheckerMonitor
,
206 "Forwarded read request: serial = %d, addr = %#llx, "
209 } else if (is_write
) {
210 MemChecker::Serial serial
= memchecker
->startWrite(curTick(),
215 state
->serial
= serial
;
217 DPRINTF(MemCheckerMonitor
,
218 "Forwarded write request: serial = %d, addr = %#llx, "
222 DPRINTF(MemCheckerMonitor
,
223 "Forwarded non read/write request: addr = %#llx\n", addr
);
225 } else if (successful
) {
226 DPRINTF(MemCheckerMonitor
,
227 "Forwarded request marked for cache response: addr = %#llx\n",
235 MemCheckerMonitor::recvTimingResp(PacketPtr pkt
)
237 // should always see responses
238 assert(pkt
->isResponse());
240 // Store relevant fields of packet, because packet may be modified
241 // or even deleted when sendTiming() is called.
242 bool is_read
= pkt
->isRead() && !pkt
->req
->isPrefetch();
243 bool is_write
= pkt
->isWrite();
244 bool is_failed_LLSC
= pkt
->isLLSC() && pkt
->req
->getExtraData() == 0;
245 unsigned size
= pkt
->getSize();
246 Addr addr
= pkt
->getAddr();
247 std::unique_ptr
<uint8_t[]> pkt_data
;
248 MemCheckerMonitorSenderState
* received_state
= NULL
;
251 // On receipt of a response, only need to allocate pkt_data if this is
252 // a read. For writes, we have already given the MemChecker the data on
253 // the request, so it doesn't make sense to allocate on write.
254 pkt_data
.reset(new uint8_t[size
]);
255 pkt
->writeData(pkt_data
.get());
258 if (is_read
|| is_write
) {
260 dynamic_cast<MemCheckerMonitorSenderState
*>(pkt
->senderState
);
262 // Restore initial sender state
263 panic_if(received_state
== NULL
,
264 "Monitor got a response without monitor sender state\n");
267 pkt
->senderState
= received_state
->predecessor
;
270 // Attempt to send the packet
271 bool successful
= slavePort
.sendTimingResp(pkt
);
273 // If packet successfully send, complete transaction in MemChecker
274 // instance, and delete sender state, otherwise restore state.
277 DPRINTF(MemCheckerMonitor
,
278 "Received read response: serial = %d, addr = %#llx, "
280 received_state
->serial
, addr
, size
);
282 bool result
= memchecker
->completeRead(received_state
->serial
,
289 warn("%s: read of %#llx @ cycle %d failed:\n%s\n",
292 memchecker
->getErrorMessage().c_str());
294 panic_if(!warnOnly
, "MemChecker violation!");
297 delete received_state
;
298 } else if (is_write
) {
299 DPRINTF(MemCheckerMonitor
,
300 "Received write response: serial = %d, addr = %#llx, "
302 received_state
->serial
, addr
, size
);
304 if (is_failed_LLSC
) {
305 // The write was not successful, let MemChecker know.
306 memchecker
->abortWrite(received_state
->serial
,
310 memchecker
->completeWrite(received_state
->serial
,
316 delete received_state
;
318 DPRINTF(MemCheckerMonitor
,
319 "Received non read/write response: addr = %#llx\n", addr
);
321 } else if (is_read
|| is_write
) {
322 // Don't delete anything and let the packet look like we
324 pkt
->senderState
= received_state
;
331 MemCheckerMonitor::recvTimingSnoopReq(PacketPtr pkt
)
333 slavePort
.sendTimingSnoopReq(pkt
);
337 MemCheckerMonitor::recvTimingSnoopResp(PacketPtr pkt
)
339 return masterPort
.sendTimingSnoopResp(pkt
);
343 MemCheckerMonitor::isSnooping() const
345 // check if the connected master port is snooping
346 return slavePort
.isSnooping();
350 MemCheckerMonitor::getAddrRanges() const
352 // get the address ranges of the connected slave port
353 return masterPort
.getAddrRanges();
357 MemCheckerMonitor::recvReqRetry()
359 slavePort
.sendRetryReq();
363 MemCheckerMonitor::recvRespRetry()
365 masterPort
.sendRetryResp();
369 MemCheckerMonitor::recvRangeChange()
371 slavePort
.sendRangeChange();