src/mem/mem_checker_monitor.hh

   1 /*
   2  * Copyright (c) 2012-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __MEM_MEM_CHECKER_MONITOR_HH__
  39 #define __MEM_MEM_CHECKER_MONITOR_HH__
  40
  41 #include "base/statistics.hh"
  42 #include "mem/mem_checker.hh"
  43 #include "params/MemCheckerMonitor.hh"
  44 #include "sim/sim_object.hh"
  45 #include "sim/system.hh"
  46
  47 /**
  48  * Implements a MemChecker monitor, to be inserted between two ports.
  49  */
  50 class MemCheckerMonitor : public SimObject
  51 {
  52   public:
  53
  54     /** Parameters of memchecker monitor */
  55     typedef MemCheckerMonitorParams Params;
  56     const Params* params() const
  57     { return reinterpret_cast<const Params*>(_params); }
  58
  59     /**
  60      * Constructor based on the Python params
  61      *
  62      * @param params Python parameters
  63      */
  64     MemCheckerMonitor(Params* params);
  65
  66     /** Destructor */
  67     ~MemCheckerMonitor();
  68
  69     Port &getPort(const std::string &if_name,
  70                   PortID idx=InvalidPortID) override;
  71
  72     void init() override;
  73
  74   private:
  75
  76     struct MemCheckerMonitorSenderState : public Packet::SenderState
  77     {
  78         MemCheckerMonitorSenderState(MemChecker::Serial _serial)
  79             : serial(_serial)
  80         {}
  81
  82         MemChecker::Serial serial;
  83     };
  84
  85     /**
  86      * This is the master port of the communication monitor. All recv
  87      * functions call a function in MemCheckerMonitor, where the
  88      * send function of the slave port is called. Besides this, these
  89      * functions can also perform actions for capturing statistics.
  90      */
  91     class MonitorMasterPort : public RequestPort
  92     {
  93
  94       public:
  95
  96         MonitorMasterPort(const std::string& _name, MemCheckerMonitor& _mon)
  97             : RequestPort(_name, &_mon), mon(_mon)
  98         { }
  99
 100       protected:
 101
 102         void recvFunctionalSnoop(PacketPtr pkt)
 103         {
 104             mon.recvFunctionalSnoop(pkt);
 105         }
 106
 107         Tick recvAtomicSnoop(PacketPtr pkt)
 108         {
 109             return mon.recvAtomicSnoop(pkt);
 110         }
 111
 112         bool recvTimingResp(PacketPtr pkt)
 113         {
 114             return mon.recvTimingResp(pkt);
 115         }
 116
 117         void recvTimingSnoopReq(PacketPtr pkt)
 118         {
 119             mon.recvTimingSnoopReq(pkt);
 120         }
 121
 122         void recvRangeChange()
 123         {
 124             mon.recvRangeChange();
 125         }
 126
 127         bool isSnooping() const
 128         {
 129             return mon.isSnooping();
 130         }
 131
 132         void recvReqRetry()
 133         {
 134             mon.recvReqRetry();
 135         }
 136
 137       private:
 138
 139         MemCheckerMonitor& mon;
 140
 141     };
 142
 143     /** Instance of master port, facing the memory side */
 144     MonitorMasterPort masterPort;
 145
 146     /**
 147      * This is the slave port of the communication monitor. All recv
 148      * functions call a function in MemCheckerMonitor, where the
 149      * send function of the master port is called. Besides this, these
 150      * functions can also perform actions for capturing statistics.
 151      */
 152     class MonitorSlavePort : public ResponsePort
 153     {
 154
 155       public:
 156
 157         MonitorSlavePort(const std::string& _name, MemCheckerMonitor& _mon)
 158             : ResponsePort(_name, &_mon), mon(_mon)
 159         { }
 160
 161       protected:
 162
 163         void recvFunctional(PacketPtr pkt)
 164         {
 165             mon.recvFunctional(pkt);
 166         }
 167
 168         Tick recvAtomic(PacketPtr pkt)
 169         {
 170             return mon.recvAtomic(pkt);
 171         }
 172
 173         bool recvTimingReq(PacketPtr pkt)
 174         {
 175             return mon.recvTimingReq(pkt);
 176         }
 177
 178         bool recvTimingSnoopResp(PacketPtr pkt)
 179         {
 180             return mon.recvTimingSnoopResp(pkt);
 181         }
 182
 183         AddrRangeList getAddrRanges() const
 184         {
 185             return mon.getAddrRanges();
 186         }
 187
 188         void recvRespRetry()
 189         {
 190             mon.recvRespRetry();
 191         }
 192
 193       private:
 194
 195         MemCheckerMonitor& mon;
 196
 197     };
 198
 199     /** Instance of slave port, i.e. on the CPU side */
 200     MonitorSlavePort slavePort;
 201
 202     void recvFunctional(PacketPtr pkt);
 203
 204     void recvFunctionalSnoop(PacketPtr pkt);
 205
 206     Tick recvAtomic(PacketPtr pkt);
 207
 208     Tick recvAtomicSnoop(PacketPtr pkt);
 209
 210     bool recvTimingReq(PacketPtr pkt);
 211
 212     bool recvTimingResp(PacketPtr pkt);
 213
 214     void recvTimingSnoopReq(PacketPtr pkt);
 215
 216     bool recvTimingSnoopResp(PacketPtr pkt);
 217
 218     AddrRangeList getAddrRanges() const;
 219
 220     bool isSnooping() const;
 221
 222     void recvReqRetry();
 223
 224     void recvRespRetry();
 225
 226     void recvRangeChange();
 227
 228     bool warnOnly;
 229
 230     MemChecker *memchecker;
 231 };
 232
 233 #endif //__MEM_MEM_CHECKER_MONITOR_HH__