src/mem/mem_ctrl.hh

   1 /*
   2  * Copyright (c) 2012-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2013 Amin Farmahini-Farahani
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /**
  42  * @file
  43  * MemCtrl declaration
  44  */
  45
  46 #ifndef __MEM_CTRL_HH__
  47 #define __MEM_CTRL_HH__
  48
  49 #include <deque>
  50 #include <string>
  51 #include <unordered_set>
  52 #include <utility>
  53 #include <vector>
  54
  55 #include "base/callback.hh"
  56 #include "base/statistics.hh"
  57 #include "enums/MemSched.hh"
  58 #include "mem/qos/mem_ctrl.hh"
  59 #include "mem/qport.hh"
  60 #include "params/MemCtrl.hh"
  61 #include "sim/eventq.hh"
  62
  63 class DRAMInterface;
  64 class NVMInterface;
  65
  66 /**
  67  * A burst helper helps organize and manage a packet that is larger than
  68  * the memory burst size. A system packet that is larger than the burst size
  69  * is split into multiple packets and all those packets point to
  70  * a single burst helper such that we know when the whole packet is served.
  71  */
  72 class BurstHelper
  73 {
  74   public:
  75
  76     /** Number of bursts requred for a system packet **/
  77     const unsigned int burstCount;
  78
  79     /** Number of bursts serviced so far for a system packet **/
  80     unsigned int burstsServiced;
  81
  82     BurstHelper(unsigned int _burstCount)
  83         : burstCount(_burstCount), burstsServiced(0)
  84     { }
  85 };
  86
  87 /**
  88  * A memory packet stores packets along with the timestamp of when
  89  * the packet entered the queue, and also the decoded address.
  90  */
  91 class MemPacket
  92 {
  93   public:
  94
  95     /** When did request enter the controller */
  96     const Tick entryTime;
  97
  98     /** When will request leave the controller */
  99     Tick readyTime;
 100
 101     /** This comes from the outside world */
 102     const PacketPtr pkt;
 103
 104     /** RequestorID associated with the packet */
 105     const RequestorID _requestorId;
 106
 107     const bool read;
 108
 109     /** Does this packet access DRAM?*/
 110     const bool dram;
 111
 112     /** Will be populated by address decoder */
 113     const uint8_t rank;
 114     const uint8_t bank;
 115     const uint32_t row;
 116
 117     /**
 118      * Bank id is calculated considering banks in all the ranks
 119      * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
 120      * bankId = 8 --> rank1, bank0
 121      */
 122     const uint16_t bankId;
 123
 124     /**
 125      * The starting address of the packet.
 126      * This address could be unaligned to burst size boundaries. The
 127      * reason is to keep the address offset so we can accurately check
 128      * incoming read packets with packets in the write queue.
 129      */
 130     Addr addr;
 131
 132     /**
 133      * The size of this dram packet in bytes
 134      * It is always equal or smaller than the burst size
 135      */
 136     unsigned int size;
 137
 138     /**
 139      * A pointer to the BurstHelper if this MemPacket is a split packet
 140      * If not a split packet (common case), this is set to NULL
 141      */
 142     BurstHelper* burstHelper;
 143
 144     /**
 145      * QoS value of the encapsulated packet read at queuing time
 146      */
 147     uint8_t _qosValue;
 148
 149     /**
 150      * Set the packet QoS value
 151      * (interface compatibility with Packet)
 152      */
 153     inline void qosValue(const uint8_t qv) { _qosValue = qv; }
 154
 155     /**
 156      * Get the packet QoS value
 157      * (interface compatibility with Packet)
 158      */
 159     inline uint8_t qosValue() const { return _qosValue; }
 160
 161     /**
 162      * Get the packet RequestorID
 163      * (interface compatibility with Packet)
 164      */
 165     inline RequestorID requestorId() const { return _requestorId; }
 166
 167     /**
 168      * Get the packet size
 169      * (interface compatibility with Packet)
 170      */
 171     inline unsigned int getSize() const { return size; }
 172
 173     /**
 174      * Get the packet address
 175      * (interface compatibility with Packet)
 176      */
 177     inline Addr getAddr() const { return addr; }
 178
 179     /**
 180      * Return true if its a read packet
 181      * (interface compatibility with Packet)
 182      */
 183     inline bool isRead() const { return read; }
 184
 185     /**
 186      * Return true if its a write packet
 187      * (interface compatibility with Packet)
 188      */
 189     inline bool isWrite() const { return !read; }
 190
 191     /**
 192      * Return true if its a DRAM access
 193      */
 194     inline bool isDram() const { return dram; }
 195
 196     MemPacket(PacketPtr _pkt, bool is_read, bool is_dram, uint8_t _rank,
 197                uint8_t _bank, uint32_t _row, uint16_t bank_id, Addr _addr,
 198                unsigned int _size)
 199         : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
 200           _requestorId(pkt->requestorId()),
 201           read(is_read), dram(is_dram), rank(_rank), bank(_bank), row(_row),
 202           bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
 203           _qosValue(_pkt->qosValue())
 204     { }
 205
 206 };
 207
 208 // The memory packets are store in a multiple dequeue structure,
 209 // based on their QoS priority
 210 typedef std::deque<MemPacket*> MemPacketQueue;
 211
 212
 213 /**
 214  * The memory controller is a single-channel memory controller capturing
 215  * the most important timing constraints associated with a
 216  * contemporary controller. For multi-channel memory systems, the controller
 217  * is combined with a crossbar model, with the channel address
 218  * interleaving taking part in the crossbar.
 219  *
 220  * As a basic design principle, this controller
 221  * model is not cycle callable, but instead uses events to: 1) decide
 222  * when new decisions can be made, 2) when resources become available,
 223  * 3) when things are to be considered done, and 4) when to send
 224  * things back. The controller interfaces to media specific interfaces
 225  * to enable flexible topoloties.
 226  * Through these simple principles, the model delivers
 227  * high performance, and lots of flexibility, allowing users to
 228  * evaluate the system impact of a wide range of memory technologies.
 229  *
 230  * For more details, please see Hansson et al, "Simulating DRAM
 231  * controllers for future system architecture exploration",
 232  * Proc. ISPASS, 2014. If you use this model as part of your research
 233  * please cite the paper.
 234  *
 235  */
 236 class MemCtrl : public QoS::MemCtrl
 237 {
 238   private:
 239
 240     // For now, make use of a queued response port to avoid dealing with
 241     // flow control for the responses being sent back
 242     class MemoryPort : public QueuedResponsePort
 243     {
 244
 245         RespPacketQueue queue;
 246         MemCtrl& ctrl;
 247
 248       public:
 249
 250         MemoryPort(const std::string& name, MemCtrl& _ctrl);
 251
 252       protected:
 253
 254         Tick recvAtomic(PacketPtr pkt);
 255
 256         void recvFunctional(PacketPtr pkt);
 257
 258         bool recvTimingReq(PacketPtr);
 259
 260         virtual AddrRangeList getAddrRanges() const;
 261
 262     };
 263
 264     /**
 265      * Our incoming port, for a multi-ported controller add a crossbar
 266      * in front of it
 267      */
 268     MemoryPort port;
 269
 270     /**
 271      * Remember if the memory system is in timing mode
 272      */
 273     bool isTimingMode;
 274
 275     /**
 276      * Remember if we have to retry a request when available.
 277      */
 278     bool retryRdReq;
 279     bool retryWrReq;
 280
 281     /**
 282      * Bunch of things requires to setup "events" in gem5
 283      * When event "respondEvent" occurs for example, the method
 284      * processRespondEvent is called; no parameters are allowed
 285      * in these methods
 286      */
 287     void processNextReqEvent();
 288     EventFunctionWrapper nextReqEvent;
 289
 290     void processRespondEvent();
 291     EventFunctionWrapper respondEvent;
 292
 293     /**
 294      * Check if the read queue has room for more entries
 295      *
 296      * @param pkt_count The number of entries needed in the read queue
 297      * @return true if read queue is full, false otherwise
 298      */
 299     bool readQueueFull(unsigned int pkt_count) const;
 300
 301     /**
 302      * Check if the write queue has room for more entries
 303      *
 304      * @param pkt_count The number of entries needed in the write queue
 305      * @return true if write queue is full, false otherwise
 306      */
 307     bool writeQueueFull(unsigned int pkt_count) const;
 308
 309     /**
 310      * When a new read comes in, first check if the write q has a
 311      * pending request to the same address.\ If not, decode the
 312      * address to populate rank/bank/row, create one or mutliple
 313      * "mem_pkt", and push them to the back of the read queue.\
 314      * If this is the only
 315      * read request in the system, schedule an event to start
 316      * servicing it.
 317      *
 318      * @param pkt The request packet from the outside world
 319      * @param pkt_count The number of memory bursts the pkt
 320      * @param is_dram Does this packet access DRAM?
 321      * translate to. If pkt size is larger then one full burst,
 322      * then pkt_count is greater than one.
 323      */
 324     void addToReadQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
 325
 326     /**
 327      * Decode the incoming pkt, create a mem_pkt and push to the
 328      * back of the write queue. \If the write q length is more than
 329      * the threshold specified by the user, ie the queue is beginning
 330      * to get full, stop reads, and start draining writes.
 331      *
 332      * @param pkt The request packet from the outside world
 333      * @param pkt_count The number of memory bursts the pkt
 334      * @param is_dram Does this packet access DRAM?
 335      * translate to. If pkt size is larger then one full burst,
 336      * then pkt_count is greater than one.
 337      */
 338     void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
 339
 340     /**
 341      * Actually do the burst based on media specific access function.
 342      * Update bus statistics when complete.
 343      *
 344      * @param mem_pkt The memory packet created from the outside world pkt
 345      */
 346     void doBurstAccess(MemPacket* mem_pkt);
 347
 348     /**
 349      * When a packet reaches its "readyTime" in the response Q,
 350      * use the "access()" method in AbstractMemory to actually
 351      * create the response packet, and send it back to the outside
 352      * world requestor.
 353      *
 354      * @param pkt The packet from the outside world
 355      * @param static_latency Static latency to add before sending the packet
 356      */
 357     void accessAndRespond(PacketPtr pkt, Tick static_latency);
 358
 359     /**
 360      * Determine if there is a packet that can issue.
 361      *
 362      * @param pkt The packet to evaluate
 363      */
 364     bool packetReady(MemPacket* pkt);
 365
 366     /**
 367      * Calculate the minimum delay used when scheduling a read-to-write
 368      * transision.
 369      * @param return minimum delay
 370      */
 371     Tick minReadToWriteDataGap();
 372
 373     /**
 374      * Calculate the minimum delay used when scheduling a write-to-read
 375      * transision.
 376      * @param return minimum delay
 377      */
 378     Tick minWriteToReadDataGap();
 379
 380     /**
 381      * The memory schduler/arbiter - picks which request needs to
 382      * go next, based on the specified policy such as FCFS or FR-FCFS
 383      * and moves it to the head of the queue.
 384      * Prioritizes accesses to the same rank as previous burst unless
 385      * controller is switching command type.
 386      *
 387      * @param queue Queued requests to consider
 388      * @param extra_col_delay Any extra delay due to a read/write switch
 389      * @return an iterator to the selected packet, else queue.end()
 390      */
 391     MemPacketQueue::iterator chooseNext(MemPacketQueue& queue,
 392         Tick extra_col_delay);
 393
 394     /**
 395      * For FR-FCFS policy reorder the read/write queue depending on row buffer
 396      * hits and earliest bursts available in memory
 397      *
 398      * @param queue Queued requests to consider
 399      * @param extra_col_delay Any extra delay due to a read/write switch
 400      * @return an iterator to the selected packet, else queue.end()
 401      */
 402     MemPacketQueue::iterator chooseNextFRFCFS(MemPacketQueue& queue,
 403             Tick extra_col_delay);
 404
 405     /**
 406      * Calculate burst window aligned tick
 407      *
 408      * @param cmd_tick Initial tick of command
 409      * @return burst window aligned tick
 410      */
 411     Tick getBurstWindow(Tick cmd_tick);
 412
 413     /**
 414      * Used for debugging to observe the contents of the queues.
 415      */
 416     void printQs() const;
 417
 418     /**
 419      * Burst-align an address.
 420      *
 421      * @param addr The potentially unaligned address
 422      * @param is_dram Does this packet access DRAM?
 423      *
 424      * @return An address aligned to a memory burst
 425      */
 426     Addr burstAlign(Addr addr, bool is_dram) const;
 427
 428     /**
 429      * The controller's main read and write queues,
 430      * with support for QoS reordering
 431      */
 432     std::vector<MemPacketQueue> readQueue;
 433     std::vector<MemPacketQueue> writeQueue;
 434
 435     /**
 436      * To avoid iterating over the write queue to check for
 437      * overlapping transactions, maintain a set of burst addresses
 438      * that are currently queued. Since we merge writes to the same
 439      * location we never have more than one address to the same burst
 440      * address.
 441      */
 442     std::unordered_set<Addr> isInWriteQueue;
 443
 444     /**
 445      * Response queue where read packets wait after we're done working
 446      * with them, but it's not time to send the response yet. The
 447      * responses are stored separately mostly to keep the code clean
 448      * and help with events scheduling. For all logical purposes such
 449      * as sizing the read queue, this and the main read queue need to
 450      * be added together.
 451      */
 452     std::deque<MemPacket*> respQueue;
 453
 454     /**
 455      * Holds count of commands issued in burst window starting at
 456      * defined Tick. This is used to ensure that the command bandwidth
 457      * does not exceed the allowable media constraints.
 458      */
 459     std::unordered_multiset<Tick> burstTicks;
 460
 461     /**
 462      * Create pointer to interface of the actual dram media when connected
 463      */
 464     DRAMInterface* const dram;
 465
 466     /**
 467      * Create pointer to interface of the actual nvm media when connected
 468      */
 469     NVMInterface* const nvm;
 470
 471     /**
 472      * The following are basic design parameters of the memory
 473      * controller, and are initialized based on parameter values.
 474      * The rowsPerBank is determined based on the capacity, number of
 475      * ranks and banks, the burst size, and the row buffer size.
 476      */
 477     const uint32_t readBufferSize;
 478     const uint32_t writeBufferSize;
 479     const uint32_t writeHighThreshold;
 480     const uint32_t writeLowThreshold;
 481     const uint32_t minWritesPerSwitch;
 482     uint32_t writesThisTime;
 483     uint32_t readsThisTime;
 484
 485     /**
 486      * Memory controller configuration initialized based on parameter
 487      * values.
 488      */
 489     Enums::MemSched memSchedPolicy;
 490
 491     /**
 492      * Pipeline latency of the controller frontend. The frontend
 493      * contribution is added to writes (that complete when they are in
 494      * the write buffer) and reads that are serviced the write buffer.
 495      */
 496     const Tick frontendLatency;
 497
 498     /**
 499      * Pipeline latency of the backend and PHY. Along with the
 500      * frontend contribution, this latency is added to reads serviced
 501      * by the memory.
 502      */
 503     const Tick backendLatency;
 504
 505     /**
 506      * Length of a command window, used to check
 507      * command bandwidth
 508      */
 509     const Tick commandWindow;
 510
 511     /**
 512      * Till when must we wait before issuing next RD/WR burst?
 513      */
 514     Tick nextBurstAt;
 515
 516     Tick prevArrival;
 517
 518     /**
 519      * The soonest you have to start thinking about the next request
 520      * is the longest access time that can occur before
 521      * nextBurstAt. Assuming you need to precharge, open a new row,
 522      * and access, it is tRP + tRCD + tCL.
 523      */
 524     Tick nextReqTime;
 525
 526     struct CtrlStats : public Stats::Group
 527     {
 528         CtrlStats(MemCtrl &ctrl);
 529
 530         void regStats() override;
 531
 532         MemCtrl &ctrl;
 533
 534         // All statistics that the model needs to capture
 535         Stats::Scalar readReqs;
 536         Stats::Scalar writeReqs;
 537         Stats::Scalar readBursts;
 538         Stats::Scalar writeBursts;
 539         Stats::Scalar servicedByWrQ;
 540         Stats::Scalar mergedWrBursts;
 541         Stats::Scalar neitherReadNorWriteReqs;
 542         // Average queue lengths
 543         Stats::Average avgRdQLen;
 544         Stats::Average avgWrQLen;
 545
 546         Stats::Scalar numRdRetry;
 547         Stats::Scalar numWrRetry;
 548         Stats::Vector readPktSize;
 549         Stats::Vector writePktSize;
 550         Stats::Vector rdQLenPdf;
 551         Stats::Vector wrQLenPdf;
 552         Stats::Histogram rdPerTurnAround;
 553         Stats::Histogram wrPerTurnAround;
 554
 555         Stats::Scalar bytesReadWrQ;
 556         Stats::Scalar bytesReadSys;
 557         Stats::Scalar bytesWrittenSys;
 558         // Average bandwidth
 559         Stats::Formula avgRdBWSys;
 560         Stats::Formula avgWrBWSys;
 561
 562         Stats::Scalar totGap;
 563         Stats::Formula avgGap;
 564
 565         // per-requestor bytes read and written to memory
 566         Stats::Vector requestorReadBytes;
 567         Stats::Vector requestorWriteBytes;
 568
 569         // per-requestor bytes read and written to memory rate
 570         Stats::Formula requestorReadRate;
 571         Stats::Formula requestorWriteRate;
 572
 573         // per-requestor read and write serviced memory accesses
 574         Stats::Vector requestorReadAccesses;
 575         Stats::Vector requestorWriteAccesses;
 576
 577         // per-requestor read and write total memory access latency
 578         Stats::Vector requestorReadTotalLat;
 579         Stats::Vector requestorWriteTotalLat;
 580
 581         // per-requestor raed and write average memory access latency
 582         Stats::Formula requestorReadAvgLat;
 583         Stats::Formula requestorWriteAvgLat;
 584     };
 585
 586     CtrlStats stats;
 587
 588     /**
 589      * Upstream caches need this packet until true is returned, so
 590      * hold it for deletion until a subsequent call
 591      */
 592     std::unique_ptr<Packet> pendingDelete;
 593
 594     /**
 595      * Select either the read or write queue
 596      *
 597      * @param is_read The current burst is a read, select read queue
 598      * @return a reference to the appropriate queue
 599      */
 600     std::vector<MemPacketQueue>& selQueue(bool is_read)
 601     {
 602         return (is_read ? readQueue : writeQueue);
 603     };
 604
 605     /**
 606      * Remove commands that have already issued from burstTicks
 607      */
 608     void pruneBurstTick();
 609
 610   public:
 611
 612     MemCtrl(const MemCtrlParams &p);
 613
 614     /**
 615      * Ensure that all interfaced have drained commands
 616      *
 617      * @return bool flag, set once drain complete
 618      */
 619     bool allIntfDrained() const;
 620
 621     DrainState drain() override;
 622
 623     /**
 624      * Check for command bus contention for single cycle command.
 625      * If there is contention, shift command to next burst.
 626      * Check verifies that the commands issued per burst is less
 627      * than a defined max number, maxCommandsPerWindow.
 628      * Therefore, contention per cycle is not verified and instead
 629      * is done based on a burst window.
 630      *
 631      * @param cmd_tick Initial tick of command, to be verified
 632      * @param max_cmds_per_burst Number of commands that can issue
 633      *                           in a burst window
 634      * @return tick for command issue without contention
 635      */
 636     Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst);
 637
 638     /**
 639      * Check for command bus contention for multi-cycle (2 currently)
 640      * command. If there is contention, shift command(s) to next burst.
 641      * Check verifies that the commands issued per burst is less
 642      * than a defined max number, maxCommandsPerWindow.
 643      * Therefore, contention per cycle is not verified and instead
 644      * is done based on a burst window.
 645      *
 646      * @param cmd_tick Initial tick of command, to be verified
 647      * @param max_multi_cmd_split Maximum delay between commands
 648      * @param max_cmds_per_burst Number of commands that can issue
 649      *                           in a burst window
 650      * @return tick for command issue without contention
 651      */
 652     Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
 653                         Tick max_multi_cmd_split = 0);
 654
 655     /**
 656      * Is there a respondEvent scheduled?
 657      *
 658      * @return true if event is scheduled
 659      */
 660     bool respondEventScheduled() const { return respondEvent.scheduled(); }
 661
 662     /**
 663      * Is there a read/write burst Event scheduled?
 664      *
 665      * @return true if event is scheduled
 666      */
 667     bool requestEventScheduled() const { return nextReqEvent.scheduled(); }
 668
 669     /**
 670      * restart the controller
 671      * This can be used by interfaces to restart the
 672      * scheduler after maintainence commands complete
 673      *
 674      * @param Tick to schedule next event
 675      */
 676     void restartScheduler(Tick tick) { schedule(nextReqEvent, tick); }
 677
 678     /**
 679      * Check the current direction of the memory channel
 680      *
 681      * @param next_state Check either the current or next bus state
 682      * @return True when bus is currently in a read state
 683      */
 684     bool inReadBusState(bool next_state) const;
 685
 686     /**
 687      * Check the current direction of the memory channel
 688      *
 689      * @param next_state Check either the current or next bus state
 690      * @return True when bus is currently in a write state
 691      */
 692     bool inWriteBusState(bool next_state) const;
 693
 694     Port &getPort(const std::string &if_name,
 695                   PortID idx=InvalidPortID) override;
 696
 697     virtual void init() override;
 698     virtual void startup() override;
 699     virtual void drainResume() override;
 700
 701   protected:
 702
 703     Tick recvAtomic(PacketPtr pkt);
 704     void recvFunctional(PacketPtr pkt);
 705     bool recvTimingReq(PacketPtr pkt);
 706
 707 };
 708
 709 #endif //__MEM_CTRL_HH__