src/mem/mem_delay.cc

   1 /*
   2  * Copyright (c) 2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Andreas Sandberg
  38  */
  39
  40 #include "mem/mem_delay.hh"
  41
  42 #include "params/MemDelay.hh"
  43 #include "params/SimpleMemDelay.hh"
  44
  45 MemDelay::MemDelay(const MemDelayParams *p)
  46     : MemObject(p),
  47       masterPort(name() + "-master", *this),
  48       slavePort(name() + "-slave", *this),
  49       reqQueue(*this, masterPort),
  50       respQueue(*this, slavePort),
  51       snoopRespQueue(*this, masterPort)
  52 {
  53 }
  54
  55 void
  56 MemDelay::init()
  57 {
  58     if (!slavePort.isConnected() || !masterPort.isConnected())
  59         fatal("Memory delay is not connected on both sides.\n");
  60 }
  61
  62
  63 BaseMasterPort&
  64 MemDelay::getMasterPort(const std::string& if_name, PortID idx)
  65 {
  66     if (if_name == "master") {
  67         return masterPort;
  68     } else {
  69         return MemObject::getMasterPort(if_name, idx);
  70     }
  71 }
  72
  73 BaseSlavePort&
  74 MemDelay::getSlavePort(const std::string& if_name, PortID idx)
  75 {
  76     if (if_name == "slave") {
  77         return slavePort;
  78     } else {
  79         return MemObject::getSlavePort(if_name, idx);
  80     }
  81 }
  82
  83 bool
  84 MemDelay::checkFunctional(PacketPtr pkt)
  85 {
  86     return slavePort.checkFunctional(pkt) ||
  87         masterPort.checkFunctional(pkt);
  88 }
  89
  90 MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent)
  91     : QueuedMasterPort(_name, &_parent,
  92                        _parent.reqQueue, _parent.snoopRespQueue),
  93       parent(_parent)
  94 {
  95 }
  96
  97 bool
  98 MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
  99 {
 100     const Tick when = curTick() + parent.delayResp(pkt);
 101
 102     parent.slavePort.schedTimingResp(pkt, when);
 103
 104     return true;
 105 }
 106
 107 void
 108 MemDelay::MasterPort::recvFunctionalSnoop(PacketPtr pkt)
 109 {
 110     if (parent.checkFunctional(pkt)) {
 111         pkt->makeResponse();
 112     } else {
 113         parent.slavePort.sendFunctionalSnoop(pkt);
 114     }
 115 }
 116
 117 Tick
 118 MemDelay::MasterPort::recvAtomicSnoop(PacketPtr pkt)
 119 {
 120     const Tick delay = parent.delaySnoopResp(pkt);
 121
 122     return delay + parent.slavePort.sendAtomicSnoop(pkt);
 123 }
 124
 125 void
 126 MemDelay::MasterPort::recvTimingSnoopReq(PacketPtr pkt)
 127 {
 128     parent.slavePort.sendTimingSnoopReq(pkt);
 129 }
 130
 131
 132 MemDelay::SlavePort::SlavePort(const std::string &_name, MemDelay &_parent)
 133     : QueuedSlavePort(_name, &_parent, _parent.respQueue),
 134       parent(_parent)
 135 {
 136 }
 137
 138 Tick
 139 MemDelay::SlavePort::recvAtomic(PacketPtr pkt)
 140 {
 141     const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt);
 142
 143     return delay + parent.masterPort.sendAtomic(pkt);
 144 }
 145
 146 bool
 147 MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
 148 {
 149     const Tick when = curTick() + parent.delayReq(pkt);
 150
 151     parent.masterPort.schedTimingReq(pkt, when);
 152
 153     return true;
 154 }
 155
 156 void
 157 MemDelay::SlavePort::recvFunctional(PacketPtr pkt)
 158 {
 159     if (parent.checkFunctional(pkt)) {
 160         pkt->makeResponse();
 161     } else {
 162         parent.masterPort.sendFunctional(pkt);
 163     }
 164 }
 165
 166 bool
 167 MemDelay::SlavePort::recvTimingSnoopResp(PacketPtr pkt)
 168 {
 169     const Tick when = curTick() + parent.delaySnoopResp(pkt);
 170
 171     parent.masterPort.schedTimingSnoopResp(pkt, when);
 172
 173     return true;
 174 }
 175
 176
 177
 178 SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams *p)
 179     : MemDelay(p),
 180       readReqDelay(p->read_req),
 181       readRespDelay(p->read_resp),
 182       writeReqDelay(p->write_req),
 183       writeRespDelay(p->write_resp)
 184 {
 185 }
 186
 187 Tick
 188 SimpleMemDelay::delayReq(PacketPtr pkt)
 189 {
 190     if (pkt->isRead()) {
 191         return readReqDelay;
 192     } else if (pkt->isWrite()) {
 193         return writeReqDelay;
 194     } else {
 195         return 0;
 196     }
 197 }
 198
 199 Tick
 200 SimpleMemDelay::delayResp(PacketPtr pkt)
 201 {
 202     if (pkt->isRead()) {
 203         return readRespDelay;
 204     } else if (pkt->isWrite()) {
 205         return writeRespDelay;
 206     } else {
 207         return 0;
 208     }
 209 }
 210
 211
 212 SimpleMemDelay *
 213 SimpleMemDelayParams::create()
 214 {
 215     return new SimpleMemDelay(this);
 216 }