2 * Copyright (c) 2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andreas Sandberg
40 #include "mem/mem_delay.hh"
42 #include "params/MemDelay.hh"
43 #include "params/SimpleMemDelay.hh"
45 MemDelay::MemDelay(const MemDelayParams
*p
)
47 masterPort(name() + "-master", *this),
48 slavePort(name() + "-slave", *this),
49 reqQueue(*this, masterPort
),
50 respQueue(*this, slavePort
),
51 snoopRespQueue(*this, masterPort
)
58 if (!slavePort
.isConnected() || !masterPort
.isConnected())
59 fatal("Memory delay is not connected on both sides.\n");
64 MemDelay::getMasterPort(const std::string
& if_name
, PortID idx
)
66 if (if_name
== "master") {
69 return MemObject::getMasterPort(if_name
, idx
);
74 MemDelay::getSlavePort(const std::string
& if_name
, PortID idx
)
76 if (if_name
== "slave") {
79 return MemObject::getSlavePort(if_name
, idx
);
84 MemDelay::checkFunctional(PacketPtr pkt
)
86 return slavePort
.checkFunctional(pkt
) ||
87 masterPort
.checkFunctional(pkt
);
90 MemDelay::MasterPort::MasterPort(const std::string
&_name
, MemDelay
&_parent
)
91 : QueuedMasterPort(_name
, &_parent
,
92 _parent
.reqQueue
, _parent
.snoopRespQueue
),
98 MemDelay::MasterPort::recvTimingResp(PacketPtr pkt
)
100 const Tick when
= curTick() + parent
.delayResp(pkt
);
102 parent
.slavePort
.schedTimingResp(pkt
, when
);
108 MemDelay::MasterPort::recvFunctionalSnoop(PacketPtr pkt
)
110 if (parent
.checkFunctional(pkt
)) {
113 parent
.slavePort
.sendFunctionalSnoop(pkt
);
118 MemDelay::MasterPort::recvAtomicSnoop(PacketPtr pkt
)
120 const Tick delay
= parent
.delaySnoopResp(pkt
);
122 return delay
+ parent
.slavePort
.sendAtomicSnoop(pkt
);
126 MemDelay::MasterPort::recvTimingSnoopReq(PacketPtr pkt
)
128 parent
.slavePort
.sendTimingSnoopReq(pkt
);
132 MemDelay::SlavePort::SlavePort(const std::string
&_name
, MemDelay
&_parent
)
133 : QueuedSlavePort(_name
, &_parent
, _parent
.respQueue
),
139 MemDelay::SlavePort::recvAtomic(PacketPtr pkt
)
141 const Tick delay
= parent
.delayReq(pkt
) + parent
.delayResp(pkt
);
143 return delay
+ parent
.masterPort
.sendAtomic(pkt
);
147 MemDelay::SlavePort::recvTimingReq(PacketPtr pkt
)
149 const Tick when
= curTick() + parent
.delayReq(pkt
);
151 parent
.masterPort
.schedTimingReq(pkt
, when
);
157 MemDelay::SlavePort::recvFunctional(PacketPtr pkt
)
159 if (parent
.checkFunctional(pkt
)) {
162 parent
.masterPort
.sendFunctional(pkt
);
167 MemDelay::SlavePort::recvTimingSnoopResp(PacketPtr pkt
)
169 const Tick when
= curTick() + parent
.delaySnoopResp(pkt
);
171 parent
.masterPort
.schedTimingSnoopResp(pkt
, when
);
178 SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams
*p
)
180 readReqDelay(p
->read_req
),
181 readRespDelay(p
->read_resp
),
182 writeReqDelay(p
->write_req
),
183 writeRespDelay(p
->write_resp
)
188 SimpleMemDelay::delayReq(PacketPtr pkt
)
192 } else if (pkt
->isWrite()) {
193 return writeReqDelay
;
200 SimpleMemDelay::delayResp(PacketPtr pkt
)
203 return readRespDelay
;
204 } else if (pkt
->isWrite()) {
205 return writeRespDelay
;
213 SimpleMemDelayParams::create()
215 return new SimpleMemDelay(this);