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43 * MemInterface declaration
46 #ifndef __MEM_INTERFACE_HH__
47 #define __MEM_INTERFACE_HH__
51 #include <unordered_set>
55 #include "base/statistics.hh"
56 #include "enums/AddrMap.hh"
57 #include "enums/PageManage.hh"
58 #include "mem/abstract_mem.hh"
59 #include "mem/drampower.hh"
60 #include "mem/mem_ctrl.hh"
61 #include "params/DRAMInterface.hh"
62 #include "params/MemInterface.hh"
63 #include "params/NVMInterface.hh"
64 #include "sim/eventq.hh"
67 * General interface to memory device
68 * Includes functions and parameters shared across media types
70 class MemInterface : public AbstractMemory
74 * A basic class to track the bank state, i.e. what row is
75 * currently open (if any), when is the bank free to accept a new
76 * column (read/write) command, when can it be precharged, and
77 * when can it be activated.
79 * The bank also keeps track of how many bytes have been accessed
80 * in the open row since it was opened.
86 static const uint32_t NO_ROW = -1;
98 uint32_t bytesAccessed;
101 openRow(NO_ROW), bank(0), bankgr(0),
102 rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
103 rowAccesses(0), bytesAccessed(0)
108 * A pointer to the parent MemCtrl instance
113 * Number of commands that can issue in the defined controller
114 * command window, used to verify command bandwidth
116 unsigned int maxCommandsPerWindow;
119 * Memory controller configuration initialized based on parameter
122 Enums::AddrMap addrMapping;
125 * General device and channel characteristics
126 * The rowsPerBank is determined based on the capacity, number of
127 * ranks and banks, the burst size, and the row buffer size.
129 const uint32_t burstSize;
130 const uint32_t deviceSize;
131 const uint32_t deviceRowBufferSize;
132 const uint32_t devicesPerRank;
133 const uint32_t rowBufferSize;
134 const uint32_t burstsPerRowBuffer;
135 const uint32_t burstsPerStripe;
136 const uint32_t ranksPerChannel;
137 const uint32_t banksPerRank;
138 uint32_t rowsPerBank;
141 * General timing requirements
143 M5_CLASS_VAR_USED const Tick tCK;
150 * @return delay between write and read commands
152 virtual Tick writeToReadDelay() const { return tBURST + tWTR; }
155 * @return delay between write and read commands
157 Tick readToWriteDelay() const { return tBURST + tRTW; }
160 * @return delay between accesses to different ranks
162 Tick rankToRankDelay() const { return tBURST + tCS; }
168 * Buffer sizes for read and write queues in the controller
169 * These are passed to the controller on instantiation
170 * Defining them here allows for buffers to be resized based
171 * on memory type / configuration.
173 const uint32_t readBufferSize;
174 const uint32_t writeBufferSize;
176 /** Set a pointer to the controller and initialize
177 * interface based on controller parameters
178 * @param _ctrl pointer to the parent controller
179 * @param command_window size of command window used to
180 * check command bandwidth
182 void setCtrl(MemCtrl* _ctrl, unsigned int command_window);
185 * Get an address in a dense range which starts from 0. The input
186 * address is the physical address of the request in an address
187 * space that contains other SimObjects apart from this
190 * @param addr The intput address which should be in the addrRange
191 * @return An address in the continues range [0, max)
193 Addr getCtrlAddr(Addr addr) { return range.getOffset(addr); }
196 * Setup the rank based on packet received
198 * @param integer value of rank to be setup. used to index ranks vector
199 * @param are we setting up rank for read or write packet?
201 virtual void setupRank(const uint8_t rank, const bool is_read) = 0;
204 * Check drain state of interface
206 * @return true if all ranks are drained and idle
209 virtual bool allRanksDrained() const = 0;
212 * For FR-FCFS policy, find first command that can issue
213 * Function will be overriden by interface to select based
214 * on media characteristics, used to determine when read
215 * or write can issue.
217 * @param queue Queued requests to consider
218 * @param min_col_at Minimum tick for 'seamless' issue
219 * @return an iterator to the selected packet, else queue.end()
220 * @return the tick when the packet selected will issue
222 virtual std::pair<MemPacketQueue::iterator, Tick>
223 chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const = 0;
226 * Function to calulate unloaded latency
228 virtual Tick accessLatency() const = 0;
231 * @return number of bytes in a burst for this interface
233 uint32_t bytesPerBurst() const { return burstSize; }
236 * @return time to offset next command
238 virtual Tick commandOffset() const = 0;
241 * Check if a burst operation can be issued to the interface
243 * @param Return true if RD/WR can issue
245 virtual bool burstReady(MemPacket* pkt) const = 0;
248 * Determine the required delay for an access to a different rank
250 * @return required rank to rank delay
252 Tick rankDelay() const { return tCS; }
256 * @return minimum additional bus turnaround required for read-to-write
258 Tick minReadToWriteDataGap() const { return std::min(tRTW, tCS); }
262 * @return minimum additional bus turnaround required for write-to-read
264 Tick minWriteToReadDataGap() const { return std::min(tWTR, tCS); }
267 * Address decoder to figure out physical mapping onto ranks,
268 * banks, and rows. This function is called multiple times on the same
269 * system packet if the pakcet is larger than burst of the memory. The
270 * pkt_addr is used for the offset within the packet.
272 * @param pkt The packet from the outside world
273 * @param pkt_addr The starting address of the packet
274 * @param size The size of the packet in bytes
275 * @param is_read Is the request for a read or a write to memory
276 * @param is_dram Is the request to a DRAM interface
277 * @return A MemPacket pointer with the decoded information
279 MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
280 unsigned int size, bool is_read, bool is_dram);
283 * Add rank to rank delay to bus timing to all banks in all ranks
284 * when access to an alternate interface is issued
286 * param cmd_at Time of current command used as starting point for
287 * addition of rank-to-rank delay
289 virtual void addRankToRankDelay(Tick cmd_at) = 0;
291 typedef MemInterfaceParams Params;
292 MemInterface(const Params &_p);
296 * Interface to DRAM devices with media specific parameters,
297 * statistics, and functions.
298 * The DRAMInterface includes a class for individual ranks
299 * and per rank functions.
301 class DRAMInterface : public MemInterface
305 * Simple structure to hold the values needed to keep track of
306 * commands for DRAMPower
310 Data::MemCommand::cmds type;
314 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
316 : type(_type), bank(_bank), timeStamp(time_stamp)
321 * The power state captures the different operational states of
322 * the DRAM and interacts with the bus read/write state machine,
323 * and the refresh state machine.
325 * PWR_IDLE : The idle state in which all banks are closed
326 * From here can transition to: PWR_REF, PWR_ACT,
329 * PWR_REF : Auto-refresh state. Will transition when refresh is
330 * complete based on power state prior to PWR_REF
331 * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
334 * PWR_SREF : Self-refresh state. Entered after refresh if
335 * previous state was PWR_PRE_PDN
336 * From here can transition to: PWR_IDLE
338 * PWR_PRE_PDN : Precharge power down state
339 * From here can transition to: PWR_REF, PWR_IDLE
341 * PWR_ACT : Activate state in which one or more banks are open
342 * From here can transition to: PWR_IDLE, PWR_ACT_PDN
344 * PWR_ACT_PDN : Activate power down state
345 * From here can transition to: PWR_ACT
358 * The refresh state is used to control the progress of the
359 * refresh scheduling. When normal operation is in progress the
360 * refresh state is idle. Once tREFI has elasped, a refresh event
361 * is triggered to start the following STM transitions which are
362 * used to issue a refresh and return back to normal operation
364 * REF_IDLE : IDLE state used during normal operation
365 * From here can transition to: REF_DRAIN
367 * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
368 * after self-refresh exit completes
369 * From here can transition to: REF_DRAIN
371 * REF_DRAIN : Drain state in which on going accesses complete.
372 * From here can transition to: REF_PD_EXIT
374 * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
375 * Next state dependent on whether banks are open
376 * From here can transition to: REF_PRE, REF_START
378 * REF_PRE : Close (precharge) all open banks
379 * From here can transition to: REF_START
381 * REF_START : Issue refresh command and update DRAMPower stats
382 * From here can transition to: REF_RUN
384 * REF_RUN : Refresh running, waiting for tRFC to expire
385 * From here can transition to: REF_IDLE, REF_SREF_EXIT
399 struct RankStats : public Stats::Group
401 RankStats(DRAMInterface &dram, Rank &rank);
403 void regStats() override;
404 void resetStats() override;
405 void preDumpStats() override;
412 Stats::Scalar actEnergy;
413 Stats::Scalar preEnergy;
414 Stats::Scalar readEnergy;
415 Stats::Scalar writeEnergy;
416 Stats::Scalar refreshEnergy;
419 * Active Background Energy
421 Stats::Scalar actBackEnergy;
424 * Precharge Background Energy
426 Stats::Scalar preBackEnergy;
429 * Active Power-Down Energy
431 Stats::Scalar actPowerDownEnergy;
434 * Precharge Power-Down Energy
436 Stats::Scalar prePowerDownEnergy;
439 * self Refresh Energy
441 Stats::Scalar selfRefreshEnergy;
443 Stats::Scalar totalEnergy;
444 Stats::Scalar averagePower;
447 * Stat to track total DRAM idle time
450 Stats::Scalar totalIdleTime;
453 * Track time spent in each power state.
455 Stats::Vector pwrStateTime;
459 * Rank class includes a vector of banks. Refresh and Power state
460 * machines are defined per rank. Events required to change the
461 * state of the refresh and power state machine are scheduled per
462 * rank. This class allows the implementation of rank-wise refresh
463 * and rank-wise power-down.
465 class Rank : public EventManager
470 * A reference to the parent DRAMInterface instance
475 * Since we are taking decisions out of order, we need to keep
476 * track of what power transition is happening at what time
478 PowerState pwrStateTrans;
481 * Previous low-power state, which will be re-entered after refresh.
483 PowerState pwrStatePostRefresh;
486 * Track when we transitioned to the current power state
491 * Keep track of when a refresh is due.
496 * Function to update Power Stats
498 void updatePowerStats();
501 * Schedule a power state transition in the future, and
502 * potentially override an already scheduled transition.
504 * @param pwr_state Power state to transition to
505 * @param tick Tick when transition should take place
507 void schedulePowerEvent(PowerState pwr_state, Tick tick);
512 * Current power state.
517 * current refresh state
519 RefreshState refreshState;
522 * rank is in or transitioning to power-down or self-refresh
524 bool inLowPowerState;
532 * Track number of packets in read queue going to this rank
534 uint32_t readEntries;
537 * Track number of packets in write queue going to this rank
539 uint32_t writeEntries;
542 * Number of ACT, RD, and WR events currently scheduled
543 * Incremented when a refresh event is started as well
544 * Used to determine when a low-power state can be entered
546 uint8_t outstandingEvents;
549 * delay low-power exit until this requirement is met
551 Tick wakeUpAllowedAt;
554 * One DRAMPower instance per rank
559 * List of commands issued, to be sent to DRAMPpower at refresh
560 * and stats dump. Keep commands here since commands to different
561 * banks are added out of order. Will only pass commands up to
562 * curTick() to DRAMPower after sorting.
564 std::vector<Command> cmdList;
567 * Vector of Banks. Each rank is made of several devices which in
568 * term are made from several banks.
570 std::vector<Bank> banks;
573 * To track number of banks which are currently active for
576 unsigned int numBanksActive;
578 /** List to keep track of activate ticks */
579 std::deque<Tick> actTicks;
582 * Track when we issued the last read/write burst
586 Rank(const DRAMInterfaceParams &_p, int _rank,
587 DRAMInterface& _dram);
589 const std::string name() const { return csprintf("%d", rank); }
592 * Kick off accounting for power and refresh states and
593 * schedule initial refresh.
595 * @param ref_tick Tick for first refresh
597 void startup(Tick ref_tick);
600 * Stop the refresh events.
605 * Check if there is no refresh and no preparation of refresh ongoing
606 * i.e. the refresh state machine is in idle
608 * @param Return true if the rank is idle from a refresh point of view
610 bool inRefIdleState() const { return refreshState == REF_IDLE; }
613 * Check if the current rank has all banks closed and is not
614 * in a low power state
616 * @param Return true if the rank is idle from a bank
617 * and power point of view
619 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
622 * Trigger a self-refresh exit if there are entries enqueued
623 * Exit if there are any read entries regardless of the bus state.
624 * If we are currently issuing write commands, exit if we have any
625 * write commands enqueued as well.
626 * Could expand this in the future to analyze state of entire queue
629 * @return boolean indicating self-refresh exit should be scheduled
631 bool forceSelfRefreshExit() const;
634 * Check if the command queue of current rank is idle
636 * @param Return true if the there are no commands in Q.
637 * Bus direction determines queue checked.
639 bool isQueueEmpty() const;
642 * Let the rank check if it was waiting for requests to drain
643 * to allow it to transition states.
645 void checkDrainDone();
648 * Push command out of cmdList queue that are scheduled at
649 * or before curTick() to DRAMPower library
650 * All commands before curTick are guaranteed to be complete
651 * and can safely be flushed.
656 * Computes stats just prior to dump event
661 * Reset stats on a stats event
666 * Schedule a transition to power-down (sleep)
668 * @param pwr_state Power state to transition to
669 * @param tick Absolute tick when transition should take place
671 void powerDownSleep(PowerState pwr_state, Tick tick);
674 * schedule and event to wake-up from power-down or self-refresh
675 * and update bank timing parameters
677 * @param exit_delay Relative tick defining the delay required between
678 * low-power exit and the next command
680 void scheduleWakeUpEvent(Tick exit_delay);
682 void processWriteDoneEvent();
683 EventFunctionWrapper writeDoneEvent;
685 void processActivateEvent();
686 EventFunctionWrapper activateEvent;
688 void processPrechargeEvent();
689 EventFunctionWrapper prechargeEvent;
691 void processRefreshEvent();
692 EventFunctionWrapper refreshEvent;
694 void processPowerEvent();
695 EventFunctionWrapper powerEvent;
697 void processWakeUpEvent();
698 EventFunctionWrapper wakeUpEvent;
705 * Function for sorting Command structures based on timeStamp
707 * @param a Memory Command
708 * @param next Memory Command
709 * @return true if timeStamp of Command 1 < timeStamp of Command 2
712 sortTime(const Command& cmd, const Command& cmd_next)
714 return cmd.timeStamp < cmd_next.timeStamp;
718 * DRAM specific device characteristics
720 const uint32_t bankGroupsPerRank;
721 const bool bankGroupArch;
724 * DRAM specific timing requirements
727 const Tick tBURST_MIN;
728 const Tick tBURST_MAX;
729 const Tick tCCD_L_WR;
745 const Tick clkResyncDelay;
746 const bool dataClockSync;
747 const bool burstInterleave;
748 const uint8_t twoCycleActivate;
749 const uint32_t activationLimit;
750 const Tick wrToRdDlySameBG;
751 const Tick rdToWrDlySameBG;
754 Enums::PageManage pageMgmt;
756 * Max column accesses (read and write) per row, before forefully
759 const uint32_t maxAccessesPerRow;
762 uint64_t timeStampOffset;
764 // Holds the value of the DRAM rank of burst issued
767 /** Enable or disable DRAM powerdown states. */
768 bool enableDRAMPowerdown;
770 /** The time when stats were last reset used to calculate average power */
771 Tick lastStatsResetTick;
774 * Keep track of when row activations happen, in order to enforce
775 * the maximum number of activations in the activation window. The
776 * method updates the time that the banks become available based
777 * on the current limits.
779 * @param rank_ref Reference to the rank
780 * @param bank_ref Reference to the bank
781 * @param act_tick Time when the activation takes place
782 * @param row Index of the row
784 void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
788 * Precharge a given bank and also update when the precharge is
789 * done. This will also deal with any stats related to the
790 * accesses to the open page.
792 * @param rank_ref The rank to precharge
793 * @param bank_ref The bank to precharge
794 * @param pre_tick Time when the precharge takes place
795 * @param auto_or_preall Is this an auto-precharge or precharge all command
796 * @param trace Is this an auto precharge then do not add to trace
798 void prechargeBank(Rank& rank_ref, Bank& bank_ref,
799 Tick pre_tick, bool auto_or_preall = false,
802 struct DRAMStats : public Stats::Group
804 DRAMStats(DRAMInterface &dram);
806 void regStats() override;
807 void resetStats() override;
811 /** total number of DRAM bursts serviced */
812 Stats::Scalar readBursts;
813 Stats::Scalar writeBursts;
815 /** DRAM per bank stats */
816 Stats::Vector perBankRdBursts;
817 Stats::Vector perBankWrBursts;
819 // Latencies summed over all requests
820 Stats::Scalar totQLat;
821 Stats::Scalar totBusLat;
822 Stats::Scalar totMemAccLat;
824 // Average latencies per request
825 Stats::Formula avgQLat;
826 Stats::Formula avgBusLat;
827 Stats::Formula avgMemAccLat;
829 // Row hit count and rate
830 Stats::Scalar readRowHits;
831 Stats::Scalar writeRowHits;
832 Stats::Formula readRowHitRate;
833 Stats::Formula writeRowHitRate;
834 Stats::Histogram bytesPerActivate;
835 // Number of bytes transferred to/from DRAM
836 Stats::Scalar bytesRead;
837 Stats::Scalar bytesWritten;
840 Stats::Formula avgRdBW;
841 Stats::Formula avgWrBW;
842 Stats::Formula peakBW;
844 Stats::Formula busUtil;
845 Stats::Formula busUtilRead;
846 Stats::Formula busUtilWrite;
847 Stats::Formula pageHitRate;
853 * Vector of dram ranks
855 std::vector<Rank*> ranks;
858 * @return delay between write and read commands
860 Tick writeToReadDelay() const override { return tBURST + tWTR + tCL; }
863 * Find which are the earliest banks ready to issue an activate
864 * for the enqueued requests. Assumes maximum of 32 banks per rank
865 * Also checks if the bank is already prepped.
867 * @param queue Queued requests to consider
868 * @param min_col_at time of seamless burst command
869 * @return One-hot encoded mask of bank indices
870 * @return boolean indicating burst can issue seamlessly, with no gaps
872 std::pair<std::vector<uint32_t>, bool>
873 minBankPrep(const MemPacketQueue& queue, Tick min_col_at) const;
876 * @return time to send a burst of data without gaps
881 return (burstInterleave ? tBURST_MAX / 2 : tBURST);
886 * Initialize the DRAM interface and verify parameters
888 void init() override;
891 * Iterate through dram ranks and instantiate per rank startup routine
893 void startup() override;
896 * Setup the rank based on packet received
898 * @param integer value of rank to be setup. used to index ranks vector
899 * @param are we setting up rank for read or write packet?
901 void setupRank(const uint8_t rank, const bool is_read) override;
904 * Iterate through dram ranks to exit self-refresh in order to drain
909 * Return true once refresh is complete for all ranks and there are no
910 * additional commands enqueued. (only evaluated when draining)
911 * This will ensure that all banks are closed, power state is IDLE, and
912 * power stats have been updated
914 * @return true if all ranks have refreshed, with no commands enqueued
917 bool allRanksDrained() const override;
920 * Iterate through DRAM ranks and suspend them
925 * @return time to offset next command
927 Tick commandOffset() const override { return (tRP + tRCD); }
930 * Function to calulate unloaded, closed bank access latency
932 Tick accessLatency() const override { return (tRP + tRCD + tCL); }
935 * For FR-FCFS policy, find first DRAM command that can issue
937 * @param queue Queued requests to consider
938 * @param min_col_at Minimum tick for 'seamless' issue
939 * @return an iterator to the selected packet, else queue.end()
940 * @return the tick when the packet selected will issue
942 std::pair<MemPacketQueue::iterator, Tick>
943 chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
946 * Actually do the burst - figure out the latency it
947 * will take to service the req based on bank state, channel state etc
948 * and then update those states to account for this request. Based
949 * on this, update the packet's "readyTime" and move it to the
950 * response q from where it will eventually go back to the outside
953 * @param mem_pkt The packet created from the outside world pkt
954 * @param next_burst_at Minimum bus timing requirement from controller
955 * @param queue Reference to the read or write queue with the packet
956 * @return pair, tick when current burst is issued and
957 * tick when next burst can issue
959 std::pair<Tick, Tick>
960 doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
961 const std::vector<MemPacketQueue>& queue);
964 * Check if a burst operation can be issued to the DRAM
966 * @param Return true if RD/WR can issue
967 * This requires the DRAM to be in the
971 burstReady(MemPacket* pkt) const override
973 return ranks[pkt->rank]->inRefIdleState();
977 * This function checks if ranks are actively refreshing and
978 * therefore busy. The function also checks if ranks are in
979 * the self-refresh state, in which case, a self-refresh exit
982 * return boolean if all ranks are in refresh and therefore busy
987 * Add rank to rank delay to bus timing to all DRAM banks in alli ranks
988 * when access to an alternate interface is issued
990 * param cmd_at Time of current command used as starting point for
991 * addition of rank-to-rank delay
993 void addRankToRankDelay(Tick cmd_at) override;
996 * Complete response process for DRAM when read burst is complete
997 * This will update the counters and check if a power down state
1000 * @param rank Specifies rank associated with read burst
1002 void respondEvent(uint8_t rank);
1005 * Check the refresh state to determine if refresh needs
1006 * to be kicked back into action after a read response
1008 * @param rank Specifies rank associated with read burst
1010 void checkRefreshState(uint8_t rank);
1012 DRAMInterface(const DRAMInterfaceParams &_p);
1016 * Interface to NVM devices with media specific parameters,
1017 * statistics, and functions.
1018 * The NVMInterface includes a class for individual ranks
1019 * and per rank functions.
1021 class NVMInterface : public MemInterface
1025 * NVM rank class simply includes a vector of banks.
1027 class Rank : public EventManager
1032 * Current Rank index
1037 * Vector of NVM banks. Each rank is made of several banks
1038 * that can be accessed in parallel.
1040 std::vector<Bank> banks;
1042 Rank(const NVMInterfaceParams &_p, int _rank,
1043 NVMInterface& _nvm);
1047 * NVM specific device and channel characteristics
1049 const uint32_t maxPendingWrites;
1050 const uint32_t maxPendingReads;
1051 const bool twoCycleRdWr;
1054 * NVM specific timing requirements
1060 struct NVMStats : public Stats::Group
1062 NVMStats(NVMInterface &nvm);
1064 void regStats() override;
1069 Stats::Scalar readBursts;
1070 Stats::Scalar writeBursts;
1072 Stats::Vector perBankRdBursts;
1073 Stats::Vector perBankWrBursts;
1075 // Latencies summed over all requests
1076 Stats::Scalar totQLat;
1077 Stats::Scalar totBusLat;
1078 Stats::Scalar totMemAccLat;
1080 // Average latencies per request
1081 Stats::Formula avgQLat;
1082 Stats::Formula avgBusLat;
1083 Stats::Formula avgMemAccLat;
1085 Stats::Scalar bytesRead;
1086 Stats::Scalar bytesWritten;
1088 // Average bandwidth
1089 Stats::Formula avgRdBW;
1090 Stats::Formula avgWrBW;
1091 Stats::Formula peakBW;
1092 Stats::Formula busUtil;
1093 Stats::Formula busUtilRead;
1094 Stats::Formula busUtilWrite;
1097 Stats::Histogram pendingReads;
1098 Stats::Histogram pendingWrites;
1099 Stats::Histogram bytesPerBank;
1103 void processWriteRespondEvent();
1104 EventFunctionWrapper writeRespondEvent;
1106 void processReadReadyEvent();
1107 EventFunctionWrapper readReadyEvent;
1110 * Vector of nvm ranks
1112 std::vector<Rank*> ranks;
1115 * Holding queue for non-deterministic write commands, which
1116 * maintains writes that have been issued but have not completed
1117 * Stored seperately mostly to keep the code clean and help with
1118 * events scheduling.
1119 * This mimics a buffer on the media controller and therefore is
1120 * not added to the main write queue for sizing
1122 std::list<Tick> writeRespQueue;
1124 std::deque<Tick> readReadyQueue;
1127 * Check if the write response queue is empty
1129 * @param Return true if empty
1131 bool writeRespQueueEmpty() const { return writeRespQueue.empty(); }
1134 * Till when must we wait before issuing next read command?
1138 // keep track of reads that have issued for which data is either
1139 // not yet ready or has not yet been transferred to the ctrl
1140 uint16_t numPendingReads;
1141 uint16_t numReadDataReady;
1144 // keep track of the number of reads that have yet to be issued
1145 uint16_t numReadsToIssue;
1147 // number of writes in the writeQueue for the NVM interface
1148 uint32_t numWritesQueued;
1151 * Initialize the NVM interface and verify parameters
1153 void init() override;
1156 * Setup the rank based on packet received
1158 * @param integer value of rank to be setup. used to index ranks vector
1159 * @param are we setting up rank for read or write packet?
1161 void setupRank(const uint8_t rank, const bool is_read) override;
1164 * Check drain state of NVM interface
1166 * @return true if write response queue is empty
1169 bool allRanksDrained() const override { return writeRespQueueEmpty(); }
1172 * @return time to offset next command
1174 Tick commandOffset() const override { return tBURST; }
1177 * Check if a burst operation can be issued to the NVM
1179 * @param Return true if RD/WR can issue
1180 * for reads, also verfy that ready count
1181 * has been updated to a non-zero value to
1182 * account for race conditions between events
1184 bool burstReady(MemPacket* pkt) const override;
1187 * This function checks if ranks are busy.
1188 * This state is true when either:
1189 * 1) There is no command with read data ready to transmit or
1190 * 2) The NVM inteface has reached the maximum number of outstanding
1192 * @param read_queue_empty There are no read queued
1193 * @param all_writes_nvm All writes in queue are for NVM interface
1194 * @return true of NVM is busy
1197 bool isBusy(bool read_queue_empty, bool all_writes_nvm);
1199 * For FR-FCFS policy, find first NVM command that can issue
1200 * default to first command to prepped region
1202 * @param queue Queued requests to consider
1203 * @param min_col_at Minimum tick for 'seamless' issue
1204 * @return an iterator to the selected packet, else queue.end()
1205 * @return the tick when the packet selected will issue
1207 std::pair<MemPacketQueue::iterator, Tick>
1208 chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
1211 * Add rank to rank delay to bus timing to all NVM banks in alli ranks
1212 * when access to an alternate interface is issued
1214 * param cmd_at Time of current command used as starting point for
1215 * addition of rank-to-rank delay
1217 void addRankToRankDelay(Tick cmd_at) override;
1221 * Select read command to issue asynchronously
1223 void chooseRead(MemPacketQueue& queue);
1226 * Function to calulate unloaded access latency
1228 Tick accessLatency() const override { return (tREAD + tSEND); }
1231 * Check if the write response queue has reached defined threshold
1233 * @param Return true if full
1236 writeRespQueueFull() const
1238 return writeRespQueue.size() == maxPendingWrites;
1242 readsWaitingToIssue() const
1244 return ((numReadsToIssue != 0) &&
1245 (numPendingReads < maxPendingReads));
1249 * Actually do the burst and update stats.
1251 * @param pkt The packet created from the outside world pkt
1252 * @param next_burst_at Minimum bus timing requirement from controller
1253 * @return pair, tick when current burst is issued and
1254 * tick when next burst can issue
1256 std::pair<Tick, Tick>
1257 doBurstAccess(MemPacket* pkt, Tick next_burst_at);
1259 NVMInterface(const NVMInterfaceParams &_p);
1262 #endif //__MEM_INTERFACE_HH__