src/mem/noncoherent_bus.cc

   1 /*
   2  * Copyright (c) 2011-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  *          Andreas Hansson
  42  *          William Wang
  43  */
  44
  45 /**
  46  * @file
  47  * Definition of a bus object.
  48  */
  49
  50 #include "base/misc.hh"
  51 #include "base/trace.hh"
  52 #include "debug/Bus.hh"
  53 #include "debug/BusAddrRanges.hh"
  54 #include "debug/NoncoherentBus.hh"
  55 #include "mem/noncoherent_bus.hh"
  56
  57 NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
  58     : BaseBus(p), reqLayer(*this, ".reqLayer", p->clock),
  59       respLayer(*this, ".respLayer", p->clock)
  60 {
  61     // create the ports based on the size of the master and slave
  62     // vector ports, and the presence of the default port, the ports
  63     // are enumerated starting from zero
  64     for (int i = 0; i < p->port_master_connection_count; ++i) {
  65         std::string portName = csprintf("%s.master[%d]", name(), i);
  66         MasterPort* bp = new NoncoherentBusMasterPort(portName, *this, i);
  67         masterPorts.push_back(bp);
  68     }
  69
  70     // see if we have a default slave device connected and if so add
  71     // our corresponding master port
  72     if (p->port_default_connection_count) {
  73         defaultPortID = masterPorts.size();
  74         std::string portName = name() + ".default";
  75         MasterPort* bp = new NoncoherentBusMasterPort(portName, *this,
  76                                                       defaultPortID);
  77         masterPorts.push_back(bp);
  78     }
  79
  80     // create the slave ports, once again starting at zero
  81     for (int i = 0; i < p->port_slave_connection_count; ++i) {
  82         std::string portName = csprintf("%s.slave[%d]", name(), i);
  83         SlavePort* bp = new NoncoherentBusSlavePort(portName, *this, i);
  84         slavePorts.push_back(bp);
  85     }
  86
  87     clearPortCache();
  88 }
  89
  90 bool
  91 NoncoherentBus::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
  92 {
  93     // determine the source port based on the id
  94     SlavePort *src_port = slavePorts[slave_port_id];
  95
  96     // we should never see express snoops on a non-coherent bus
  97     assert(!pkt->isExpressSnoop());
  98
  99     // test if the bus should be considered occupied for the current
 100     // port
 101     if (!reqLayer.tryTiming(src_port)) {
 102         DPRINTF(NoncoherentBus, "recvTimingReq: src %s %s 0x%x BUSY\n",
 103                 src_port->name(), pkt->cmdString(), pkt->getAddr());
 104         return false;
 105     }
 106
 107     DPRINTF(NoncoherentBus, "recvTimingReq: src %s %s 0x%x\n",
 108             src_port->name(), pkt->cmdString(), pkt->getAddr());
 109
 110     // set the source port for routing of the response
 111     pkt->setSrc(slave_port_id);
 112
 113     Tick headerFinishTime = calcPacketTiming(pkt);
 114     Tick packetFinishTime = pkt->finishTime;
 115
 116     // since it is a normal request, determine the destination
 117     // based on the address and attempt to send the packet
 118     bool success = masterPorts[findPort(pkt->getAddr())]->sendTimingReq(pkt);
 119
 120     if (!success)  {
 121         // inhibited packets should never be forced to retry
 122         assert(!pkt->memInhibitAsserted());
 123
 124         DPRINTF(NoncoherentBus, "recvTimingReq: src %s %s 0x%x RETRY\n",
 125                 src_port->name(), pkt->cmdString(), pkt->getAddr());
 126
 127         reqLayer.failedTiming(src_port, headerFinishTime);
 128
 129         return false;
 130     }
 131
 132     reqLayer.succeededTiming(packetFinishTime);
 133
 134     return true;
 135 }
 136
 137 bool
 138 NoncoherentBus::recvTimingResp(PacketPtr pkt, PortID master_port_id)
 139 {
 140     // determine the source port based on the id
 141     MasterPort *src_port = masterPorts[master_port_id];
 142
 143     // test if the bus should be considered occupied for the current
 144     // port
 145     if (!respLayer.tryTiming(src_port)) {
 146         DPRINTF(NoncoherentBus, "recvTimingResp: src %s %s 0x%x BUSY\n",
 147                 src_port->name(), pkt->cmdString(), pkt->getAddr());
 148         return false;
 149     }
 150
 151     DPRINTF(NoncoherentBus, "recvTimingResp: src %s %s 0x%x\n",
 152             src_port->name(), pkt->cmdString(), pkt->getAddr());
 153
 154     calcPacketTiming(pkt);
 155     Tick packetFinishTime = pkt->finishTime;
 156
 157     // send the packet to the destination through one of our slave
 158     // ports, as determined by the destination field
 159     bool success M5_VAR_USED = slavePorts[pkt->getDest()]->sendTimingResp(pkt);
 160
 161     // currently it is illegal to block responses... can lead to
 162     // deadlock
 163     assert(success);
 164
 165     respLayer.succeededTiming(packetFinishTime);
 166
 167     return true;
 168 }
 169
 170 void
 171 NoncoherentBus::recvRetry()
 172 {
 173     // responses never block on forwarding them, so the retry will
 174     // always be coming from a port to which we tried to forward a
 175     // request
 176     reqLayer.recvRetry();
 177 }
 178
 179 Tick
 180 NoncoherentBus::recvAtomic(PacketPtr pkt, PortID slave_port_id)
 181 {
 182     DPRINTF(NoncoherentBus, "recvAtomic: packet src %s addr 0x%x cmd %s\n",
 183             slavePorts[slave_port_id]->name(), pkt->getAddr(),
 184             pkt->cmdString());
 185
 186     // determine the destination port
 187     PortID dest_id = findPort(pkt->getAddr());
 188
 189     // forward the request to the appropriate destination
 190     Tick response_latency = masterPorts[dest_id]->sendAtomic(pkt);
 191
 192     pkt->finishTime = curTick() + response_latency;
 193     return response_latency;
 194 }
 195
 196 void
 197 NoncoherentBus::recvFunctional(PacketPtr pkt, PortID slave_port_id)
 198 {
 199     if (!pkt->isPrint()) {
 200         // don't do DPRINTFs on PrintReq as it clutters up the output
 201         DPRINTF(NoncoherentBus,
 202                 "recvFunctional: packet src %s addr 0x%x cmd %s\n",
 203                 slavePorts[slave_port_id]->name(), pkt->getAddr(),
 204                 pkt->cmdString());
 205     }
 206
 207     // determine the destination port
 208     PortID dest_id = findPort(pkt->getAddr());
 209
 210     // forward the request to the appropriate destination
 211     masterPorts[dest_id]->sendFunctional(pkt);
 212 }
 213
 214 unsigned int
 215 NoncoherentBus::drain(DrainManager *dm)
 216 {
 217     // sum up the individual layers
 218     return reqLayer.drain(dm) + respLayer.drain(dm);
 219 }
 220
 221 NoncoherentBus*
 222 NoncoherentBusParams::create()
 223 {
 224     return new NoncoherentBus(this);
 225 }