src/mem/noncoherent_bus.hh

   1 /*
   2  * Copyright (c) 2011-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  *          William Wang
  44  */
  45
  46 /**
  47  * @file
  48  * Declaration of a non-coherent bus.
  49  */
  50
  51 #ifndef __MEM_NONCOHERENT_BUS_HH__
  52 #define __MEM_NONCOHERENT_BUS_HH__
  53
  54 #include "mem/bus.hh"
  55 #include "params/NoncoherentBus.hh"
  56
  57 /**
  58  * A non-coherent bus connects a number of non-snooping masters and
  59  * slaves, and routes the request and response packets based on the
  60  * address. The request packets issued by the master connected to a
  61  * non-coherent bus could still snoop in caches attached to a coherent
  62  * bus, as is the case with the I/O bus and memory bus in most system
  63  * configurations. No snoops will, however, reach any master on the
  64  * non-coherent bus itself.
  65  *
  66  * The non-coherent bus can be used as a template for modelling PCI,
  67  * PCIe, and non-coherent AMBA and OCP buses, and is typically used
  68  * for the I/O buses.
  69  */
  70 class NoncoherentBus : public BaseBus
  71 {
  72
  73   protected:
  74
  75     /**
  76      * Declare the layers of this bus, one vector for requests and one
  77      * for responses.
  78      */
  79     typedef Layer<SlavePort,MasterPort> ReqLayer;
  80     typedef Layer<MasterPort,SlavePort> RespLayer;
  81     std::vector<ReqLayer*> reqLayers;
  82     std::vector<RespLayer*> respLayers;
  83
  84     /**
  85      * Declaration of the non-coherent bus slave port type, one will
  86      * be instantiated for each of the master ports connecting to the
  87      * bus.
  88      */
  89     class NoncoherentBusSlavePort : public SlavePort
  90     {
  91       private:
  92
  93         /** A reference to the bus to which this port belongs. */
  94         NoncoherentBus &bus;
  95
  96       public:
  97
  98         NoncoherentBusSlavePort(const std::string &_name,
  99                                 NoncoherentBus &_bus, PortID _id)
 100             : SlavePort(_name, &_bus, _id), bus(_bus)
 101         { }
 102
 103       protected:
 104
 105         /**
 106          * When receiving a timing request, pass it to the bus.
 107          */
 108         virtual bool recvTimingReq(PacketPtr pkt)
 109         { return bus.recvTimingReq(pkt, id); }
 110
 111         /**
 112          * When receiving an atomic request, pass it to the bus.
 113          */
 114         virtual Tick recvAtomic(PacketPtr pkt)
 115         { return bus.recvAtomic(pkt, id); }
 116
 117         /**
 118          * When receiving a functional request, pass it to the bus.
 119          */
 120         virtual void recvFunctional(PacketPtr pkt)
 121         { bus.recvFunctional(pkt, id); }
 122
 123         /**
 124          * When receiving a retry, pass it to the bus.
 125          */
 126         virtual void recvRetry()
 127         { panic("Bus slave ports always succeed and should never retry.\n"); }
 128
 129         /**
 130          * Return the union of all adress ranges seen by this bus.
 131          */
 132         virtual AddrRangeList getAddrRanges() const
 133         { return bus.getAddrRanges(); }
 134
 135     };
 136
 137     /**
 138      * Declaration of the bus master port type, one will be
 139      * instantiated for each of the slave ports connecting to the
 140      * bus.
 141      */
 142     class NoncoherentBusMasterPort : public MasterPort
 143     {
 144       private:
 145
 146         /** A reference to the bus to which this port belongs. */
 147         NoncoherentBus &bus;
 148
 149       public:
 150
 151         NoncoherentBusMasterPort(const std::string &_name,
 152                                  NoncoherentBus &_bus, PortID _id)
 153             : MasterPort(_name, &_bus, _id), bus(_bus)
 154         { }
 155
 156       protected:
 157
 158         /**
 159          * When receiving a timing response, pass it to the bus.
 160          */
 161         virtual bool recvTimingResp(PacketPtr pkt)
 162         { return bus.recvTimingResp(pkt, id); }
 163
 164         /** When reciving a range change from the peer port (at id),
 165             pass it to the bus. */
 166         virtual void recvRangeChange()
 167         { bus.recvRangeChange(id); }
 168
 169         /** When reciving a retry from the peer port (at id),
 170             pass it to the bus. */
 171         virtual void recvRetry()
 172         { bus.recvRetry(id); }
 173
 174     };
 175
 176     /** Function called by the port when the bus is recieving a Timing
 177       request packet.*/
 178     virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
 179
 180     /** Function called by the port when the bus is recieving a Timing
 181       response packet.*/
 182     virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
 183
 184     /** Timing function called by port when it is once again able to process
 185      * requests. */
 186     void recvRetry(PortID master_port_id);
 187
 188     /** Function called by the port when the bus is recieving a Atomic
 189       transaction.*/
 190     Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
 191
 192     /** Function called by the port when the bus is recieving a Functional
 193         transaction.*/
 194     void recvFunctional(PacketPtr pkt, PortID slave_port_id);
 195
 196   public:
 197
 198     NoncoherentBus(const NoncoherentBusParams *p);
 199
 200     virtual ~NoncoherentBus();
 201
 202     unsigned int drain(DrainManager *dm);
 203
 204     /**
 205      * stats
 206      */
 207     virtual void regStats();
 208     Stats::Scalar dataThroughBus;
 209 };
 210
 211 #endif //__MEM_NONCOHERENT_BUS_HH__