src/mem/noncoherent_bus.hh

   1 /*
   2  * Copyright (c) 2011-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  *          William Wang
  44  */
  45
  46 /**
  47  * @file
  48  * Declaration of a non-coherent bus.
  49  */
  50
  51 #ifndef __MEM_NONCOHERENT_BUS_HH__
  52 #define __MEM_NONCOHERENT_BUS_HH__
  53
  54 #include "mem/bus.hh"
  55 #include "params/NoncoherentBus.hh"
  56
  57 /**
  58  * A non-coherent bus connects a number of non-snooping masters and
  59  * slaves, and routes the request and response packets based on the
  60  * address. The request packets issued by the master connected to a
  61  * non-coherent bus could still snoop in caches attached to a coherent
  62  * bus, as is the case with the I/O bus and memory bus in most system
  63  * configurations. No snoops will, however, reach any master on the
  64  * non-coherent bus itself.
  65  *
  66  * The non-coherent bus can be used as a template for modelling PCI,
  67  * PCIe, and non-coherent AMBA and OCP buses, and is typically used
  68  * for the I/O buses.
  69  */
  70 class NoncoherentBus : public BaseBus
  71 {
  72
  73   protected:
  74
  75     /**
  76      * Declare the single layer of this bus.
  77      */
  78     Layer layer;
  79
  80     /**
  81      * Declaration of the non-coherent bus slave port type, one will
  82      * be instantiated for each of the master ports connecting to the
  83      * bus.
  84      */
  85     class NoncoherentBusSlavePort : public SlavePort
  86     {
  87       private:
  88
  89         /** A reference to the bus to which this port belongs. */
  90         NoncoherentBus &bus;
  91
  92       public:
  93
  94         NoncoherentBusSlavePort(const std::string &_name,
  95                                 NoncoherentBus &_bus, PortID _id)
  96             : SlavePort(_name, &_bus, _id), bus(_bus)
  97         { }
  98
  99       protected:
 100
 101         /**
 102          * When receiving a timing request, pass it to the bus.
 103          */
 104         virtual bool recvTimingReq(PacketPtr pkt)
 105         { return bus.recvTimingReq(pkt, id); }
 106
 107         /**
 108          * When receiving an atomic request, pass it to the bus.
 109          */
 110         virtual Tick recvAtomic(PacketPtr pkt)
 111         { return bus.recvAtomic(pkt, id); }
 112
 113         /**
 114          * When receiving a functional request, pass it to the bus.
 115          */
 116         virtual void recvFunctional(PacketPtr pkt)
 117         { bus.recvFunctional(pkt, id); }
 118
 119         /**
 120          * When receiving a retry, pass it to the bus.
 121          */
 122         virtual void recvRetry()
 123         { panic("Bus slave ports always succeed and should never retry.\n"); }
 124
 125         /**
 126          * Return the union of all adress ranges seen by this bus.
 127          */
 128         virtual AddrRangeList getAddrRanges() const
 129         { return bus.getAddrRanges(); }
 130
 131         /**
 132          * Get the maximum block size as seen by the bus.
 133          */
 134         virtual unsigned deviceBlockSize() const
 135         { return bus.findBlockSize(); }
 136
 137     };
 138
 139     /**
 140      * Declaration of the bus master port type, one will be
 141      * instantiated for each of the slave ports connecting to the
 142      * bus.
 143      */
 144     class NoncoherentBusMasterPort : public MasterPort
 145     {
 146       private:
 147
 148         /** A reference to the bus to which this port belongs. */
 149         NoncoherentBus &bus;
 150
 151       public:
 152
 153         NoncoherentBusMasterPort(const std::string &_name,
 154                                  NoncoherentBus &_bus, PortID _id)
 155             : MasterPort(_name, &_bus, _id), bus(_bus)
 156         { }
 157
 158       protected:
 159
 160         /**
 161          * When receiving a timing response, pass it to the bus.
 162          */
 163         virtual bool recvTimingResp(PacketPtr pkt)
 164         { return bus.recvTimingResp(pkt, id); }
 165
 166         /** When reciving a range change from the peer port (at id),
 167             pass it to the bus. */
 168         virtual void recvRangeChange()
 169         { bus.recvRangeChange(id); }
 170
 171         /** When reciving a retry from the peer port (at id),
 172             pass it to the bus. */
 173         virtual void recvRetry()
 174         { bus.recvRetry(); }
 175
 176         /**
 177          * Get the maximum block size as seen by the bus.
 178          */
 179         virtual unsigned deviceBlockSize() const
 180         { return bus.findBlockSize(); }
 181
 182     };
 183
 184     /** Function called by the port when the bus is recieving a Timing
 185       request packet.*/
 186     virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
 187
 188     /** Function called by the port when the bus is recieving a Timing
 189       response packet.*/
 190     virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
 191
 192     /** Timing function called by port when it is once again able to process
 193      * requests. */
 194     void recvRetry();
 195
 196     /** Function called by the port when the bus is recieving a Atomic
 197       transaction.*/
 198     Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
 199
 200     /** Function called by the port when the bus is recieving a Functional
 201         transaction.*/
 202     void recvFunctional(PacketPtr pkt, PortID slave_port_id);
 203
 204   public:
 205
 206     NoncoherentBus(const NoncoherentBusParams *p);
 207
 208     unsigned int drain(Event *de);
 209
 210 };
 211
 212 #endif //__MEM_NONCOHERENT_BUS_HH__