src/mem/noncoherent_bus.hh

   1 /*
   2  * Copyright (c) 2011-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  *          William Wang
  44  */
  45
  46 /**
  47  * @file
  48  * Declaration of a non-coherent bus.
  49  */
  50
  51 #ifndef __MEM_NONCOHERENT_BUS_HH__
  52 #define __MEM_NONCOHERENT_BUS_HH__
  53
  54 #include "mem/bus.hh"
  55 #include "params/NoncoherentBus.hh"
  56
  57 /**
  58  * A non-coherent bus connects a number of non-snooping masters and
  59  * slaves, and routes the request and response packets based on the
  60  * address. The request packets issued by the master connected to a
  61  * non-coherent bus could still snoop in caches attached to a coherent
  62  * bus, as is the case with the I/O bus and memory bus in most system
  63  * configurations. No snoops will, however, reach any master on the
  64  * non-coherent bus itself.
  65  *
  66  * The non-coherent bus can be used as a template for modelling PCI,
  67  * PCIe, and non-coherent AMBA and OCP buses, and is typically used
  68  * for the I/O buses.
  69  */
  70 class NoncoherentBus : public BaseBus
  71 {
  72
  73   protected:
  74
  75     /**
  76      * Declaration of the non-coherent bus slave port type, one will
  77      * be instantiated for each of the master ports connecting to the
  78      * bus.
  79      */
  80     class NoncoherentBusSlavePort : public SlavePort
  81     {
  82       private:
  83
  84         /** A reference to the bus to which this port belongs. */
  85         NoncoherentBus &bus;
  86
  87       public:
  88
  89         NoncoherentBusSlavePort(const std::string &_name,
  90                                 NoncoherentBus &_bus, PortID _id)
  91             : SlavePort(_name, &_bus, _id), bus(_bus)
  92         { }
  93
  94       protected:
  95
  96         /**
  97          * When receiving a timing request, pass it to the bus.
  98          */
  99         virtual bool recvTimingReq(PacketPtr pkt)
 100         { return bus.recvTimingReq(pkt, id); }
 101
 102         /**
 103          * When receiving an atomic request, pass it to the bus.
 104          */
 105         virtual Tick recvAtomic(PacketPtr pkt)
 106         { return bus.recvAtomic(pkt, id); }
 107
 108         /**
 109          * When receiving a functional request, pass it to the bus.
 110          */
 111         virtual void recvFunctional(PacketPtr pkt)
 112         { bus.recvFunctional(pkt, id); }
 113
 114         /**
 115          * When receiving a retry, pass it to the bus.
 116          */
 117         virtual void recvRetry()
 118         { panic("Bus slave ports always succeed and should never retry.\n"); }
 119
 120         /**
 121          * Return the union of all adress ranges seen by this bus.
 122          */
 123         virtual AddrRangeList getAddrRanges()
 124         { return bus.getAddrRanges(); }
 125
 126         /**
 127          * Get the maximum block size as seen by the bus.
 128          */
 129         virtual unsigned deviceBlockSize() const
 130         { return bus.findBlockSize(); }
 131
 132     };
 133
 134     /**
 135      * Declaration of the bus master port type, one will be
 136      * instantiated for each of the slave ports connecting to the
 137      * bus.
 138      */
 139     class NoncoherentBusMasterPort : public MasterPort
 140     {
 141       private:
 142
 143         /** A reference to the bus to which this port belongs. */
 144         NoncoherentBus &bus;
 145
 146       public:
 147
 148         NoncoherentBusMasterPort(const std::string &_name,
 149                                  NoncoherentBus &_bus, PortID _id)
 150             : MasterPort(_name, &_bus, _id), bus(_bus)
 151         { }
 152
 153       protected:
 154
 155         /**
 156          * When receiving a timing response, pass it to the bus.
 157          */
 158         virtual bool recvTimingResp(PacketPtr pkt)
 159         { return bus.recvTimingResp(pkt, id); }
 160
 161         /** When reciving a range change from the peer port (at id),
 162             pass it to the bus. */
 163         virtual void recvRangeChange()
 164         { bus.recvRangeChange(id); }
 165
 166         /** When reciving a retry from the peer port (at id),
 167             pass it to the bus. */
 168         virtual void recvRetry()
 169         { bus.recvRetry(); }
 170
 171         /**
 172          * Get the maximum block size as seen by the bus.
 173          */
 174         virtual unsigned deviceBlockSize() const
 175         { return bus.findBlockSize(); }
 176
 177     };
 178
 179     /** Function called by the port when the bus is recieving a Timing
 180       request packet.*/
 181     virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
 182
 183     /** Function called by the port when the bus is recieving a Timing
 184       response packet.*/
 185     virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
 186
 187     /** Function called by the port when the bus is recieving a Atomic
 188       transaction.*/
 189     Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
 190
 191     /** Function called by the port when the bus is recieving a Functional
 192         transaction.*/
 193     void recvFunctional(PacketPtr pkt, PortID slave_port_id);
 194
 195   public:
 196
 197     NoncoherentBus(const NoncoherentBusParams *p);
 198
 199 };
 200
 201 #endif //__MEM_NONCOHERENT_BUS_HH__