src/mem/noncoherent_xbar.cc

   1 /*
   2  * Copyright (c) 2011-2015, 2018-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /**
  42  * @file
  43  * Definition of a non-coherent crossbar object.
  44  */
  45
  46 #include "mem/noncoherent_xbar.hh"
  47
  48 #include "base/logging.hh"
  49 #include "base/trace.hh"
  50 #include "debug/NoncoherentXBar.hh"
  51 #include "debug/XBar.hh"
  52
  53 NoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams &p)
  54     : BaseXBar(p)
  55 {
  56     // create the ports based on the size of the memory-side port and
  57     // CPU-side port vector ports, and the presence of the default port,
  58     // the ports are enumerated starting from zero
  59     for (int i = 0; i < p.port_mem_side_ports_connection_count; ++i) {
  60         std::string portName = csprintf("%s.mem_side_port[%d]", name(), i);
  61         RequestPort* bp = new NoncoherentXBarRequestPort(portName, *this, i);
  62         memSidePorts.push_back(bp);
  63         reqLayers.push_back(new ReqLayer(*bp, *this,
  64                                          csprintf("reqLayer%d", i)));
  65     }
  66
  67     // see if we have a default CPU-side-port device connected and if so add
  68     // our corresponding memory-side port
  69     if (p.port_default_connection_count) {
  70         defaultPortID = memSidePorts.size();
  71         std::string portName = name() + ".default";
  72         RequestPort* bp = new NoncoherentXBarRequestPort(portName, *this,
  73                                                       defaultPortID);
  74         memSidePorts.push_back(bp);
  75         reqLayers.push_back(new ReqLayer(*bp, *this, csprintf("reqLayer%d",
  76                                                               defaultPortID)));
  77     }
  78
  79     // create the CPU-side ports, once again starting at zero
  80     for (int i = 0; i < p.port_cpu_side_ports_connection_count; ++i) {
  81         std::string portName = csprintf("%s.cpu_side_ports[%d]", name(), i);
  82         QueuedResponsePort* bp = new NoncoherentXBarResponsePort(portName,
  83                                                                 *this, i);
  84         cpuSidePorts.push_back(bp);
  85         respLayers.push_back(new RespLayer(*bp, *this,
  86                                            csprintf("respLayer%d", i)));
  87     }
  88 }
  89
  90 NoncoherentXBar::~NoncoherentXBar()
  91 {
  92     for (auto l: reqLayers)
  93         delete l;
  94     for (auto l: respLayers)
  95         delete l;
  96 }
  97
  98 bool
  99 NoncoherentXBar::recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id)
 100 {
 101     // determine the source port based on the id
 102     ResponsePort *src_port = cpuSidePorts[cpu_side_port_id];
 103
 104     // we should never see express snoops on a non-coherent crossbar
 105     assert(!pkt->isExpressSnoop());
 106
 107     // determine the destination based on the address
 108     PortID mem_side_port_id = findPort(pkt->getAddrRange());
 109
 110     // test if the layer should be considered occupied for the current
 111     // port
 112     if (!reqLayers[mem_side_port_id]->tryTiming(src_port)) {
 113         DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x BUSY\n",
 114                 src_port->name(), pkt->cmdString(), pkt->getAddr());
 115         return false;
 116     }
 117
 118     DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x\n",
 119             src_port->name(), pkt->cmdString(), pkt->getAddr());
 120
 121     // store size and command as they might be modified when
 122     // forwarding the packet
 123     unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
 124     unsigned int pkt_cmd = pkt->cmdToIndex();
 125
 126     // store the old header delay so we can restore it if needed
 127     Tick old_header_delay = pkt->headerDelay;
 128
 129     // a request sees the frontend and forward latency
 130     Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod();
 131
 132     // set the packet header and payload delay
 133     calcPacketTiming(pkt, xbar_delay);
 134
 135     // determine how long to be crossbar layer is busy
 136     Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
 137
 138     // before forwarding the packet (and possibly altering it),
 139     // remember if we are expecting a response
 140     const bool expect_response = pkt->needsResponse() &&
 141         !pkt->cacheResponding();
 142
 143     // since it is a normal request, attempt to send the packet
 144     bool success = memSidePorts[mem_side_port_id]->sendTimingReq(pkt);
 145
 146     if (!success)  {
 147         DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x RETRY\n",
 148                 src_port->name(), pkt->cmdString(), pkt->getAddr());
 149
 150         // restore the header delay as it is additive
 151         pkt->headerDelay = old_header_delay;
 152
 153         // occupy until the header is sent
 154         reqLayers[mem_side_port_id]->failedTiming(src_port,
 155                                                 clockEdge(Cycles(1)));
 156
 157         return false;
 158     }
 159
 160     // remember where to route the response to
 161     if (expect_response) {
 162         assert(routeTo.find(pkt->req) == routeTo.end());
 163         routeTo[pkt->req] = cpu_side_port_id;
 164     }
 165
 166     reqLayers[mem_side_port_id]->succeededTiming(packetFinishTime);
 167
 168     // stats updates
 169     pktCount[cpu_side_port_id][mem_side_port_id]++;
 170     pktSize[cpu_side_port_id][mem_side_port_id] += pkt_size;
 171     transDist[pkt_cmd]++;
 172
 173     return true;
 174 }
 175
 176 bool
 177 NoncoherentXBar::recvTimingResp(PacketPtr pkt, PortID mem_side_port_id)
 178 {
 179     // determine the source port based on the id
 180     RequestPort *src_port = memSidePorts[mem_side_port_id];
 181
 182     // determine the destination
 183     const auto route_lookup = routeTo.find(pkt->req);
 184     assert(route_lookup != routeTo.end());
 185     const PortID cpu_side_port_id = route_lookup->second;
 186     assert(cpu_side_port_id != InvalidPortID);
 187     assert(cpu_side_port_id < respLayers.size());
 188
 189     // test if the layer should be considered occupied for the current
 190     // port
 191     if (!respLayers[cpu_side_port_id]->tryTiming(src_port)) {
 192         DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x BUSY\n",
 193                 src_port->name(), pkt->cmdString(), pkt->getAddr());
 194         return false;
 195     }
 196
 197     DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x\n",
 198             src_port->name(), pkt->cmdString(), pkt->getAddr());
 199
 200     // store size and command as they might be modified when
 201     // forwarding the packet
 202     unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
 203     unsigned int pkt_cmd = pkt->cmdToIndex();
 204
 205     // a response sees the response latency
 206     Tick xbar_delay = responseLatency * clockPeriod();
 207
 208     // set the packet header and payload delay
 209     calcPacketTiming(pkt, xbar_delay);
 210
 211     // determine how long to be crossbar layer is busy
 212     Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
 213
 214     // send the packet through the destination CPU-side port, and pay for
 215     // any outstanding latency
 216     Tick latency = pkt->headerDelay;
 217     pkt->headerDelay = 0;
 218     cpuSidePorts[cpu_side_port_id]->schedTimingResp(pkt,
 219                                         curTick() + latency);
 220
 221     // remove the request from the routing table
 222     routeTo.erase(route_lookup);
 223
 224     respLayers[cpu_side_port_id]->succeededTiming(packetFinishTime);
 225
 226     // stats updates
 227     pktCount[cpu_side_port_id][mem_side_port_id]++;
 228     pktSize[cpu_side_port_id][mem_side_port_id] += pkt_size;
 229     transDist[pkt_cmd]++;
 230
 231     return true;
 232 }
 233
 234 void
 235 NoncoherentXBar::recvReqRetry(PortID mem_side_port_id)
 236 {
 237     // responses never block on forwarding them, so the retry will
 238     // always be coming from a port to which we tried to forward a
 239     // request
 240     reqLayers[mem_side_port_id]->recvRetry();
 241 }
 242
 243 Tick
 244 NoncoherentXBar::recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id,
 245                                     MemBackdoorPtr *backdoor)
 246 {
 247     DPRINTF(NoncoherentXBar, "recvAtomic: packet src %s addr 0x%x cmd %s\n",
 248             cpuSidePorts[cpu_side_port_id]->name(), pkt->getAddr(),
 249             pkt->cmdString());
 250
 251     unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
 252     unsigned int pkt_cmd = pkt->cmdToIndex();
 253
 254     // determine the destination port
 255     PortID mem_side_port_id = findPort(pkt->getAddrRange());
 256
 257     // stats updates for the request
 258     pktCount[cpu_side_port_id][mem_side_port_id]++;
 259     pktSize[cpu_side_port_id][mem_side_port_id] += pkt_size;
 260     transDist[pkt_cmd]++;
 261
 262     // forward the request to the appropriate destination
 263     auto mem_side_port = memSidePorts[mem_side_port_id];
 264     Tick response_latency = backdoor ?
 265         mem_side_port->sendAtomicBackdoor(pkt, *backdoor) :
 266         mem_side_port->sendAtomic(pkt);
 267
 268     // add the response data
 269     if (pkt->isResponse()) {
 270         pkt_size = pkt->hasData() ? pkt->getSize() : 0;
 271         pkt_cmd = pkt->cmdToIndex();
 272
 273         // stats updates
 274         pktCount[cpu_side_port_id][mem_side_port_id]++;
 275         pktSize[cpu_side_port_id][mem_side_port_id] += pkt_size;
 276         transDist[pkt_cmd]++;
 277     }
 278
 279     // @todo: Not setting first-word time
 280     pkt->payloadDelay = response_latency;
 281     return response_latency;
 282 }
 283
 284 void
 285 NoncoherentXBar::recvFunctional(PacketPtr pkt, PortID cpu_side_port_id)
 286 {
 287     if (!pkt->isPrint()) {
 288         // don't do DPRINTFs on PrintReq as it clutters up the output
 289         DPRINTF(NoncoherentXBar,
 290                 "recvFunctional: packet src %s addr 0x%x cmd %s\n",
 291                 cpuSidePorts[cpu_side_port_id]->name(), pkt->getAddr(),
 292                 pkt->cmdString());
 293     }
 294
 295     // since our CPU-side ports are queued ports we need to check them as well
 296     for (const auto& p : cpuSidePorts) {
 297         // if we find a response that has the data, then the
 298         // downstream caches/memories may be out of date, so simply stop
 299         // here
 300         if (p->trySatisfyFunctional(pkt)) {
 301             if (pkt->needsResponse())
 302                 pkt->makeResponse();
 303             return;
 304         }
 305     }
 306
 307     // determine the destination port
 308     PortID dest_id = findPort(pkt->getAddrRange());
 309
 310     // forward the request to the appropriate destination
 311     memSidePorts[dest_id]->sendFunctional(pkt);
 312 }