src/mem/noncoherent_xbar.hh

   1 /*
   2  * Copyright (c) 2011-2015, 2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
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  20  * notice, this list of conditions and the following disclaimer;
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  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /**
  42  * @file
  43  * Declaration of a non-coherent crossbar.
  44  */
  45
  46 #ifndef __MEM_NONCOHERENT_XBAR_HH__
  47 #define __MEM_NONCOHERENT_XBAR_HH__
  48
  49 #include "mem/xbar.hh"
  50 #include "params/NoncoherentXBar.hh"
  51
  52 /**
  53  * A non-coherent crossbar connects a number of non-snooping memory-side ports
  54  * and cpu_sides, and routes the request and response packets based on
  55  * the address. The request packets issued by the memory-side port connected to
  56  * a non-coherent crossbar could still snoop in caches attached to a
  57  * coherent crossbar, as is the case with the I/O bus and memory bus
  58  * in most system configurations. No snoops will, however, reach any
  59  * memory-side port on the non-coherent crossbar itself.
  60  *
  61  * The non-coherent crossbar can be used as a template for modelling
  62  * PCIe, and non-coherent AMBA and OCP buses, and is typically used
  63  * for the I/O buses.
  64  */
  65 class NoncoherentXBar : public BaseXBar
  66 {
  67
  68   protected:
  69
  70     /**
  71      * Declare the layers of this crossbar, one vector for requests
  72      * and one for responses.
  73      */
  74     std::vector<ReqLayer*> reqLayers;
  75     std::vector<RespLayer*> respLayers;
  76
  77     /**
  78      * Declaration of the non-coherent crossbar CPU-side port type, one
  79      * will be instantiated for each of the memory-side ports connecting to
  80      * the crossbar.
  81      */
  82     class NoncoherentXBarResponsePort : public QueuedResponsePort
  83     {
  84       private:
  85
  86         /** A reference to the crossbar to which this port belongs. */
  87         NoncoherentXBar &xbar;
  88
  89         /** A normal packet queue used to store responses. */
  90         RespPacketQueue queue;
  91
  92       public:
  93
  94         NoncoherentXBarResponsePort(const std::string &_name,
  95                                 NoncoherentXBar &_xbar, PortID _id)
  96             : QueuedResponsePort(_name, &_xbar, queue, _id), xbar(_xbar),
  97               queue(_xbar, *this)
  98         { }
  99
 100       protected:
 101
 102         bool
 103         recvTimingReq(PacketPtr pkt) override
 104         {
 105             return xbar.recvTimingReq(pkt, id);
 106         }
 107
 108         Tick
 109         recvAtomic(PacketPtr pkt) override
 110         {
 111             return xbar.recvAtomicBackdoor(pkt, id);
 112         }
 113
 114         Tick
 115         recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
 116         {
 117             return xbar.recvAtomicBackdoor(pkt, id, &backdoor);
 118         }
 119
 120         void
 121         recvFunctional(PacketPtr pkt) override
 122         {
 123             xbar.recvFunctional(pkt, id);
 124         }
 125
 126         AddrRangeList
 127         getAddrRanges() const override
 128         {
 129             return xbar.getAddrRanges();
 130         }
 131     };
 132
 133     /**
 134      * Declaration of the crossbar memory-side port type, one will be
 135      * instantiated for each of the CPU-side ports connecting to the
 136      * crossbar.
 137      */
 138     class NoncoherentXBarRequestPort : public RequestPort
 139     {
 140       private:
 141
 142         /** A reference to the crossbar to which this port belongs. */
 143         NoncoherentXBar &xbar;
 144
 145       public:
 146
 147         NoncoherentXBarRequestPort(const std::string &_name,
 148                                  NoncoherentXBar &_xbar, PortID _id)
 149             : RequestPort(_name, &_xbar, _id), xbar(_xbar)
 150         { }
 151
 152       protected:
 153
 154         bool
 155         recvTimingResp(PacketPtr pkt) override
 156         {
 157             return xbar.recvTimingResp(pkt, id);
 158         }
 159
 160         void
 161         recvRangeChange() override
 162         {
 163             xbar.recvRangeChange(id);
 164         }
 165
 166         void
 167         recvReqRetry() override
 168         {
 169             xbar.recvReqRetry(id);
 170         }
 171     };
 172
 173     virtual bool recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id);
 174     virtual bool recvTimingResp(PacketPtr pkt, PortID mem_side_port_id);
 175     void recvReqRetry(PortID mem_side_port_id);
 176     Tick recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id,
 177                             MemBackdoorPtr *backdoor=nullptr);
 178     void recvFunctional(PacketPtr pkt, PortID cpu_side_port_id);
 179
 180   public:
 181
 182     NoncoherentXBar(const NoncoherentXBarParams &p);
 183
 184     virtual ~NoncoherentXBar();
 185 };
 186
 187 #endif //__MEM_NONCOHERENT_XBAR_HH__